Screening method of center wafer for simulation modeling of semiconductor device

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a central wafer screening method for semiconductor device simulation modeling. Mapping test is carried out on the whole wafer, medians of various electrical parameters of devices with different sizes are obtained, each wafer is scored according to error absolute values of the electrical parameters and the corresponding medians, and finally the wafer with the highest score is the center wafer. According to the method, no wafer is omitted, the problem that the electrical parameters of the central wafer deviate from the median due to process fluctuation is solved, and assignment and screening are more typicality; the problem that devices of certain sizes and / or electrical parameters in the center wafer obtained through screening in an existing method greatly deviate from the median value of Mapping data is solved, and the accuracy of establishing a TCAD simulation model through the electrical performance of the center wafer is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a method for screening a central wafer for simulation modeling of semiconductor devices. Background Art

[0002] In the semiconductor manufacturing process, in order to evaluate the stability of the process, it is usually necessary to characterize the device performance on the test piece. The test piece is a wafer (Wafer), and each wafer has multiple identical chips (Die), and each chip contains a MOSFET (metal oxide semiconductor field effect transistor) device matrix with different width-to-length ratios (W / L) sizes. Due to the deviation of the preparation process, the electrical performance of MOSFET devices with the same width-to-length ratio size in different chips on the same wafer is different, including Mapping (wafer test data distribution map) data and Curve (curve) data. Among them, Mapping data includes electrical parameters such as linear region threshold voltage Vthlin, linear region current Idlin, linear region transconductance gmlin, saturation region threshold voltage Vthsat, saturation region current Idsat, and saturation region transconductance gmsat; Curve data includes IV and CV curves.

[0003] In order to establish a TCAD (Technology Computer Aided Design) simulation model for MOSFET devices, it is necessary to screen a central wafer (Golden Die) with typical electrical parameters and Curve data that can represent the manufacturing process. The commonly used screening method is to obtain the Mapping data of devices of different sizes of all Dies on the entire wafer, that is, the electrical parameters of all devices, and then select the wafers whose electrical parameters are close to the median of the Mapping data as the Golden Die. However, when the process fluctuations are large, the electrical performance of devices in different wafers varies greatly. This causes the screened Golden Die to deviate from the median in some electrical parameters and Curve data, and cannot reflect the typical electrical performance of the device under process conditions, which seriously affects the accuracy and applicability of device simulation modeling. Summary of the invention

[0004] In view of the above-mentioned problems or shortcomings, the present invention aims to provide a method for screening central chips for semiconductor device simulation modeling to ensure that the electrical parameters of devices of different sizes in the screened Golden Die are close to the median of the Mapping data, so that the device TCAD model established based on the electrical parameters and Curve parameters can more accurately reflect the typical values ​​of the manufacturing process.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A method for screening a center wafer for semiconductor device simulation modeling comprises the following steps:

[0007] Step 1: Conduct electrical parameter tests on MOSFET devices with different width-to-length ratios (W / L) in each chip on a single wafer.

[0008] Step 2: Based on the test results of step 1, calculate the median values ​​of various electrical parameter values ​​corresponding to each MOSFET device with different width-to-length ratio W / L of all wafers.

[0009] Step 3: For a MOSFET device with a width-to-length ratio of W1 / L1 (one of W / L), calculate the absolute value of the error between each electrical parameter value of each chip and the corresponding median.

[0010] Step 4: For W1 / L1 size MOSFET devices, under each electrical parameter, assign scores to the first N (N≥3) chips whose absolute error values ​​are arranged from small to large.

[0011] Step 5: Add up the scores of all electrical parameters of each scored chip obtained in step 4 to obtain the score of each chip under the W1 / L1 size device.

[0012] Step 6: Repeat steps 3 to 5 to obtain the score of each wafer at each width-to-length ratio W / L.

[0013] Step 7: Add up the scores of devices with different width-to-length ratios (W / L) in each chip to obtain the total score of each chip. The chip with the highest total score is the center chip.

[0014] Furthermore, the electrical parameters in step 1 include: a linear region threshold voltage Vthlin, a linear region current Idlin, a linear region transconductance gmlin, a saturation region threshold voltage Vthsat, a saturation region current Idsat, and a saturation region transconductance gmsat.

[0015] Furthermore, the scoring in step 4 is specifically as follows: the first N chips arranged in ascending order of absolute value of electrical parameter error are scored respectively, with a total of N scores, namely P1, P2, ..., PN.

[0016] Furthermore, in step 4, the N scores satisfy P1>P2>…>PN.

[0017] Furthermore, the electrical parameter scores of each chip in step 5 include the accumulation of the chip's Vthlin score, Idlin score, gmlin score, Vthsat score, Idsat score and gmsat score.

[0018] Furthermore, repeating steps 3 to 5 in step 6 includes first completing steps 3 to 5 on the first W / L size device, and then repeating the operation on the second W / L size device until the operation of all W / L size devices is completed; or after completing step 3 on all W / L size devices, step 4 is performed on all W / L size devices, and finally step 5 is performed on all W / L size devices.

[0019] Furthermore, the medians of the various electrical parameter values ​​calculated in step 2 include the medians of Vthlin, Idlin, gmlin, Vthsat, Idsat, and gmsat calculated respectively under different width-to-length ratios W / L.

[0020] The present invention assigns points to all MOSFET devices of different width-to-length ratios W / L in each chip on a single wafer in a specific manner, and then obtains the total score of each chip on the single wafer, and selects the chip with the highest total score as the center chip. Although there is heterogeneity of wafer materials in a single wafer, and the current chip preparation technology will definitely lead to deviations in the characteristics of each chip on a single wafer due to batch production (the positions of each chip on a wafer are different); the present invention does not omit any wafer, and although there are deviations in the characteristics of each chip on a single wafer, the present invention still considers the premise that the deviation will not be too large, and the scoring method is more typical. The present invention comprehensively considers all devices with width-to-length ratios W / L and multiple electrical parameters on each chip, avoiding the problem that certain size devices and / or electrical parameters in the screened center chip deviate greatly from the median value of the Mapping data, so the electrical performance of the final selected center chip is more typical.

[0021] In summary, the method for screening center wafers for semiconductor device simulation modeling proposed in the present invention performs a Mapping test on the entire wafer to obtain the median of various electrical parameters of devices of different sizes, and scores each wafer according to the absolute value of the error between the electrical parameter and the corresponding median, and the wafer with the highest final score is the center wafer. This method improves the screening of center wafers, and the electrical parameters of devices of different sizes on the center wafer obtained are close to the median, overcoming the problem of the center wafer electrical parameters deviating from the median due to process fluctuations, and improving the accuracy of establishing a TCAD simulation model using the electrical performance of the center wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a flow chart of the present invention.

[0023] Figure 2 Matrix of W / L dimensions of all MOSFET devices in the examples.

[0024] Figure 3 It is the score of the example wafer in the device with a width-to-length ratio of W1 / L1.

[0025] Figure 4 The figure shows the comparison of the electrical parameter Vthlin of the Golden Die in the embodiment with the median of all the chips and the relative error.

[0026] Figure 5 The figure shows the comparison of the electrical parameter Idlin of the Golden Die in the embodiment with the median of all the wafers and the relative error.

[0027] Figure 6 The figure shows the comparison of the electrical parameter gmlin of the Golden Die in the embodiment with the median of all the wafers and the relative error.

[0028] Figure 7 The figure shows the comparison of the electrical parameter Vthsat of the Golden Die in the embodiment with the median of all the chips and the relative error.

[0029] Figure 8 The figure shows the comparison of the electrical parameter Idsat of the Golden Die in the embodiment with the median of all wafers and the relative error.

[0030] Fig. 9 The figure shows the comparison of the electrical parameter gmsat of the Golden Die in the embodiment with the median of all wafers and the relative error. DETAILED DESCRIPTION

[0031] The present invention is described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited to these embodiments.

[0032] A method for screening center wafers for semiconductor device simulation modeling, such as Figure 1 As shown, the following steps are included:

[0033] Step 1: Conduct electrical parameter tests on MOSFET devices with different width-to-length ratios (W / L) in each chip on the same wafer.

[0034] Specifically, the MOSFET devices with different width-to-length ratios W / L in this embodiment include: Figure 2 The W / L size matrix of MOSFET devices supported by the process shown.

[0035] The electrical parameters specifically include six types: linear region threshold voltage Vthlin, linear region current Idlin, linear region transconductance gmlin, saturation region threshold voltage Vthsat, saturation region current Idsat and saturation region transconductance gmsat.

[0036] Step 2: Based on the test results of step 1, calculate the median of the six electrical parameter values ​​corresponding to each MOSFET device with different width-to-length ratio W / L.

[0037] Specifically, in Figure 2 The medians of Vthlin, Idlin, gmlin, Vthsat, Idsat, and gmsat are calculated for 56 devices with different W / L sizes.

[0038] Step 3: For a device with a width-to-length ratio of W1 / L1, calculate the absolute value of the error between each electrical parameter value of each chip and the corresponding median.

[0039] Specifically, the absolute value of the error includes the absolute value of the difference between Vthlin and the corresponding median, the absolute value of the difference between Idlin and the corresponding median, the absolute value of the difference between gmlin and the corresponding median, the absolute value of the difference between Vthsat and the corresponding median, the absolute value of the difference between Idsat and the corresponding median, and the absolute value of the difference between gmsat and the corresponding median for each chip under the condition of a device with a width-to-length ratio of W1 / L1.

[0040] Step 4: For W1 / L1 size MOSFET devices, under each electrical parameter, assign scores to the first N (N≥3) chips whose absolute error values ​​are arranged from small to large.

[0041] In this embodiment, N=5, and the absolute values ​​of the errors of the six electrical parameters are arranged from small to large, that is, the first five chips in the order are assigned points. In this embodiment, the first five chips in the order are assigned 5 points, 4 points, 3 points, 2 points, and 1 point respectively. Figure 3 As shown, the scores of the wafer of the embodiment under the W1 / L1 size device, and the absolute value of each electrical parameter error is assigned 5 points, 4 points, 3 points, 2 points, and 1 point from small to large.

[0042] Step 5: Add up the scores of all electrical parameters of each scored chip obtained in step 4 to obtain the score of each chip under the W1 / L1 size device.

[0043] Specifically, adding the scores of the six electrical parameters includes adding the Vthlin score, Idlin score, gmlin score, Vthsat score, Idsat score, and gmsat score of the chip. Figure 3 , the scores of the wafers of the embodiment in the device with a width-to-length ratio of W1 / L1, the full score of each wafer in one size is 30 points (a total of 6 electrical parameters, each electrical parameter has a full score of 5 points), the minimum score is 0 points, and the wafer with a score of 0 points is not in Figure 3 Given in.

[0044] Step 6: Repeat steps 3 to 5 to obtain the score of each wafer at each width-to-length ratio W / L.

[0045] Specifically, after completing the calculation of the score of each chip under the W1 / L1 size device, the calculation of the next size device is carried out, for a total of 56 W / L size devices, and each chip finally obtains 56 scores.

[0046] Step 7: Add the scores of devices with different width-to-length ratios W / L in each wafer to obtain the total score of each wafer. In this embodiment, the 56 scores of each wafer obtained in step 6 are added to obtain the final score of each wafer. The wafer with the highest total score is the center wafer.

[0047] Figure 4-Figure 9 The comparison of various electrical parameters of Golden Die with the median of all wafers and the relative error (the smaller the relative error, the closer the electrical parameters of Golden Die are to the median of all wafers) obtained by screening in the embodiment correspond to the electrical parameters Vthlin, Idlin, gmlin, Vthsat, Idsat, and gmsat in sequence. The relative error calculation method is: first calculate the absolute value of the error between the median of all wafers and the center wafer of the electrical parameter, and then calculate the percentage of the ratio of the absolute value of the error to the median of all wafers. The maximum relative error occurs in the electrical parameter Vthsat, which is 4.79%.

[0048] This embodiment provides a method of using the electrical parameters of all sizes of MOSFET devices of all wafers on a wafer to screen out a center wafer that can represent the typical device characteristics of the entire wafer, providing a basis for TCAD simulation modeling of the device. The relative errors of all electrical parameters of the obtained center wafer are less than 5%, indicating that the center wafer can represent the typical device characteristics of the entire wafer and can be used for TCAD simulation modeling of the device.

[0049] It can be seen from the above embodiments that the present invention performs Mapping test on the whole wafer to obtain the median of various electrical parameters of devices of different sizes, and scores each chip according to the absolute value of the error between the electrical parameter and the corresponding median, and the chip with the highest final score is the center chip. The present invention does not miss any chip, overcomes the problem of the electrical parameters of the center chip deviating from the median due to process fluctuations, and the scoring screening is more typical; it avoids the problem that certain size devices and / or electrical parameters in the center chip obtained by the existing method deviate greatly from the median value of the Mapping data, and improves the accuracy of establishing the TCAD simulation model using the electrical performance of the center chip.

Claims

1. A method for screening center wafers for semiconductor device simulation modeling, characterized in that: The following steps are involved: Step 1, conducting electrical parameter tests on MOSFET devices with different width-to-length ratios W / L in each chip on a single wafer; Step 2: According to the test results of step 1, the median values ​​of various electrical parameter values ​​corresponding to each MOSFET device with different width-to-length ratio W / L are calculated; Step 3, for one of the MOSFET devices with a width-to-length ratio of W1 / L1, calculate the absolute value of the error between each electrical parameter value of each chip and the corresponding median; Step 4: For W1 / L1 size MOSFET devices, under each electrical parameter, the first N chips whose absolute error values ​​are arranged from small to large are scored, N ≥ 3; Step 5, sum up the scores of all electrical parameters of each scored wafer obtained in step 4 to obtain the score of each wafer under the W1 / L1 size device; Step 6: Repeat steps 3 to 5 to obtain the score of each wafer at each width-to-length ratio W / L. Step 7: Add up the scores of devices with different width-to-length ratios (W / L) in each chip to obtain the total score of each chip. The chip with the highest total score is the center chip.

2. The method for selecting a center wafer for semiconductor device simulation modeling according to claim 1, characterized in that: The electrical parameters in step 1 include: a linear region threshold voltage Vthlin, a linear region current Idlin, a linear region transconductance gmlin, a saturation region threshold voltage Vthsat, a saturation region current Idsat, and a saturation region transconductance gmsat.

3. The method for selecting a center wafer for semiconductor device simulation modeling according to claim 1, characterized in that: The scoring in step 4 is specifically as follows: the first N chips arranged in ascending order of absolute value of electrical parameter error are scored in sequence, with a total of N scores, P1, P2, ..., PN.

4. The method for selecting a center wafer for semiconductor device simulation modeling according to claim 1, characterized in that: In step 4, the N scores satisfy P1>P2>...>PN.

5. The method for selecting a center wafer for semiconductor device simulation modeling according to claim 1, characterized in that: The electrical parameter scores of each chip in step 5 include the cumulative Vthlin score, Idlin score, gmlin score, Vthsat score, Idsat score and gmsat score of the chip.

6. The method for selecting a center wafer for semiconductor device simulation modeling according to claim 1, characterized in that: Repeating steps 3 to 5 in step 6 includes first completing steps 3 to 5 for the first W / L size device, and then repeating the operation for the second W / L size device until the operation for all W / L size devices is completed; Alternatively, after completing step 3 for all W / L size devices, perform step 4 for all W / L size devices, and finally perform step 5 for all W / L size devices.

7. The method for selecting a center wafer for semiconductor device simulation modeling according to claim 1, characterized in that: The medians of the various electrical parameter values ​​calculated in step 2 include respectively calculating the medians of Vthlin, Idlin, gmlin, Vthsat, Idsat, and gmsat under different width-to-length ratios W / L.

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