A multi-stage cluster-type three-dimensional network-on-chip system for neuron network simulation

Abstract

The present application relates to a network system on chip, in particular to a kind of multi-level cluster type three-dimensional network system on chip for neuron network simulation.A kind of multi-level cluster type three-dimensional network system on chip for neuron network simulation includes multiple functional nodes, functional node includes vertically stacked routing chip and multiple computing chips, routing chip is arranged at the bottom of multiple computing chips;Computing chip includes processing core, first-level router, second-level router and higher level router, routing chip includes second-level router and higher level router, and the highest level router of computing chip is the same level with the highest level router of routing chip.The present application adopts multi-level cluster type three-dimensional network structure design on chip, and the connection distance between chip is shortened by three-dimensional stack in functional node interior, so as to reduce inter-chip data transmission delay, improve the computing efficiency of system.

Description

TECHNICAL FIELD

[0001] The present application relates to a network-on-chip system, in particular to a multi-level cluster type three-dimensional network-on-chip system for neuron network simulation. BACKGROUND

[0002] Neuromorphic systems for neuron network simulation are usually composed of multiple chips, and the efficiency of on-chip and inter-chip communication is one of the main factors affecting system performance. Network-on-chip technology is often used to solve such communication problems. In neuron network simulation, the processor cores of the network-on-chip can be regarded as neuron models, and the routing nodes are similar to the synapses of neurons. By interconnecting between routing nodes, the neuron network simulation can be completed by using network-on-chip technology. However, the current two-dimensional neuron network architecture is difficult to adapt to the needs of large-scale neuron network simulation, and cannot simultaneously simulate the local connection characteristics and global connection characteristics in the neuron network, and the scalability needs to be improved. The existing single-level parallel design of three-dimensional network-on-chip structure will produce resource competition and link congestion when facing large-scale neuron network calculation, and the simple three-dimensional stacking structure cannot meet the real-time needs of large-scale neuron simulation. Therefore, it is necessary to design an expandable neuron network simulation network-on-chip structure to reduce the delay of data transmission and improve the number of neurons that can be simulated. SUMMARY

[0003] The technical problem to be solved by the present application is to overcome the deficiencies in the prior art and provide a multi-level cluster type three-dimensional network-on-chip system for neuron network simulation.

[0004] The present application is implemented by the following technical solutions:

[0005] A multi-level cluster type three-dimensional network-on-chip system for neuron network simulation, the network-on-chip system comprising a plurality of functional nodes, the functional nodes comprising routing chips and a plurality of computing chips arranged vertically stacked, the routing chips are arranged at the bottom of the plurality of computing chips;

[0006] The computing chip comprises a processing core, a first-level router, a second-level router and a higher-level router, the routing chip comprises a second-level router and a higher-level router, the highest level router of the computing chip is the same as the highest level router of the routing chip;

[0007] The first-level router is connected to a plurality of processing cores on the same computing chip, and adjacent two first-level routers on the same computing chip are connected;

[0008] The second-level router and the higher-level router on the computing chip are connected to multiple lower-level routers on the same computing chip, the second-level router and the higher-level router on the routing chip are connected to multiple same-level routers on the same routing chip, the second-level router and the higher-level router on the routing chip are connected to multiple lower-level routers on the routing chip, and the second-level router and the higher-level router are also connected to corresponding same-level routers on an adjacent computing chip or corresponding same-level routers on an adjacent routing chip.

[0009] Further, the computing chip comprises a plurality of neuron computing modules.

[0010] Further, the neuron computing module comprises:

[0011] a neuron model for calculating firing data of a neuron;

[0012] a block random access memory for storing neuron and synapse parameters to complete time division multiplexing;

[0013] a plastic synapse model for calculating connection strength between neuron models.

[0014] Further, the on-chip network system comprises a higher-level router level of three.

[0015] Further, the first-level router is connected to four adjacent first-level routers on the same computing chip; and / or

[0016] the first-level router is connected to four adjacent first-level routers on the same computing chip; and / or

[0017] the second-level router on the computing chip is connected to four adjacent first-level routers on the same computing chip; and / or

[0018] the second-level router is connected to a second-level router at a corresponding position on an adjacent computing chip or a second-level router on an adjacent routing chip; and / or

[0019] the third-level router on the computing chip is connected to four adjacent second-level routers on the same computing chip; and / or

[0020] the third-level router is connected to a third-level router at a corresponding position on an adjacent computing chip or a third-level router on an adjacent routing chip; and / or

[0021] the third-level router on the routing chip is connected to four adjacent second-level routers on the same routing chip.

[0022] Further, the on-chip network system further comprises a backplane, and a plurality of the functional nodes are arranged on the backplane.

[0023] Further, the bottom plate comprises a communication interface for connecting a power supply, a digital-analog signal conversion module and a USB communication interface.

[0024] The beneficial effects of the present application are: the present application designs a multi-level cluster type three-dimensional network-on-chip structure for the demand of large-scale neuron network hardware simulation, and forms an expandable system by stacking functional nodes containing computing chips and routing chips. The main advantages are: first, the three-dimensional stacking structure in the functional node shortens the connection distance between chips, thereby reducing the inter-chip data transmission delay in the functional node; second, the expandability of the system is enhanced, so that the system can continue to expand according to the grid topology structure in units of functional nodes; third, this architecture can be considered as a two-level cluster design, the functional node is a one-level cluster, which has a lower inter-chip data transmission delay and can simulate the local connection characteristics of neurons in the neuron network. A plurality of one-level clusters can form a two-level cluster, which has a higher inter-chip data transmission delay and can simulate the global connection characteristics of neurons in the neuron network. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a connection structure diagram of a plurality of functional nodes of the present application.

[0026] Figure 2 is a structure diagram of a computing chip of the present application.

[0027] Figure 3 is a structure diagram of a neuron computing module of the present application.

[0028] Figure 4 is a structure diagram of a routing chip of the present application.

[0029] Figure 5 is a connection structure diagram of a plurality of chips of a functional node of the present application. DETAILED DESCRIPTION

[0030] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below in combination with the drawings and the best embodiment. All other embodiments obtained by those skilled in the art on the basis of the embodiments in the application without creative labor are within the scope of protection of the application.

[0031] In the description of the invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the invention.

[0032] In addition, it should be noted that in the description of the invention, unless otherwise explicitly specified and limited, the terms "mounting", "setting", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the invention can be understood according to the specific circumstances.

[0033] Referring to Figure 1 The present application provides a multi-level cluster type three-dimensional network-on-chip system for neuron network simulation. The system comprises a plurality of functional nodes, each of which is similar to a hierarchical cerebral cortical column microcircuit. The functional node comprises a plurality of computing chips and a routing chip arranged vertically and stacked, and the routing chip is arranged at the bottom of the plurality of computing chips. The number of chips of the functional node can be increased or decreased according to actual needs. The network-on-chip of the functional node adopts a multi-level cluster type three-dimensional mesh structure, which combines the advantages of cluster type mesh routing and hierarchical routing, enhances the scalability of the system, and is beneficial to large-scale implementation and application. When the number of functional nodes is small, a simple and efficient mesh structure is selected for connection. This architecture can be regarded as a two-level cluster design, the functional node is a one-level cluster, has a lower inter-chip data transmission delay, and can simulate the local connection characteristics of neurons in a neuron network, and a plurality of one-level clusters can form a two-level cluster, the data transmission delay between nodes is high, and can simulate the global connection characteristics of neurons in a neuron network.

[0034] Referring to Figure 2 A plurality of processing cores P are arranged on the computing chip. In this embodiment, 64 processing cores P are arranged on one computing chip. A neuron calculation module is arranged in the processing core P. Referring to Figure 3The neuron computing module includes a neuron model, a block random access memory (BRAM) and a plastic synapse model. The neuron model is a main computing unit for calculating the firing data of the neuron. The BRAM is used for storing the neuron and synapse parameters to complete time division multiplexing. The plastic synapse model is used for calculating the connection strength between the neuron models. Since the neuron model computing unit and the BRAM are close in the chip, the characteristic of the human brain that the storage and the calculation are integrated can be simulated to a certain extent.

[0035] The specific steps of the neuron computing module are as follows: when the neuron core receives a data packet containing pulse event information, the data packet is first decoded for synapse current calculation, then the neuron state and weight update are performed, and time division multiplexing calculation is performed according to the configuration parameters. After the neuron state and synapse weight update are completed, the corresponding parameters are stored in the corresponding BRAM, and the firing data of the neuron is also output to the router for the next operation.

[0036] Continuing to refer to Figure 2 A plurality of first-level routers R1 are also arranged on the computing chip. In this embodiment, 16 first-level routers R1 are arranged on the computing chip. Each first-level router R1 is connected to 4 processing cores P in the vicinity. The first-level router R1 is also connected to a first-level router R1 in the vicinity. In this embodiment, one first-level router R1 is connected to at most 4 first-level routers R1. The first-level router R1 can receive the information input by the processing core P. When there is a large amount of incoming information, the information is first input into the input buffer module for buffering before being routed, and is sequentially used under the control of the buffer controller by the first-in-first-out queue virtual channel. The data input from the processing core P needs to be packaged into one or more data packets by the data packet processor. The number and destination address of the data packets are determined by the neuron synapse routing table. The number of all nodes connected to the current node is saved in the synapse routing table, and can be modified by the designer according to the connection relationship between the neurons, so as to support the connection between any neurons.

[0037] A plurality of second-level routers R2 are also arranged on the computing chip. In this embodiment, 4 second-level routers R2 are arranged on the computing chip. Each second-level router R2 on the computing chip is connected to a first-level router R1 in the vicinity. In this embodiment, one second-level router R2 on the computing chip is connected to at most 4 first-level routers R1.

[0038] A third-level router R3 is also arranged on the computing chip. In this embodiment, one third-level router R3 is arranged on the computing chip. The third-level router R3 on the computing chip is connected to the second-level router R2. In this embodiment, one third-level router R3 on the computing chip is connected to 4 second-level routers R2.

[0039] The working principle of the second-level router R2 on the computing chip is similar to that of the third-level router R3, and the working principle of the third-level router R3 on the computing chip is similar to that of the first-level router R1. In addition, the second-level router R2 on the computing chip is connected to the second-level router R2 on the adjacent computing chip, and the third-level router R3 on the computing chip is connected to the third-level router R3 on the adjacent computing chip.

[0040] Although the computing chip includes 64 processing cores P, 16 first-level routers R1, 4 second-level routers R2, and 1 third-level router R3 in this embodiment, this arrangement is not a limitation of the present application. Other arrangements can be used in other embodiments without departing from the principles of the present application, such as: other numbers of processing cores P and routers at different levels can be used, the highest level of routers can be adjusted, and the number of connections of each router can be adjusted. These changes do not deviate from the basic principles of the present application and thus fall within the scope of the present application.

[0041] Referring to Figure 4 , a plurality of second-level routers R2 are provided on the routing chip. In this embodiment, 4 second-level routers R2 are provided on a routing chip. The second-level routers R2 on the routing chip are connected to nearby second-level routers R2. In this embodiment, a second-level router R2 on the routing chip is connected to at most 2 second-level routers R2 on the same routing chip.

[0042] A third-level router R3 is also provided on the routing chip. In this embodiment, 1 third-level router R3 is provided on a routing chip. The third-level router R3 on the routing chip is connected to nearby second-level routers R2. In this embodiment, the third-level router R3 on the routing chip is connected to at most 4 second-level routers R2.

[0043] Referring to Figure 5 , the second-level router R2 is also connected to the second-level router R2 at the corresponding position on the adjacent computing chip or the second-level router R2 at the corresponding position on the adjacent routing chip. The third-level router R3 is also connected to the third-level router R3 at the corresponding position on the adjacent computing chip or the third-level router R3 at the corresponding position on the adjacent routing chip.

[0044] The working principle of the second-level router R2 and the third-level router R3 on the routing chip is similar to that of the second-level router R2 and the third-level router R3 on the computing chip. In addition, the second-level router R2 and the third-level router R3 on the routing chip are also connected to the same-level routers on the routing chip. This arrangement enables the second-level router R2 and the third-level router R3 on the routing chip to act as horizontal routers to alleviate the pressure of routing communication when the load of the first-level router R1 is too high.

[0045] The traditional routing network structure is that: the first level router R1 is used as both a horizontal router connecting the routers on the same chip and a vertical router connecting the routers on the adjacent chips. In the routing network structure of the application, the first level router R1 is only used as a horizontal router, and the second level router R2 and the third level router R3 are additionally arranged,

[0046] Further, the on-chip network system further comprises a bottom plate, and the bottom routing chips of the plurality of functional nodes are arranged on the bottom plate. The bottom plate is provided with a communication interface. The communication interface is used for connecting a power supply, a digital-analog signal conversion module and a USB communication interface.

[0047] The above only describes the preferred embodiments of the present application, and it should be noted that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A multi-stage clustered three-dimensional network-on-chip system for neuron network simulation, characterized in that, The system comprises a plurality of functional nodes, the functional nodes comprising a plurality of routing chips and a plurality of computing chips arranged vertically stacked, the routing chips being arranged at the bottom of the plurality of computing chips; The computing chips comprise processing cores, first-level routers, second-level routers and higher-level routers, the routing chips comprise second-level routers and higher-level routers, and the highest-level router of the computing chip is of the same level as the highest-level router of the routing chip; The first-level routers are connected to a plurality of processing cores on the same computing chip, and adjacent two first-level routers on the same computing chip are connected; The second-level routers and higher-level routers on the computing chip are connected to a plurality of lower-level routers on the same computing chip, the second-level routers and higher-level routers on the routing chip are connected to a plurality of same-level routers on the same routing chip, the second-level routers and higher-level routers on the routing chip are connected to a plurality of lower-level routers on the routing chip, and the second-level routers and higher-level routers are further connected to corresponding same-level routers on adjacent computing chips or corresponding same-level routers on adjacent routing chips; The on-chip network system comprises three levels of higher-level routers; The first-level routers are connected to four adjacent processing cores on the same computing chip; and / or The first-level routers are connected to four adjacent first-level routers on the same computing chip; and / or The second-level routers on the computing chip are connected to four adjacent first-level routers on the same computing chip; and / or The second-level routers are connected to corresponding second-level routers on adjacent computing chips or corresponding second-level routers on adjacent routing chips; and / or The third-level routers on the computing chip are connected to four adjacent second-level routers on the same computing chip; and / or The third-level routers are connected to corresponding third-level routers on adjacent computing chips or corresponding third-level routers on adjacent routing chips; and / or The third-level routers on the routing chip are connected to four adjacent second-level routers on the same routing chip. The computing chip comprises a plurality of neuron computing modules. The neuron computing module comprises: a neuron model for calculating the firing data of a neuron; a block random access memory for storing neuron and synapse parameters to complete time division multiplexing; 2. The multi-stage clustered 3D NoC system for neuron network simulation according to claim 1, wherein, a plastic synapse model for calculating the connection strength between neuron models.

3. The multi-stage clustered 3D NoC system for neuron network simulation according to claim 2, wherein, The on-chip network system further comprises a backplane, and the plurality of functional nodes are arranged on the backplane. The backplane comprises a communication interface for connecting a power supply, a digital-analog signal conversion module and a USB communication interface. ​ ​ 4. The multi-stage clustered 3D NoC system for neuron network simulation of claim 1, wherein, ​ 5. The multi-stage clustered 3D NoC system for neural network emulation of claim 4, wherein, ​

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