Display panel, driving method thereof, and display device

Abstract

The application provides a display panel and a driving method thereof and a display device, which comprise pixels arranged in an array, data lines corresponding to each pixel column, and scan lines corresponding to each pixel row, wherein the scan lines are arranged along the row direction; each scan line is configured to output a write level signal in a time-sharing manner in a data writing stage of the corresponding pixel row, so that the pixels in the pixel row write data signals output by the data lines corresponding to the pixels in the pixel row in different time-sharing periods; in this way, for each pixel row, when the scan line outputs the write level signal in a time-sharing manner, the pixels in each pixel row can directly write the required data signals without pre-charging, thereby avoiding the influence of a jump of a subsequent data signal on a previous data signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] With the advent of the era of full-screen design, in order to pursue the process and cost, the number of PIN pins of IC in the display panel is often reduced. After the number of PIN pins of IC is reduced, in order to realize multiplexing of source driving signals, a MUX circuit is often introduced.

[0003] In actual application, it is found that due to the introduction of the MUX circuit, the pixel circuit in the display panel usually adopts the pre-charging or partial direct-charging mode for writing data signals in the data writing stage, so it is easy to be interfered by other jump signals, thereby reducing the screen quality. SUMMARY

[0004] In order to solve the above problems, the inventor finds the cause of the problem through research and development, and forms a solution.

[0005] In a first aspect, the present application provides a display panel, characterized in that comprising:

[0006] Pixels arranged in an array, comprising a plurality of pixel rows and a plurality of pixel columns, the plurality of pixel columns are divided into a plurality of column-direction pixel groups;

[0007] Data lines corresponding to each pixel column, the data lines are arranged along the column direction;

[0008] Scan lines corresponding to each pixel row, the scan lines are arranged along the row direction;

[0009] Wherein, each scan line is configured to output a write level signal in a time-sharing manner in the data writing stage of the corresponding pixel row, so that the pixels of the pixel row write the data signals output by the data lines corresponding to the pixels of the pixel row in different time-sharing periods; wherein, the number of time-sharing periods is determined according to the number of pixel columns in the column-direction pixel group or the number of column-direction pixel groups.

[0010] Further, in the above display panel,

[0011] At least two sequentially adjacent pixel columns are divided into a column-direction pixel group;

[0012] The number of time-sharing periods is the same as the number of pixel columns in each column-direction pixel group.

[0013] Further, in the above display panel,

[0014] There is no overlap time period between each of the time-sharing time periods, and the total time length of all the time-sharing time periods approaches the refresh time of each pixel row.

[0015] Further, in the display panel,

[0016] The odd pixel columns are divided into an odd pixel group in the column direction, and the even pixel columns are divided into an even pixel group in the column direction.

[0017] The number of the time-sharing time periods and the number of the pixel groups in the column direction are both 2.

[0018] Further, in the display panel,

[0019] The display panel further comprises a first gate circuit and a second gate circuit.

[0020] The first gate circuit is configured to select the pixels of the even pixel group for writing of the data signal.

[0021] The second gate circuit is configured to select the pixels of the odd pixel group for writing of the data signal.

[0022] Further, in the display panel,

[0023] The data lines comprise odd data lines and even data lines, wherein the odd data lines are connected with the odd pixels in the pixel columns, and the even data lines are connected with the even pixels in the pixel columns.

[0024] The display panel further comprises a first gate circuit, a second gate circuit, a third gate circuit, and a fourth gate circuit.

[0025] The first gate circuit is configured to select the pixels of the odd pixel rows in the even pixel group to write the data signal of the odd data lines.

[0026] The third gate circuit is configured to select the pixels of the even pixel rows in the even pixel group to write the data signal of the even data lines.

[0027] The second gate circuit is configured to select the pixels of the odd pixel rows in the odd pixel group to write the data signal of the odd data lines.

[0028] The fourth gate circuit is configured to select the pixels of the even pixel rows in the odd pixel group to write the data signal of the even data lines.

[0029] Further, in the display panel,

[0030] There is an overlap time period between the two time-sharing time periods, and each of the time-sharing time periods approaches the refresh time of each pixel row.

[0031] Further, in the display panel,

[0032] The pixel circuit corresponding to the pixel includes a write transistor and a compensation transistor;

[0033] The scan line includes a plurality of sub-scan lines which are the same as the number of the time-sharing time periods;

[0034] The plurality of sub-scan lines are located on the same side of the gate of the write transistor and the gate of the compensation transistor, or at least two sub-scan lines in the plurality of sub-scan lines are located on the opposite side of the gate of the write transistor and the gate of the compensation transistor.

[0035] In a second aspect, the present application provides a driving method of the display panel, and the driving method comprises the following steps:

[0036] In the data writing stage of each pixel row, the corresponding scan line is controlled to output a write level signal in a time-sharing manner, so that the pixels in the pixel row write the data signal output by the data line corresponding to the pixels in different time-sharing time periods;

[0037] The number of the time-sharing time periods is determined according to the number of the pixel columns in the column direction pixel group or the number of the column direction pixel groups.

[0038] In a third aspect, the present application provides a display device, and the display device includes the display panel.

[0039] The technical scheme provided by the present application has one or more of the following beneficial effects:

[0040] In the implementation of the technical scheme of the present application, a plurality of pixel columns are divided into a plurality of column direction pixel groups, and the time-sharing time periods for writing data of each pixel row are determined according to the number of the pixel columns in the column direction pixel group or the number of the column direction pixel groups. Thus, in the data writing stage, the corresponding scan line of each pixel row can be controlled to output a write level signal in a time-sharing manner, so that the pixels in the pixel row write the data signal output by the data line corresponding to the pixels in different time-sharing time periods. Thus, for each pixel row, when the scan line outputs the write level signal in a time-sharing manner, the pixels in each pixel row can directly write the required data signal without pre-charging, thereby avoiding the influence of the jump of the subsequent data signal on the previous data signal. BRIEF DESCRIPTION OF DRAWINGS

[0041] The disclosure of the present invention will be more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Furthermore, similar numbers in the drawings represent similar components, wherein:

[0042] Figure 1 It is a schematic diagram of pixel arrangement of a display panel;

[0043] Figure 2 yes Figure 1 A schematic diagram of a power supply method for a display panel shown;

[0044] Figure 3 yes Figure 1 A driving timing control diagram of the display panel shown;

[0045] Figure 4 is a structural schematic diagram of a display panel of the present invention;

[0046] Figure 5 This is another pixel arrangement diagram of a display panel;

[0047] Figure 6 yes Figure 5 A driving timing control diagram of the display panel shown;

[0048] Figure 7 This is a circuit diagram of a pixel circuit in a display panel;

[0049] Figure 8 This is another pixel arrangement diagram of a display panel;

[0050] Figure 9 yes Figure 8 A driving timing control diagram of the display panel shown;

[0051] Figure 10 This is another pixel arrangement diagram of a display panel;

[0052] Figure 11 yes Figure 10 A driving timing control diagram of the display panel shown;

[0053] Figure 12 yes Figure 2 Another timing control diagram of the display panel under the power supply mode;

[0054] Figure 13 yes Figure 1 A schematic diagram of another power supply method for the display panel shown;

[0055] Figure 14 yes Figure 13 Another timing control diagram of the display panel under the power supply mode;

[0056] Figure 15 is based on Figure 10 a layout structure of the display panel shown in FIG. 1;

[0057] Figure 16 is a schematic diagram of the display device of the present application;

[0058] Figure 17 is another schematic diagram of the display device of the present application;

[0059] Figure 18 is still another schematic diagram of the display device of the present application. DETAILED DESCRIPTION

[0060] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without using some or all of these specific details, and that the present application is not limited to the specific embodiments disclosed below.

[0061] In the description of the present application, the terms "first", "second", etc. are used only for the purpose of description, and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include at least one of the features. In addition, in the present application, unless otherwise explicitly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be internal communication of two elements or interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0062] In the description of the present application, the transistors used in the circuit provided by the embodiments can be thin film transistors, field effect transistors or other switch devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as an example. The control end of any one transistor is the gate of the transistor, the first end of any one transistor is one of the source and drain of the transistor, and the second end of any one transistor is the other of the source and drain of the transistor.

[0063] In the description of the present invention, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term "coupled" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0064] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0065] As used herein, "about," "approximately," "close to," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0066] With the advent of full-screen designs, and the reduction in the number of PINs in ICs, multiplexing of source drive signals often requires the introduction of MUX circuits. However, during the data writing phase, pixel circuits in display panels typically use pre-charge or partial direct charge to write data signals, which makes them susceptible to interference from other transition signals, thereby reducing screen image quality.

[0067] Specifically, Figure 1 It is a pixel arrangement diagram of a display panel. Figure 2 yes Figure 1 A schematic diagram of a power supply method for a display panel is shown in FIG. Figure 3 yes Figure 1 A driving timing control diagram of the display panel shown in FIG. Figures 1 to 3 The four data lines in the display panel are marked as Date1 to Date4 in sequence. The pixel columns of the display panel are selected by two MUX circuits, marked as MUX1 and MUX2. Among them, MUX1 selects the even pixel columns to write data, and MUX2 selects the cardinal pixel columns to write data. The pixel arrangement of the odd pixel rows is RG1BG2, and the pixel arrangement of the even pixel rows is BG2RG1. Figure 3As shown, in the data writing stage, the conventional writing mode is as follows: for each pixel row, MUX1 controls the corresponding transistor to be turned on, the data signal dateG1G2 corresponding to the G1G2 pixel pair is pre-charged (the data signal dateG1G2 is provided by the source driving circuit source1 and the source driving circuit source2 during the period when MUX1 is turned on), after MUX2 controls the corresponding transistor to be turned on, the scan line GateN of each pixel row is turned on, N=1, 2, 3, 4, the data signal dateRB corresponding to the RB pixel is directly written (the data signal dateRB is provided by the source driving circuit source1 and the source driving circuit source2 during the period when MUX2 is turned on), and the data signal corresponding to the G1G2 pixel is pre-charged and written. It is found through research that this writing mode has the following problems: if the coupling capacitance between the data lines of adjacent G1G2 pixels and the data line corresponding to the RB pixel is large, the data signal on the parasitic data line of the G1G2 pixel will change when the data signal corresponding to the RB pixel jumps, which reduces the screen quality and affects the screen display effect.

[0068] It should be noted that, in order to distinguish whether the signal has passed through the MUX circuit, the signal from the chip IC is generally a source signal before passing through the MUX circuit, and a data signal after passing through the MUX.

[0069] Therefore, based on the problems found, the present application provides the following technical means:

[0070] Figure 4 is a structural schematic diagram of the display panel of the present application, as Figure 4 shown, the display panel includes pixels arranged in an array, which includes a plurality of pixel rows and a plurality of pixel columns. The display panel further includes a data line corresponding to each pixel column, the data line being arranged along the column direction; a scan line corresponding to each pixel row, the scan line being arranged along the row direction. Figure 4 In the present application, four rows and eight columns are taken as an example for illustration, that is, including scan lines Gate1 to Gate4 and data lines Date1 to Date8.

[0071] In a specific implementation, multiple pixel columns can be divided into multiple column-wise pixel groups, and the time-sharing period for writing data to each pixel row can be determined based on the number of pixel columns in the column-wise pixel groups or the number of pixel groups in the column-wise pixel groups. In this way, during the data writing phase, the scan line corresponding to each pixel row can be controlled to output a write level signal in a time-sharing manner, so that the pixels in the pixel row write the data signals output by the data lines corresponding to the pixels in the pixel row in different time-sharing periods. In this way, for each pixel row, when the scan line outputs the write level signal in a time-sharing manner, the pixels in each pixel row can directly write the required data signals without the need for precharging, thereby preventing the impact of the subsequent data signal jump on the previous data signal.

[0072] Specifically, Figure 5 This is another pixel arrangement diagram of the display panel. Figure 6 yes Figure 5 A driving timing control diagram of the display panel shown, Figure 7 This is a circuit diagram of a pixel circuit in a display panel. Figure 5 Only the arrangement of one row of pixels is shown, that is, the arrangement with RG1BG2 as the period. Figure 5 In this example, four adjacent pixel columns are divided into a column-wise pixel group, resulting in a total of four column-wise pixel groups. Each column-wise pixel group receives a source drive signal output by a corresponding source drive circuit. The four source drive circuits are denoted as source1, source2, source3, and source4.

[0073] In a specific implementation process, the time-sharing period during which the scan line corresponding to each pixel row outputs the write level signal in a time-sharing manner is the same as the number of pixel columns in each pixel group in the column direction. Figure 5 and Figure 6 As shown, there are four time-sharing periods in this embodiment. The scan line includes a number of sub-scan lines equal to the number of the time-sharing periods. That is, in this embodiment, each row of scan lines GateP_1 may include four sub-scan lines, denoted as GateP_1_4n to GateP_1_4n+3, and the scan signal input of each sub-scan line is Figure 7 The compensation transistor T2 and the write transistor T4 correspond to the gate Gate terminal, and the pixels in each column direction pixel group are connected to the corresponding sub-scan line.

[0074] like Figure 6 As shown, the driving method of the display panel is:

[0075] When GateP_1_4n outputs a low level signal (i.e. a write level signal), Figure 7The write transistor T4 and the compensation transistor T2 are turned on, and the data signals dateR corresponding to all R pixels in the row are written via the Date terminal (data signal input terminal) of the write transistor T4;

[0076] Similarly, when GateP_1_4n+1 outputs a low-level signal, the data signal dateG1 corresponding to all G1 pixels in the row is written via the Date terminal of write transistor T4; when GateP_1_4n+2 outputs a low-level signal, the data signal dateB corresponding to all B pixels in the row is written via the Date terminal of write transistor T4; and when GateP_1_4n+3 outputs a low-level signal, the data signal dateG2 corresponding to all G2 pixels in the row is written via the Date terminal of write transistor T4. In other words, the data signal is written using a completely direct-thrust method, which enhances the anti-interference capability of each data line in the pixel circuit, prevents the impact of subsequent data signal jumps on the previous data signal, improves screen image quality, and thus ensures the screen display effect.

[0077] Figure 8 This is another pixel arrangement diagram of the display panel. Figure 9 yes Figure 8 A driving timing control diagram of the display panel shown. Figure 5 and Figure 8 The difference between the two is that Figure 8 Arrangement with RGB as the cycle. Figure 8 In the example, four adjacent pixel columns are divided into a column direction pixel group, and a total of four column direction pixel groups are divided. Each column direction pixel group receives a source driving signal output by a corresponding source driving circuit. The four source driving circuits are respectively denoted as source1, source2, source3, and source4. Figure 8 For the display panel shown, each row of scan lines corresponds to three time-sharing periods, and the scan line includes three sub-scan lines, which are marked as GateP_1_3n to GateP_1_3n+2.

[0078] like Figure 9 As shown, the driving method of the display panel is:

[0079] When GateP_1_3n outputs a low level signal (i.e. a write level signal), Figure 7 The second write transistor T4 and the compensation transistor T2 are turned on, and the data signals dateR corresponding to all R pixels in the row are written via the Date terminal of the write transistor T4;

[0080] Similarly, when GateP_1_3n+1 outputs low level signal, the data signal dateG corresponding to all G pixels in this row is written via the Date terminal of the writing transistor T4; when GateP_1_3n+2 outputs low level signal, the data signal dateB corresponding to all B pixels in this row is written via the Date terminal of the writing transistor T4, which can achieve the effect similar to that of the display panel shown in Figure 5 which is not repeated here.

[0081] Figure 10 is another pixel arrangement diagram of a display panel, Figure 11 Figure 10 is a driving timing control diagram of the display panel shown in Figure 5 Figure 10 The difference between them is that, Figure 8 the arrangement mode with RG1BG2 as a period. Figure 10 In the display panel shown in FIG. 8, 2 sequentially adjacent pixel columns are divided into a column direction pixel group, and 8 column direction pixel groups are divided in total. Each column direction pixel group receives a source driving signal output by a corresponding source driving circuit. Among them, the 8 source driving circuits are respectively denoted as source1 to source8. For the column direction pixel group corresponding to source1, the source driving signal output by source1 is denoted as source1, and the source driving signal output by source2 is denoted as source2. Figure 10 For the display panel shown in FIG. 8, the number of time-sharing periods corresponding to each row of scan lines is 2, which includes 2 sub-scan lines, denoted as GateP_1_2n to GateP_1_2n+2.

[0082] As shown in FIG. 9, the driving method of the display panel is as follows: Figure 11

[0083] When GateP_1_2n outputs low level signal (i.e. writing level signal), Figure 7 the second writing transistor T4 and the compensation transistor T2 in FIG. 8 are turned on, the data signal dateR corresponding to all R pixels in this row is written via the Date terminal of the writing transistor T4, and the data signal dateB corresponding to all B pixels is written via the Date terminal of the writing transistor T4. Among them, the data signal corresponding to all R pixels is provided by the source driving circuit of the odd column direction pixel group, i.e. source1, source3, source5 and source7 can output the data signal corresponding to R pixels during the period when GateP_1_2n outputs low level signal. The data signal corresponding to all B pixels is provided by the source driving circuit of the even column direction pixel group, i.e. source2, source4, source6 and source8 can output the data signal corresponding to B pixels during the period when GateP_1_2n outputs low level signal.

[0084] ​​​Similarly, when GateP_1_2n+1 outputs a low-level signal, the data signals dateG1 corresponding to all G1 pixels are written via the Date terminal of the write transistor T4, and the data signals dateG2 corresponding to all G2 pixels are written via the Date terminal of the write transistor T4. The data signals corresponding to all G1 pixels are provided by the source driving circuits of the odd column direction pixel groups, i.e., source1, source3, source5, and source7 can output the data signals corresponding to G1 pixels during the period when GateP_1_2n+1 outputs a low-level signal. The data signals corresponding to all G2 pixels are provided by the source driving circuits of the even column direction pixel groups, i.e., source2, source4, source6, and source8 can output the data signals corresponding to G2 pixels during the period when GateP_1_2n+1 outputs a low-level signal. Figure 10 In Figure 11 the timing driving, the effects achieved are similar to those of the real panel shown in Figure 5 , which will not be described here again.

[0085] In one specific implementation process, the timing control diagram corresponding to the embodiments shown in Figure 5 , Figure 8 , Figure 10 does not have an overlapping time period between each of the time-sharing periods, and the total length of all the time-sharing periods tends to approach the refresh time of each pixel row, so that the data writing time can be guaranteed as much as possible to ensure the display quality.

[0086] In one specific implementation process, Table 1 is the refresh time corresponding to the clock signal CK / control signal CB in the case of multiple scanning lines of a mobile phone and a watch. As can be seen from Table 1, for a watch, there is relatively sufficient time to convert the MUX1:2, MUX1:3, and MUX1:4 products by using the embodiments shown in Figure 5 , Figure 8 , Figure 10 . For a mobile phone, in the case of MUX1:2, MUX1:3, and MUX1:4, it is necessary to ensure that CK / CB < 1.49 μs.

[0087] Table 1

[0088]

[0089] In one specific implementation process, the timing control diagram corresponding to the embodiments shown in Figure 5 , Figure 8 , Figure 10The embodiments shown are all examples of MUX circuit-free, and in applications, for display panels with MUX circuits, similar methods can be used to output the write level signal of each pixel row corresponding scan line in the data write stage, so that the pixels of the pixel row write the data signal output by the data line corresponding to the pixels of the pixel row in different time-sharing periods. It can also be directly charged and written to avoid the influence of the jump of the next data signal on the previous data signal.

[0090] Specifically, for the presence of MUX circuit, the odd pixel columns can be divided into an odd pixel group in the column direction, and the even pixel columns can be divided into an even pixel group in the column direction; in this case, the number of time-sharing periods and the number of pixel groups in the column direction are both 2.

[0091] Figure 12 is Figure 2 Another timing control diagram of the display panel in the power supply mode of Figure 1 and 12 As shown in the first gating circuit (MUX1) is configured to select the pixels of the even pixel group for writing of the data signal, and the second gating circuit (MUX2) is configured to select the pixels of the odd pixel group for writing of the data signal. Among them, Figure 12 The GOA output signal in the GOA is mainly named to distinguish between odd and even rows, such as * _O / E_*, and the odd and even rows are sorted respectively, such as * _O1 / E1_*, * _O2 / E2_*, O represents the odd row, and E represents the even row.

[0092] For the first pixel row, the driving method is as follows:

[0093] GOA_O1_G1G2 is low, G1 pixel is written by the first data signal provided by source1, and G2 pixel is written by the first data signal provided by source2. GOA_O1_RB is low, R pixel is written by the second data signal provided by source1, and B pixel is written by the second data signal provided by source2. Among them, there is an overlapping period between the two time-sharing periods, and each of the time-sharing periods approaches the refresh time of each pixel row. In this way, each data signal is first written in a partial direct charging manner, and then written in a partial pre-charging manner, which increases the data signal write time and alleviates the problem of insufficient data signal write time when driving row by row.

[0094] Similarly, for the driving method of the driving process of the second pixel row, the driving method is as follows:

[0095] GOA_E1_G1G2 is low, G1 pixel is written by the third data signal provided by source1, G2 pixel is written by the third data signal provided by source2. GOA_E1_RB is low, R pixel is written by the fourth data signal provided by source1, B pixel is written by the fourth data signal provided by source2.

[0096] The driving method of the driving process for the third pixel row is as follows:

[0097] GOA_O2_G1G2 is low, G1 pixel is written by the first data signal provided by source1, G2 pixel is written by the first data signal provided by source2. GOA_O2_RB is low, R pixel is written by the second data signal provided by source1, B pixel is written by the second data signal provided by source2.

[0098] The driving method of the driving process for the fourth pixel row is as follows:

[0099] GOA_E2_G1G2 is low, G2 pixel is written by the third data signal provided by source1, G1 pixel is written by the third data signal provided by source2. GOA_E2_RB is low, R pixel is written by the fourth data signal provided by source1, B pixel is written by the fourth data signal provided by source2.

[0100] It should be noted that the data signal provided by each source driving circuit source described above is Figure 12 the signal corresponding to date.

[0101] Figure 13 is Figure 1 Another power supply mode of the display panel shown in Figure 14 is Figure 13 Another timing control diagram of the display panel under the power supply mode of

[0102] As Figure 13 shown, the display panel is gated by four MUX circuits, denoted as MUX1, MUX2, MUX3 and MUX4, and each pixel column corresponds to a data line including an odd data line and an even data line, wherein the odd data line is connected to the odd pixel in the pixel column, and the even data line is connected to the even pixel in the pixel column. Continue to refer to Figure 13, MUX1 selects the pixel of the odd pixel row in the even pixel group to write the data signal of the odd data line, MUX2 selects the pixel of the odd pixel row in the odd pixel group to write the data signal of the odd data line, MUX3 selects the pixel of the even pixel row in the even pixel group to write the data signal of the even data line, and MUX4 selects the pixel of the even pixel row in the odd pixel group to write the data signal of the even data line.

[0103] As shown in FIG. 1, the driving method for the first pixel row is as follows: Figure 14

[0104] GOA_O1_G1G2 is low, G1 pixel is written by the first data signal provided by source1, and G2 pixel is written by the first data signal provided by source2. GOA_O1_RB is low, R pixel is written by the second data signal provided by source1, and B pixel is written by the second data signal provided by source2. There is an overlapping time period between two time-sharing periods, and each time-sharing period approaches the refresh time of each pixel row. In this way, each data signal is first written in a partial direct drive manner and then in a partial pre-charge manner, which increases the data signal writing time and alleviates the problem of insufficient data signal writing time in row-by-row driving. In addition, since each time-sharing period approaches the refresh time of each pixel row rather than the refresh time of two pixel rows, crosstalk between the data signals of the odd data line and the data signals of the even data line in adjacent two pixel columns can be avoided.

[0105] Specifically, Figure 14 The conversion of GOA_O1_G1G2 from a low-level signal to a high-level signal occurs before MUX2 outputs a low-level signal, that is, the opening time of GOA_O1_G1G2 approaches the refresh time of one pixel row. If the opening time of GOA_O1_G1G2 approaches the refresh time of two pixel rows, that is, the conversion of GOA_O1_G1G2 from a low-level signal to a high-level signal occurs before MUX3 outputs a low-level signal, at this time, when the pixels in the odd column of the second pixel row are writing data, the pixels in the even column of the first pixel row are still writing data, and then the data signals of the two data lines are prone to crosstalk, affecting the display effect.

[0106] Similarly, the driving method for the driving process of the second pixel row is as follows:

[0107] ​When GOA_E1_G1G2 is set low, the G2 pixel is written by the third data signal provided by source1, and the G1 pixel is written by the third data signal provided by source2. When GOA_E1_RB is set low, the R pixel is written by the fourth data signal provided by source1, and the B pixel is written by the fourth data signal provided by source2.

[0108] The driving method for the driving process of the third pixel row is as follows:

[0109] When GOA_O2_G1G2 is set low, the G1 pixel is written by the first data signal provided by source1, and the G2 pixel is written by the first data signal provided by source2. When GOA_O2_RB is set low, the R pixel is written by the second data signal provided by source1, and the B pixel is written by the second data signal provided by source2.

[0110] The driving method for the fourth pixel row is as follows:

[0111] When GOA_E2_G1G2 is set low, the G2 pixel is written by the third data signal provided by source1, and the G1 pixel is written by the third data signal provided by source2. When GOA_E2_RB is set low, the R pixel is written by the fourth data signal provided by source1, and the B pixel is written by the fourth data signal provided by source2.

[0112] It should be noted that the data signals provided by the above-mentioned source driving circuits are Figure 13 The signal corresponding to date.

[0113] In a specific implementation process, in the above embodiments, when each row of pixels uses multiple sub-scan lines to implement time-sharing data writing, the multiple sub-scan lines can be located on the same side of the gate of the write transistor and the gate of the compensation transistor in each pixel in each row of pixels, or at least two of the multiple sub-scan lines are located on different sides of the gate of the write transistor and the gate of the compensation transistor.

[0114] Figure 15 is based on Figure 10 The following is a layout structure of the display panel. Figure 15 As shown, Figure 15 The left side of the middle is the original layout structure, where each pixel is connected by a scan line. The solution of using multiple sub-scan lines to write data in time is Figure 15 In the layout on the right side, the first sub-scan line GateP_1_2n connects the pixels in the odd pixel columns, and the second sub-scan line GateP_1_2n+1 connects the pixels in the even pixel columns. Figure 15Take the case that the first sub-scan line GateP_1_2n and the second sub-scan line GateP_1_2n+1 are located on the same side of the gate of the writing transistor and the gate of the compensation transistor as an example, and the case that they are located on different sides will not be described again. Among them, Figure 15 It is only a schematic description of the arrangement of the two sub-scan lines, and the arrangement of each transistor and other related elements in the figure remains unchanged, and details can be referred to the related prior art, which will not be described again.

[0115] It should be noted that the layout structure of the above-mentioned other display panel and Figure 15 the arrangement type of the above-mentioned other display panel will not be described one by one.

[0116] Further, the present application also provides a driving method of a display panel, which comprises:

[0117] In the data writing stage of each pixel row, the corresponding scan line is controlled to output a writing level signal in time, so that the pixels of the pixel row write the data signal output by the data line corresponding to the pixels of the pixel row in different time periods.

[0118] Among them, the number of time periods is determined according to the number of pixel columns in the column direction pixel group or the number of column direction pixel groups.

[0119] Further, the present application also provides a display device, which comprises the display panel of the above-mentioned embodiments. Among them, the display device can include a mobile phone or a watch.

[0120] Figure 16 is a schematic diagram of the display device of the present application, which adopts Figure 5 the display panel shown in the figure. The gate drive circuit is arranged on both sides of the display area AA of the display panel. Among them, the light-emitting control signal line EMk in the gate drive circuit corresponds to two row pixels. Among them, k=1, 2, 3…N / 2, N is a function of the pixel row. The scan line in the gate drive circuit corresponds to one row pixel, and the scan line of each row pixel includes four sub-scan lines, which are respectively GateP_i_4n to GateP_i_4n+3, i=1, 2, 3…N.

[0121] Figure 17 is another schematic diagram of the display device of the present application, which adopts Figure 8 the display panel shown in the figure. The gate drive circuit is arranged on both sides of the display area of the display panel. Among them, the light-emitting control signal line in the gate drive circuit corresponds to two row pixels. The scan signal line in the gate drive circuit corresponds to one row pixel, and the scan line of each row pixel includes three sub-scan lines, which are respectively GateP_i_3n to GateP_i_3n+3, i=1, 2, 3…N.

[0122] Figure 18 is another schematic diagram of the display device of the present invention, which uses Figure 8 The display panel shown in FIG. Gate drive circuits are provided on both sides of the display area of ​​the display panel. Each light-emission control signal line in the gate drive circuit corresponds to two rows of pixels. Each scan signal line in the gate drive circuit corresponds to one row of pixels, and each row of pixels includes two sub-scan lines, designated GateP_i_2n through GateP_i_2n+2, where i = 1, 2, 3, ..., N.

[0123] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.

Claims

1. A display panel, characterized by, The display panel comprises: pixels arranged in an array, including a plurality of pixel rows and a plurality of pixel columns, the plurality of pixel columns being divided into a plurality of column-direction pixel groups; a data line corresponding to each pixel column, the data line being arranged along the column direction; a scan line corresponding to each pixel row, the scan line being arranged along the row direction; wherein each scan line is configured to output a write level signal in a data write stage of the corresponding pixel row, so that the pixels of the pixel row write data signals output by the data line corresponding to the pixels in different time-sharing periods; wherein the number of time-sharing periods is determined according to the number of pixel columns in the column-direction pixel group or the number of column-direction pixel groups; the pixel circuit corresponding to the pixel comprises a write transistor and a compensation transistor; the scan line comprises a plurality of sub-scan lines which are the same in number as the number of time-sharing periods; the plurality of sub-scan lines are located on the same side of the gate of the write transistor and the gate of the compensation transistor, or at least two sub-scan lines in the plurality of sub-scan lines are located on the opposite side of the gate of the write transistor and the gate of the compensation transistor.

2. The display panel of claim 1, wherein at least two sequentially adjacent pixel columns are divided into a column-direction pixel group; the number of time-sharing periods is the same as the number of pixel columns in each column-direction pixel group.

3. The display panel of claim 2, wherein there is no overlapping time period between each time-sharing period, and the total time length of all time-sharing periods approaches the refresh time of each pixel row.

4. The display panel of claim 1, wherein odd pixel columns are divided into an odd column-direction pixel group, and even pixel columns are divided into an even column-direction pixel group; the number of time-sharing periods is 2 for each of the column-direction pixel group.

5. The display panel of claim 4, wherein, The display panel further comprises a first gating circuit and a second gating circuit; the first gating circuit is configured to select the pixels of the even pixel group for writing of data signals; the second gating circuit is configured to select the pixels of the odd pixel group for writing of data signals.

6. The display panel of claim 4, wherein the data line comprises odd data lines and even data lines, wherein the odd data lines are connected to odd pixels in the pixel columns, and the even data lines are connected to even pixels in the pixel columns; the display panel further comprises a first gating circuit, a second gating circuit, a third gating circuit, and a fourth gating circuit; the first gating circuit is configured to select the pixels of odd pixel rows in the even pixel group to write data signals of the odd data lines; the third gating circuit is configured to select the pixels of even pixel rows in the even pixel group to write data signals of the even data lines; the second gating circuit is configured to select the pixels of odd pixel rows in the odd pixel group to write data signals of the odd data lines; the fourth gating circuit is configured to select the pixels of even pixel rows in the odd pixel group to write data signals of the even data lines.

7. The display panel of claim 5 or 6, wherein, there is an overlap time period between two of the time-sharing time periods, and each of the time-sharing time periods approaches a refresh time of each pixel row.

8. A driving method of a display panel according to any one of claims 1 to 7, characterized by, comprising: in a data writing stage of each pixel row, controlling the corresponding scan line to output a writing level signal in a time-sharing manner, so that the pixels of the pixel row write data signals output by corresponding data lines of the pixels in different time-sharing time periods; wherein the number of the time-sharing time periods is determined according to the number of pixel columns in a pixel group in a column direction or the number of the pixel groups in the column direction.

9. A display device, characterized by comprising: comprising the display panel of any one of claims 1 to 7.

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