A quality assessment method for an embedded storage chip

Abstract

The present invention relates to the field of computer technologies, and particularly to a method for evaluating the quality of an embedded storage chip. The method includes the following steps: constructing a load prediction model according to a pre-selected target application scenario to obtain the load prediction model; generating a dynamic load matrix according to the load prediction model to obtain the dynamic load matrix; extracting an electrical performance feature vector from the storage chip to be tested according to the dynamic load matrix to obtain the electrical performance feature vector; adjusting the adaptive test conditions according to the electrical performance feature vector to obtain the adjusted load parameters; dynamically updating the dynamic load matrix according to the load prediction model and the adjusted load parameters to obtain the updated dynamic load matrix; generating an electrical characteristic curve according to the updated dynamic load matrix to obtain the electrical characteristic curve. The present invention realizes a more accurate, comprehensive and reliable chip quality evaluation through dynamic load, storage behavior analysis and thermal characteristic analysis.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for evaluating the quality of an embedded storage chip. Background Art

[0002] Traditional methods for evaluating the quality of embedded storage chips mainly rely on static tests, focusing on some basic electrical performance indicators, such as read / write speed, data retention time, number of erase / write cycles, etc. These methods are usually carried out under fixed test conditions and lack consideration of actual application scenarios. Static test conditions are usually relatively idealized and cannot simulate the complex load conditions of the chip in actual application scenarios. For example, in actual applications, the load exhibits characteristics such as suddenness and randomness, while static tests cannot capture these dynamic characteristics, resulting in a deviation between the evaluation results and the actual performance.

[0003] Traditional methods lack in-depth analysis of chip behavior and insufficient consideration of thermal characteristics. Traditional methods mainly focus on macroscopic performance indicators and lack in-depth analysis of the internal behavior of the chip. For example, information such as the delay distribution, error mode, and throughput fluctuation of the chip under different loads is crucial for evaluating the quality of the chip, but it is difficult for traditional methods to obtain this information. The chip generates heat during operation, and excessive temperature will affect the performance and lifespan of the chip. Traditional methods usually ignore the impact of thermal characteristics on chip quality, resulting in incomplete evaluation results. Summary of the Invention

[0004] In view of this, it is necessary to provide a method for evaluating the quality of an embedded storage chip to solve at least one of the above technical problems.

[0005] To achieve the above object, a method for evaluating the quality of an embedded storage chip includes the following steps:

[0006] Step S1: Construct a load prediction model according to a pre-selected target application scenario to obtain a load prediction model; generate a dynamic load matrix according to the load prediction model to obtain a dynamic load matrix;

[0007] Step S2: Extract electrical performance feature vectors for the storage chip to be tested according to the dynamic load matrix to obtain electrical performance feature vectors; adjust the test conditions adaptively according to the electrical performance feature vectors and the load prediction model to obtain adjusted load parameters; update the dynamic load matrix dynamically according to the load prediction model and the adjusted load parameters to obtain an updated dynamic load matrix; generate an electrical characteristic curve according to the updated dynamic load matrix to obtain an electrical characteristic curve;

[0008] Step S3: Perform storage behavior simulation processing based on the updated dynamic load matrix to obtain simulated behavior data; conduct data flow analysis on the simulated behavior data to obtain data flow characteristics; construct a storage behavior map based on the data flow characteristics and the updated dynamic load matrix to obtain a storage behavior map;

[0009] Step S4: Extract thermal power consumption characteristics of the storage chip under test based on the updated dynamic load matrix to obtain a thermal power consumption feature vector; conduct thermal stability analysis based on the thermal power consumption feature vector and the storage behavior map to obtain a thermal stability index; construct a thermal energy consumption feature matrix based on the thermal stability index and the updated dynamic load matrix to obtain a thermal energy consumption feature matrix;

[0010] Step S5: Construct a quality evaluation model based on the updated dynamic load matrix, electrical characteristic curve, storage behavior map, and thermal energy consumption feature matrix to obtain a quality evaluation model; use the quality evaluation model to calculate a comprehensive quality score to obtain a comprehensive quality score; perform chip grading and screening based on the comprehensive quality score to obtain a chip grading result, so as to achieve the quality evaluation task of the embedded storage chip.

[0011] The present invention realizes load simulation based on real application scenarios by constructing a load prediction model and generating a dynamic load matrix, making the test load more representative and capable of more accurately reflecting the performance of the chip in actual use, overcoming the limitations of traditional methods using fixed load tests. Through dynamic load application and electrical performance data collection, real-time monitoring of the chip in a dynamic working environment is achieved; and through feature extraction, correlation processing, and performance bottleneck identification, adaptive adjustment of the test process is realized, enabling more targeted testing of the weak links of the chip, improving the test efficiency and accuracy, and finally generating an electrical characteristic curve to provide an intuitive basis for chip performance evaluation. Through simulated data generation and storage behavior simulation, simulation of the chip's storage behavior under real load is achieved; and through data flow analysis and construction of a storage behavior map, comprehensive analysis and visualization of the chip's storage behavior are realized, enabling a deeper understanding of the chip's performance characteristics and identification of potential performance bottlenecks. Through real-time temperature and power consumption monitoring under dynamic load and extraction of thermal power consumption characteristics, comprehensive characterization of the chip's thermal behavior and power consumption characteristics is achieved; and through thermal stability analysis in combination with the storage behavior map, the reliability and energy efficiency ratio of the chip under different working temperatures and load conditions can be more accurately evaluated, and finally a thermal energy consumption characteristic matrix is constructed to provide more comprehensive data support for chip quality evaluation. Through standardization and weight determination of multiple feature data and construction of a quality evaluation model, comprehensive evaluation of the chip quality is achieved; and through calculation of the comprehensive quality score and hierarchical screening of the chips, a scientific decision-making basis is provided for chip production and manufacturing. Therefore, the present invention provides a method for evaluating the quality of an embedded storage chip, which effectively solves the deficiencies of traditional methods for evaluating the quality of embedded storage chips by introducing technologies such as dynamic load, storage behavior analysis, and thermal characteristic analysis, and realizes more accurate, comprehensive, and reliable chip quality evaluation.

[0012] Preferably, step S1 includes the following steps:

[0013] Step S11: Collect application scenario data according to a pre-selected target application scenario to obtain an application scenario data set;

[0014] Step S12: Extract load characteristics from the application scenario data set to obtain a load characteristic vector;

[0015] Step S13: Use a machine learning algorithm to train a load prediction model based on the load characteristic vector to obtain a load prediction model;

[0016] Step S14: Generate a dynamic load matrix according to the load prediction model to obtain a dynamic load matrix.

[0017] By collecting real memory access data for three typical application scenarios, namely video codec, online transaction database, and multitasking operating system, the present invention can ensure that the subsequent generated load models and test loads are more representative and practical, can more accurately reflect the performance of the chip in actual applications, avoid the limitations of using fixed loads for testing in traditional methods, and improve the effectiveness of test results. Extract key load characteristics such as access frequency, read-write ratio, and data block size from the application scenario dataset, convert the complex application scenario data into quantifiable feature vectors, provide the necessary input data for subsequent model training and load matrix generation, enable the load prediction model to learn the load patterns under different application scenarios, and generate a dynamic load closer to the real scenario. Using machine learning algorithms, such as random forest, to train the load prediction model based on the load feature vectors, a mapping relationship between the load characteristics and the chip performance metrics (such as latency and power consumption) can be established, enabling the model to predict the performance of the chip based on the input load characteristics, providing a basis for the generation of the dynamic load matrix, and supporting subsequent adaptive test condition adjustment. Based on the trained load prediction model and the preset load fluctuation pattern, a 24-hour dynamic load matrix containing load feature vectors per minute is generated, which can simulate various load conditions of the chip within a day, including peak and trough periods, as well as the switching of different application scenarios, making the chip test more comprehensive and closer to the actual usage situation, and thus more accurately evaluating the performance and reliability of the chip.

[0018] Preferably, step S2 includes the following steps:

[0019] Step S21: Apply dynamic load to the storage chip under test according to the dynamic load matrix to obtain real-time load status data; collect raw electrical performance data of the storage chip under test.

[0020] Step S22: Extract electrical performance characteristics from the raw electrical performance data to obtain electrical performance characteristic data.

[0021] Step S23: Perform feature correlation processing on the electrical performance characteristic data and the real-time load status data to obtain electrical performance feature vectors.

[0022] Step S24: Identify potential performance bottlenecks of the chip according to the electrical performance feature vectors to obtain performance bottleneck identification results; adjust the adaptive test conditions of the load prediction model according to the performance bottleneck identification results to obtain adjusted load parameters.

[0023] Step S25: Update the dynamic load of the dynamic load matrix according to the load prediction model and the adjusted load parameters to obtain an updated dynamic load matrix; generate real-time load status according to the updated dynamic load matrix to obtain real-time updated load status data.

[0024] Step S26: Generate an electrical characteristic curve based on the real-time updated load status data and the electrical performance feature vector to obtain the electrical characteristic curve.

[0025] In the present invention, by using an FPGA test platform to apply loads according to a dynamic load matrix and synchronously collect original electrical performance data such as current, voltage, and power consumption, real-time monitoring of the chip in a dynamic working environment is achieved, providing an original data basis for subsequent feature extraction and performance analysis. Compared with static test methods, it can more accurately reflect the performance of the chip in actual application scenarios. Features such as average current, peak current, average voltage, voltage fluctuation, average power consumption, and peak power consumption are extracted from the original electrical performance data, converting the high-frequency sampled original data into more representative feature data, reducing the complexity of data processing, and providing key parameters for subsequent identification of performance bottlenecks and generation of electrical characteristic curves. The extracted electrical performance feature data is associated with the real-time load status data to construct an electrical performance feature vector, establishing a direct connection between the electrical performance of the chip and the load it bears, providing data support for subsequent analysis of the impact of the load on the chip's electrical performance. By analyzing the electrical performance feature vector, potential performance bottlenecks of the chip under different load conditions can be identified, such as excessive voltage fluctuation or high power consumption. According to the identification results, the parameters of the load prediction model are dynamically adjusted, and the dynamic load matrix is updated, which can make the test process more intelligent, more targeted at testing the weak links of the chip, and improve the test efficiency and accuracy. According to the adjusted load prediction model and parameters, the dynamic load matrix is updated, and real-time updated load status data is generated, realizing the closed-loop control of the test process. The test load can be dynamically adjusted according to the real-time performance of the chip, so as to more effectively discover potential problems of the chip and improve the comprehensiveness of the test. By plotting the electrical characteristic curve, the change trend of the chip's electrical performance under different load conditions can be intuitively displayed, such as the relationship between power consumption and load intensity, voltage stability, etc., providing an intuitive reference basis for chip performance evaluation and facilitating the rapid identification of potential problems of the chip.

[0026] Preferably, step S3 includes the following steps:

[0027] Step S31: Generate simulation data sets according to the updated dynamic load matrix to obtain simulation data sets;

[0028] Step S32: Use the simulation data sets to simulate the storage behavior of the storage chip to be tested, and optimize the storage behavior simulation according to the electrical characteristic curve to obtain simulated behavior data;

[0029] Step S33: Perform refined annotation of read and write events on the simulated behavior data to obtain finely annotated behavior data;

[0030] Step S34: Conduct a delay distribution statistics on the refined labeling behavior data to obtain a delay statistics histogram; conduct an error pattern recognition on the refined labeling behavior data to obtain an error pattern feature vector; conduct a throughput fluctuation analysis on the refined labeling behavior data to obtain a throughput fluctuation curve;

[0031] Step S35: Conduct a temporal locality analysis on the refined labeling behavior data to obtain temporal locality data; conduct a spatial locality analysis on the refined labeling behavior data to obtain spatial locality data; generate locality feature parameters based on the temporal locality data and the spatial locality data to obtain locality feature parameters;

[0032] Step S36: Conduct a data flow feature synthesis on the delay statistics histogram, the error pattern feature vector, the throughput fluctuation curve, and the locality feature parameters to obtain data flow features;

[0033] Step S37: Construct a storage behavior map based on the data flow features and the updated dynamic load matrix to obtain a storage behavior map.

[0034] The present invention generates a simulated data set according to the updated dynamic load matrix, ensuring that the simulated data is consistent with the load characteristics of the actual application scenario, and can more effectively simulate the working state of the chip in the real environment, improving the accuracy and reliability of subsequent storage behavior simulation. The storage chip is read and written using the simulated data set to simulate its storage behavior under different load conditions, and the simulation process is optimized according to the electrical characteristic curve. For example, the influence of simulated voltage fluctuations on read and write latency is simulated to make the simulation results closer to the performance of the chip in the real working environment, improving the simulation accuracy. The simulated behavior data is finely labeled, adding detailed tag information to each read and write operation, such as operation type, data size, access address, latency, error type, etc., providing a richer and more refined data basis for subsequent data flow analysis and helping to understand the storage behavior of the chip more deeply. By performing latency distribution statistics, error pattern recognition, and throughput fluctuation analysis on the finely labeled behavior data, key performance indicators of the chip under different load conditions can be extracted, such as average latency, maximum latency, error rate, throughput, etc., providing data support for the subsequent construction of the storage behavior map. By analyzing the temporal locality and spatial locality of memory accesses and generating corresponding characteristic parameters, the data access patterns of the chip under different load conditions can be understood more deeply, such as the concentration and repeatability of data accesses, helping to identify potential performance bottlenecks and optimize the memory access strategy. Combining the latency statistical histogram, error pattern feature vector, throughput fluctuation curve, and locality characteristic parameters forms a complete data flow feature, comprehensively describing the storage behavior characteristics of the chip under different load conditions and providing comprehensive data input for the subsequent construction of the storage behavior map. By constructing the storage behavior map, the performance indicators of the chip under different load conditions can be visually displayed, such as using a heat map to show the distribution of average latency and a line chart to show the trend of throughput changing with the load, facilitating the intuitive analysis and comparison of the chip's performance under different load conditions and quickly identifying potential performance problems.

[0035] Preferably, step S4 includes the following steps:

[0036] Step S41: Perform real-time monitoring of the storage chip to be tested under dynamic load according to the updated dynamic load matrix to obtain real-time temperature and power consumption data;

[0037] Step S42: Extract thermal power consumption characteristics from the real-time temperature and power consumption data to obtain a thermal power consumption feature vector;

[0038] Step S43: Perform thermal stability analysis according to the thermal power consumption feature vector and the storage behavior map to obtain a thermal stability index;

[0039] Step S44: Perform energy efficiency ratio analysis based on the thermal power consumption feature vector and the storage behavior map to obtain the energy efficiency ratio index;

[0040] Step S45: Construct a thermal energy consumption feature matrix based on the thermal stability index, the energy efficiency ratio index, and the updated dynamic load matrix to obtain the thermal energy consumption feature matrix.

[0041] Through the use of an infrared thermal imager and a power analyzer to monitor the real-time temperature and power consumption of the chip, the present invention can obtain detailed information on the thermal behavior and power consumption changes of the chip under dynamic load, which can more accurately reflect the thermal performance and power consumption characteristics of the chip in the actual working environment than static testing, providing a reliable data basis for subsequent analysis. Key thermal power consumption features such as the highest temperature, average temperature, core area temperature, average power consumption, and peak power consumption are extracted from the real-time temperature and power consumption data, converting the complex temperature and power consumption data into more representative feature vectors, simplifying the subsequent analysis process, and providing necessary input parameters for thermal stability analysis and energy efficiency ratio analysis. Combining the thermal power consumption feature vector and the storage behavior map for thermal stability analysis can evaluate the performance stability of the chip at different temperatures, such as analyzing the impact of high temperature on read / write latency and error rate, so as to more comprehensively understand the reliability of the chip within different working temperature ranges. By analyzing the thermal power consumption feature vector and the storage behavior map, the energy efficiency ratio index of the chip can be calculated, such as power consumption per unit throughput or energy consumption per unit data read / write operation, so as to evaluate the energy efficiency of the chip under different load and temperature conditions, providing a reference basis for the energy-saving optimization of the chip. Integrating the thermal stability index, the energy efficiency ratio index, and the load characteristics in the updated dynamic load matrix into a matrix to construct a thermal energy consumption feature matrix, associating the thermal performance, power consumption characteristics, and load conditions of the chip, and providing comprehensive data support for the subsequent comprehensive evaluation of the chip quality.

[0042] Preferably, step S43 includes the following steps:

[0043] Step S431: Divide the temperature range according to the thermal power consumption feature vector to obtain temperature range data;

[0044] Step S432: Extract interval performance data from the storage behavior map according to the temperature range data to obtain an interval performance data set;

[0045] Step S433: Use the finite element analysis method to construct a thermal model based on the storage chip to be tested to obtain a chip thermal model;

[0046] Step S434: Verify and calibrate the chip thermal model according to the thermal power consumption feature vector to obtain a calibrated chip thermal model;

[0047] Step S435: Perform dynamic thermal characteristic analysis based on the interval performance dataset and the calibrated chip thermal model to obtain dynamic thermal characteristic data;

[0048] Step S436: Calculate the thermal stability index based on the dynamic thermal characteristic data to obtain the thermal stability index.

[0049] By dividing the temperature range of the chip into multiple intervals, the present invention can more meticulously analyze the performance of the chip in different temperature segments, avoiding the influence on performance caused by only focusing on the average temperature and ignoring temperature fluctuations, and providing a basis for subsequent extraction of interval performance data and thermal characteristic analysis. Extracting corresponding performance data from the storage behavior map according to the temperature interval data can obtain performance indicators of the chip in different temperature intervals, such as average latency, maximum latency, and error rate, providing data support for subsequent analysis of the influence of temperature on performance. Using the finite element analysis method to construct the thermal model of the chip can simulate the temperature distribution inside the chip, providing a virtual experimental platform for subsequent thermal characteristic analysis, and avoiding problems such as high cost and complex operation in actual testing. Verifying and calibrating the constructed chip thermal model using the actually measured thermal power consumption eigenvector can improve the accuracy and reliability of the model, ensuring that the model can more accurately reflect the actual thermal behavior of the chip. Combining the interval performance dataset and the calibrated chip thermal model for dynamic thermal characteristic analysis can more deeply understand the thermal behavior and performance of the chip under different temperature and load conditions, such as analyzing the influence of temperature fluctuations on read / write latency and error rate, providing a reference basis for the thermal design and optimization of the chip. Calculating the thermal stability index according to the results of the dynamic thermal characteristic analysis can quantify the performance stability of the chip in different temperature intervals, such as calculating the influence degree of temperature fluctuations on performance indicators, providing a more specific quantitative index for the quality assessment of the chip.

[0050] Preferably, step S435 includes the following steps:

[0051] Step S4351: Perform dynamic load temperature simulation based on the interval performance dataset and the calibrated chip thermal model to obtain dynamic temperature distribution data;

[0052] Step S4352: Obtain the chip structure and function data; extract the key area temperature according to the dynamic temperature distribution data and the chip structure data to obtain the key area temperature curve;

[0053] Step S4353: Calculate the transient thermal response index according to the key area temperature curve to obtain the transient thermal response index;

[0054] Step S4354: Perform load mode influence analysis based on the updated dynamic load matrix and the calibrated chip thermal model to obtain load mode influence data;

[0055] Step S4355: Integrate the transient thermal response metrics based on the load pattern impact data to obtain dynamic thermal characteristic data for dynamic thermal characteristic data integration.

[0056] Through the use of the interval performance data set and the calibrated chip thermal model for dynamic load temperature simulation, the present invention can obtain the dynamic temperature distribution data of the chip under different loads and times, which can more accurately reflect the temperature change of the chip in the actual working environment than static temperature analysis. By obtaining the chip structure and function data and extracting the temperature curves of the key areas in combination with the dynamic temperature distribution data, the temperature changes of the key parts of the chip, such as the memory cell array, control circuit, etc., can be analyzed more precisely, so as to more specifically evaluate the thermal reliability of the chip. Calculating the transient thermal response metrics, such as the temperature rise time, temperature overshoot, and temperature stabilization time, based on the temperature curves of the key areas can quantify the thermal response speed and stability of the chip, providing a reference for the thermal design and optimization of the chip. Using the updated dynamic load matrix and the calibrated chip thermal model for load pattern impact analysis can evaluate the impact of different load patterns on the chip temperature distribution, such as the impact of different read / write ratios or access address distributions on the chip temperature, so as to guide the optimization of the load strategy and reduce the thermal stress of the chip. Integrating the transient thermal response metrics, load pattern impact data, and dynamic temperature distribution data into dynamic thermal characteristic data can more comprehensively describe the thermal behavior and performance of the chip under different loads and times, providing a richer data basis for the calculation of subsequent thermal stability metrics.

[0057] Preferably, step S4352 is specifically:

[0058] Define the key areas for the chip structure and function data to obtain the key area coordinate information;

[0059] Perform temperature data mapping on the dynamic temperature distribution data and the key area coordinate information to obtain area temperature mapping data;

[0060] Extract the time-series temperature from the area temperature mapping data to obtain the key area time-series temperature data;

[0061] Generate a temperature curve for the key area time-series temperature data to obtain the key area temperature curve.

[0062] By defining the key areas of the chip, such as the memory cell array, control circuit, and I / O interface, etc., and extracting their coordinate information, the subsequent temperature analysis can be focused on these heat-sensitive areas, thus more effectively evaluating the thermal reliability of the chip and avoiding the influence of local hotspots being ignored due to the average temperature analysis of the entire chip. Mapping the dynamic temperature distribution data onto the coordinate information of the key areas can obtain the temperature data of each key area, providing the necessary data basis for subsequent timing temperature extraction and temperature curve generation. Extracting the temperature data of each key area at different time points to form the timing temperature data can track the changing trend of the key area temperature over time, providing data support for subsequent calculation of transient thermal response metrics. Plotting the timing temperature data of the key areas into a temperature curve can visually display the changing situation of the key area temperature over time, facilitating the observation of key thermal characteristics such as temperature fluctuations, peak temperatures, and temperature change rates, providing an intuitive reference for the thermal design and optimization of the chip.

[0063] Preferably, step S4354 is specifically as follows:

[0064] Define the load mode parameters according to the updated dynamic load matrix to obtain a set of load mode parameters;

[0065] Generate the dynamic load matrix variants according to the updated dynamic load matrix and the set of load mode parameters to obtain a set of load matrix variants;

[0066] Conduct multi-mode thermal simulations according to the set of load matrix variants and the calibrated chip thermal model to obtain a multi-mode temperature data set;

[0067] Conduct a comparative analysis of the thermal response metrics on the multi-mode temperature data set to obtain the thermal response comparison data;

[0068] Summarize the influence rules of the load mode according to the thermal response comparison data to obtain the load mode influence data.

[0069] By defining the key load parameters that affect the thermal characteristics of the chip, such as read / write frequency, read / write ratio, data block size, and access address distribution, etc., as well as their value ranges and change steps, a parameter basis can be provided for generating different load patterns subsequently, ensuring a more comprehensive evaluation of the chip's thermal performance. Based on the load pattern parameter set, multiple dynamic load matrix variants are generated, and each variant represents a different load pattern, which can simulate the working conditions of the chip under various different load conditions, thereby more comprehensively evaluating the chip's thermal performance. Using the calibrated chip thermal model to perform thermal simulations on each load matrix variant, temperature distribution data of the chip under different load patterns can be obtained, providing a data basis for subsequent comparative analysis of thermal response indicators. By comparing and analyzing the thermal response indicators under different load patterns, such as the maximum temperature, average temperature, temperature rise time, etc., the influence degree of different load patterns on the chip's thermal characteristics can be evaluated, providing a reference for optimizing the load strategy. Summarizing the influence rules of different load patterns on the chip's thermal characteristics, such as the influence of read / write frequency on the maximum temperature, the influence of read / write ratio on the average temperature, etc., can help to understand more deeply the relationship between the load pattern and the chip's thermal characteristics, providing guidance for the thermal design and optimization of the chip.

[0070] Preferably, step S5 includes the following steps:

[0071] Step S51: Standardize the characteristic data of the updated dynamic load matrix, electrical characteristic curve, storage behavior map, and thermal energy consumption characteristic matrix to obtain a standardized characteristic data set;

[0072] Step S52: Determine the weights of the standardized characteristic data set to obtain characteristic weights;

[0073] Step S53: Construct a quality evaluation model based on the standardized characteristic data set and the characteristic weights to obtain a quality evaluation model;

[0074] Step S54: Use the quality evaluation model to calculate the comprehensive quality score of the standardized characteristic data set to obtain a comprehensive quality score;

[0075] Step S55: Classify and screen the chips according to the comprehensive quality score to obtain the chip classification result.

[0076] By standardizing the characteristic data of the updated dynamic load matrix, electrical characteristic curve, storage behavior map, and thermal energy consumption characteristic matrix, the present invention eliminates the differences in dimension and order of magnitude between different characteristics, avoids certain characteristics from occupying too much weight in quality assessment, and ensures the fairness and objectivity of the assessment results. The analytic hierarchy process (AHP) is used to determine the weights of each characteristic, which can distinguish the importance of different characteristics to the chip quality according to expert experience and actual application requirements, making the quality assessment model more in line with the needs of actual application scenarios. Using the standardized characteristic data set and characteristic weights to construct a quality assessment model based on support vector machine (SVM) can establish the mapping relationship between the characteristic data and the chip quality grade, realizing the quantitative assessment of chip quality. Using the constructed quality assessment model to predict the standardized characteristic data set can calculate the comprehensive quality score of each chip, integrating the assessment results of multiple characteristics into a single index, which is convenient for comparing and ranking the chip quality. Classifying and screening the chips according to the comprehensive quality score can divide the chips into different quality grades, such as excellent, qualified, and unqualified, providing a decision-making basis for chip production, manufacturing, market sales, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 It is a schematic flow chart of the steps of a quality assessment method for an embedded memory chip;

[0078] Figure 2 It is a schematic detailed implementation step flow chart of step S4 in the present invention;

[0079] Figure 3 It is a schematic detailed implementation step flow chart of step S43 in the present invention.

[0080] The implementation, functional features, and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0081] The technical method of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those skilled in the art within the scope of the present invention without creative work fall within the protection scope of the present invention.

[0082] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0083] It should be understood that although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed related items.

[0084] To achieve the above object, please refer to Figures 1 to 3 , a method for evaluating the quality of an embedded storage chip, comprising the following steps:

[0085] Step S1: Construct a load prediction model according to a preselected target application scenario to obtain a load prediction model; generate a dynamic load matrix according to the load prediction model to obtain a dynamic load matrix;

[0086] Step S2: Extract electrical performance feature vectors for the storage chip to be tested according to the dynamic load matrix to obtain electrical performance feature vectors; adjust the adaptive test conditions according to the electrical performance feature vectors and the load prediction model to obtain adjusted load parameters; update the dynamic load matrix according to the load prediction model and the adjusted load parameters to obtain an updated dynamic load matrix; generate an electrical characteristic curve according to the updated dynamic load matrix to obtain an electrical characteristic curve;

[0087] Step S3: Perform storage behavior simulation processing according to the updated dynamic load matrix to obtain simulated behavior data; perform data flow analysis on the simulated behavior data to obtain data flow characteristics; construct a storage behavior map according to the data flow characteristics and the updated dynamic load matrix to obtain a storage behavior map;

[0088] Step S4: Extract thermal power consumption feature vectors for the storage chip to be tested according to the updated dynamic load matrix to obtain thermal power consumption feature vectors; perform thermal stability analysis according to the thermal power consumption feature vectors and the storage behavior map to obtain a thermal stability index; construct a thermal energy consumption feature matrix according to the thermal stability index and the updated dynamic load matrix to obtain a thermal energy consumption feature matrix;

[0089] Step S5: Construct a quality evaluation model based on the updated dynamic load matrix, electrical characteristic curve, storage behavior map, and thermal energy consumption characteristic matrix to obtain the quality evaluation model; calculate the comprehensive quality score using the quality evaluation model to obtain the comprehensive quality score; perform chip grading and screening based on the comprehensive quality score to obtain the chip grading result, so as to implement the quality evaluation task of the embedded storage chip.

[0090] In the embodiment of the present invention, with reference to Figure 1 As shown, it is a schematic diagram of the step flow of the quality evaluation method for the embedded storage chip of the present invention. In this example, the quality evaluation method for the embedded storage chip includes the following steps:

[0091] Step S1: Construct a load prediction model according to a preselected target application scenario to obtain the load prediction model; generate a dynamic load matrix according to the load prediction model to obtain the dynamic load matrix;

[0092] In the embodiment of the present invention, first, for the three application scenarios of preselected video codec, online transaction database, and multitasking operating system, load characteristic data such as access frequency, read-write ratio, and data block size are collected, and a load prediction model is trained using the random forest algorithm to predict the delay and power consumption of the chip under different loads. Then, based on this model and a preset load fluctuation pattern, a 24-hour dynamic load matrix containing load characteristic vectors per minute is generated to simulate the load conditions of the chip at different time periods.

[0093] Step S2: Extract the electrical performance characteristic vector of the storage chip to be tested according to the dynamic load matrix to obtain the electrical performance characteristic vector; adjust the adaptive test conditions according to the electrical performance characteristic vector and the load prediction model to obtain the adjusted load parameters; perform dynamic load update on the dynamic load matrix according to the load prediction model and the adjusted load parameters to obtain the updated dynamic load matrix; generate an electrical characteristic curve according to the updated dynamic load matrix to obtain the electrical characteristic curve;

[0094] In the embodiment of the present invention, use the FPGA test platform to apply load to the chip according to the dynamic load matrix, and use an oscilloscope and a power analyzer to collect current, voltage, and power consumption data. Then, extract electrical performance characteristics such as average current, peak current, average voltage, voltage fluctuation, average power consumption, and peak power consumption to form a characteristic vector. If it is detected that the voltage fluctuation exceeds the preset threshold, adjust the weight of the corresponding load characteristic in the load prediction model, and update the dynamic load matrix to reduce the subsequent load intensity. Finally, draw an electrical characteristic curve to show the change trend of the chip's electrical performance over time.

[0095] Step S3: Perform storage behavior simulation processing based on the updated dynamic load matrix to obtain simulated behavior data; perform data flow analysis on the simulated behavior data to obtain data flow characteristics; construct a storage behavior map based on the data flow characteristics and the updated dynamic load matrix to obtain a storage behavior map;

[0096] In the embodiment of the present invention, simulated data is generated based on the updated dynamic load matrix for simulating the data access pattern in a real application scenario. Chip read and write operations are performed using the simulated data, and latency and error information are recorded to form simulated behavior data. By analyzing the simulated behavior data, data flow characteristics such as latency distribution, error rate, throughput, and temporal locality and spatial locality are extracted. Finally, a storage behavior map is constructed in the form of a heat map to display the chip performance metrics under different combinations of load characteristics.

[0097] Step S4: Extract thermal power consumption characteristics of the storage chip to be tested based on the updated dynamic load matrix to obtain a thermal power consumption feature vector; perform thermal stability analysis based on the thermal power consumption feature vector and the storage behavior map to obtain a thermal stability index; construct a thermal energy consumption feature matrix based on the thermal stability index and the updated dynamic load matrix to obtain a thermal energy consumption feature matrix;

[0098] In the embodiment of the present invention, an infrared thermal imager and a power analyzer are used to collect temperature and power consumption data of the chip under different loads, and thermal power consumption characteristics such as the highest temperature, average temperature, peak power consumption, and average power consumption are extracted. Combining the thermal power consumption feature vector and the storage behavior map, the influence of temperature on the performance metrics is analyzed, and the degree of performance metric fluctuation in different temperature ranges is calculated as the thermal stability index. Finally, the load characteristics, thermal power consumption characteristics, and thermal stability index are integrated into a matrix to form a thermal energy consumption feature matrix.

[0099] Step S5: Construct a quality evaluation model based on the updated dynamic load matrix, electrical characteristic curve, storage behavior map, and thermal energy consumption feature matrix to obtain a quality evaluation model; use the quality evaluation model to calculate a comprehensive quality score to obtain a comprehensive quality score; perform chip grading and screening based on the comprehensive quality score to obtain a chip grading result, so as to implement the quality evaluation task of the embedded storage chip;

[0100] In the embodiment of the present invention, the load characteristics of the updated dynamic load matrix, electrical characteristic curve data, storage behavior map data, and thermal energy consumption feature matrix data are standardized. Then, the analytic hierarchy process (AHP) is used to determine the weights of each feature, and the support vector machine (SVM) algorithm is used to construct a quality evaluation model. The trained model is used to predict the standardized feature data to obtain the comprehensive quality score of each chip. Finally, the chips are graded and screened according to the predefined score range.

[0101] Preferably, step S1 includes the following steps:

[0102] Step S11: Collect application scenario data according to a preselected target application scenario to obtain an application scenario data set;

[0103] Step S12: Extract load characteristics from the application scenario data set to obtain a load characteristic vector;

[0104] Step S13: Use a machine learning algorithm to train a load prediction model according to the load characteristic vector to obtain a load prediction model;

[0105] Step S14: Generate a dynamic load matrix according to the load prediction model to obtain a dynamic load matrix.

[0106] In the embodiment of the present invention, three target application scenarios are preselected: video codec, high-frequency database transaction processing, and multi-task operating system operation. For the video codec scenario, use the H.265 encoding standard to encode and decode 10 videos with a resolution of 4K, and use the storage performance analysis tool PerfMon to record the timestamp, data size, operation type (read / write), access address, etc. of each read and write operation, and continuously collect data for 2 hours. For the high-frequency database transaction processing scenario, use the MySQL database, pre-build a database containing 1 million records, execute 1000 mixed transactions including insert, delete, update, and query operations, and use the built-in performance monitoring tool Performance Schema of MySQL to record the execution time, data size, operation type, access address, etc. of each database operation, and continuously collect data for 1 hour. For the multi-task operating system operation scenario, run 5 CPU-intensive tasks and 5 I / O-intensive tasks simultaneously on the Ubuntu 20.04 operating system, and use the system-level performance analysis tool SystemTap to monitor the read and write activities of the storage chip, record the timestamp, data size, operation type, access address, etc. of each read and write operation, and continuously collect data for 3 hours. Store the data collected in the three scenarios as CSV files respectively to form an application scenario data set.

[0107] Process the application scenario dataset using the Python programming language and the Pandas data processing library. First, read the data in the CSV file and convert it into the Pandas DataFrame format. Then, for each application scenario, extract the following load characteristics: average read / write data size (calculate the average of the data sizes of each read / write operation), peak read / write data size (calculate the maximum of the data sizes of each read / write operation), read / write operation frequency (calculate the number of read / write operations occurring per unit time), read / write ratio (calculate the ratio of the number of read operations to the number of write operations), skewness of the access addresses (calculate the skewness of the access address distribution, which is used to measure the concentration degree of the access addresses). Combine the five extracted load characteristics into a five-dimensional numerical vector as the load characteristic vector of this application scenario. Repeat the above operations for each application scenario, and finally obtain three five-dimensional load characteristic vectors.

[0108] Build a load prediction model using the Python programming language and the Scikit-learn machine learning library. Select the Support Vector Regression (SVR) algorithm as the model training algorithm. Use the three five-dimensional load characteristic vectors extracted in step S12 as input features, and use the previously measured average latency, maximum latency, and average power consumption of the storage chip under the corresponding scenario as target variables. Divide the dataset into a training set and a test set with a ratio of 8:2. Use the training set data to train the SVR model, and use the test set data to evaluate the prediction performance of the model. Use the Mean Squared Error (MSE) as the evaluation metric. Optimize the hyperparameters (such as kernel function type, regularization parameter, etc.) of the SVR model through the grid search method to minimize the MSE. After training, obtain the final load prediction model.

[0109] Set the test duration to 10 hours. Divide the test duration into 100 time periods, each time period being 6 minutes. Use the Python programming language to generate a 100-row and 5-column matrix as the dynamic load matrix. For each time period, first generate a five-dimensional load characteristic vector according to the preset load change pattern (such as sine wave, random fluctuation, etc.). Then, input this load characteristic vector into the load prediction model trained in step S13 to predict the performance metrics (average latency, maximum latency, and average power consumption) of the storage chip under this load. Use the predicted performance metrics as constraint conditions to adjust the generated five-dimensional load characteristic vector to ensure that the predicted performance metrics are within the preset range. Store the adjusted five-dimensional load characteristic vector in the corresponding row of the dynamic load matrix. The finally obtained dynamic load matrix contains the load characteristic vectors of 100 time periods for subsequent testing.

[0110] Preferably, step S2 includes the following steps:

[0111] Step S21: Apply dynamic load to the storage chip under test according to the dynamic load matrix to obtain real-time load status data; collect electrical performance data of the storage chip under test to obtain original electrical performance data;

[0112] Step S22: Extract electrical performance features from the original electrical performance data to obtain electrical performance feature data;

[0113] Step S23: Perform feature correlation processing on the electrical performance feature data and the real-time load status data to obtain an electrical performance feature vector;

[0114] Step S24: Identify potential performance bottlenecks of the chip according to the electrical performance feature vector to obtain a performance bottleneck identification result; adaptively adjust the test conditions of the load prediction model according to the performance bottleneck identification result to obtain adjusted load parameters;

[0115] Step S25: Update the dynamic load of the dynamic load matrix according to the load prediction model and the adjusted load parameters to obtain an updated dynamic load matrix; generate a real-time load status according to the updated dynamic load matrix to obtain real-time updated load status data;

[0116] Step S26: Generate an electrical characteristic curve according to the real-time updated load status data and the electrical performance feature vector to obtain an electrical characteristic curve.

[0117] In the embodiment of the present invention, an FPGA development board is used to control the load of the storage chip under test. The dynamic load matrix is imported into the FPGA development board. The FPGA development board generates corresponding control signals according to the load feature vectors in each time period of the dynamic load matrix, and controls the test platform to send read / write requests to the storage chip under test. Each read / write request contains information such as a specific data size, access address, operation type (read / write), etc., to simulate the load characteristics defined in the dynamic load matrix. At the same time, a high-precision digital oscilloscope is used to collect the current and voltage signals of the storage chip in real time at a sampling rate of 1 GHz, and a power analyzer is used to collect power consumption data at the same sampling rate. The collected current, voltage, and power consumption data are stored as a CSV file to form the original electrical performance data. The currently applied load characteristics are recorded once per second to generate real-time load status data, which is also stored as a CSV file.

[0118] Use a Python script to process the original electrical performance data. First, read the current, voltage, and power consumption data from a CSV file. Then, perform denoising on the data, using the wavelet transform method to remove high-frequency noise. Next, calculate the instantaneous power at each sampling point and extract the following electrical performance characteristics: average current, peak current, average voltage, voltage fluctuation range (the difference between the maximum voltage and the minimum voltage), average power consumption, and peak power consumption. Store the extracted feature data as a new CSV file to form the electrical performance feature data.

[0119] Use a Python script to associate the electrical performance feature data with the real-time load status data. First, read the data from two CSV files. Since the sampling rate of the electrical performance data is much higher than the recording frequency of the real-time load status data, it is necessary to downsample the electrical performance feature data to match the time interval of the real-time load status data. Use the average value method for downsampling. Then, merge the electrical performance characteristics corresponding to each time point with the load status data to form a vector containing load characteristics and electrical performance characteristics, that is, the electrical performance feature vector. Store the electrical performance feature vectors at all time points as a new CSV file.

[0120] Use a Python script and a pre-trained machine learning model (such as a random forest model) to analyze the electrical performance feature vector and identify potential performance bottlenecks of the chip. For example, if it is found that the peak current is too high and the voltage fluctuation range is large during high-frequency write operations of the chip, it is considered that there is a bottleneck in the driving ability of the chip. Record the identified performance bottlenecks (such as driving ability, read / write speed, power consumption, etc.) as the performance bottleneck identification results. According to the performance bottleneck identification results, adjust the input parameter weights of the load prediction model. For example, if a driving ability bottleneck is identified, increase the weights of the features related to write operations (such as write frequency, write data size) in the load feature vector. Take the adjusted parameter weights as the adjusted load parameters.

[0121] Use a Python script to apply the adjusted load parameters to the dynamic load matrix. The specific operation is as follows: input the load feature vector of each time period in the dynamic load matrix into the adjusted load prediction model to re-predict the performance metrics of the storage chip. According to the prediction results, fine-tune the load feature vector, such as increasing or decreasing the read / write frequency, adjusting the read / write ratio, etc., to make the predicted performance metrics closer to the target values. Update the adjusted load feature vector to the dynamic load matrix to obtain the updated dynamic load matrix. According to the updated dynamic load matrix, generate real-time load status data and store it as a CSV file, containing the load feature information at each time point, called the real-time updated load status data.

[0122] Using the Matplotlib library in Python, generate electrical characteristic curves based on real-time updated load status data and electrical performance feature vectors. Take the load characteristics (such as read / write frequency, data size, read / write ratio, etc.) in the real-time updated load status data as the abscissa, and take the electrical performance characteristics (such as average current, peak current, average voltage, voltage fluctuation range, average power consumption, peak power consumption, etc.) in the electrical performance feature vector as the ordinate. Plot multiple curves, where each curve represents the change trend of an electrical performance characteristic with the load characteristic. For example, a curve of average power consumption versus read / write frequency can be plotted, a curve of peak current versus data size can be plotted, etc. Save the generated electrical characteristic curves as picture files, such as PNG or SVG format, for subsequent analysis and evaluation. These curves intuitively show the electrical performance of the chip under different load conditions, such as the relationship between power consumption and load intensity, voltage stability, etc., providing key data for subsequent quality assessment.

[0123] Preferably, step S3 includes the following steps:

[0124] Step S31: Generate simulation data according to the updated dynamic load matrix to obtain a simulation data set;

[0125] Step S32: Use the simulation data set to simulate the storage behavior of the storage chip to be tested, and optimize the storage behavior simulation according to the electrical characteristic curves to obtain simulated behavior data;

[0126] Step S33: Refinedly label the read / write events of the simulated behavior data to obtain refined labeled behavior data;

[0127] Step S34: Conduct delay distribution statistics on the refined labeled behavior data to obtain a delay statistics histogram; conduct error mode recognition on the refined labeled behavior data to obtain an error mode feature vector; conduct throughput fluctuation analysis on the refined labeled behavior data to obtain a throughput fluctuation curve;

[0128] Step S35: Conduct temporal locality analysis on the refined labeled behavior data to obtain temporal locality data; conduct spatial locality analysis on the refined labeled behavior data to obtain spatial locality data; generate locality characteristic parameters according to the temporal locality data and the spatial locality data to obtain locality characteristic parameters;

[0129] Step S36: Synthesize the data flow characteristics of the delay statistics histogram, the error mode feature vector, the throughput fluctuation curve, and the locality characteristic parameters to obtain data flow characteristics;

[0130] Step S37: Construct a storage behavior map according to the data flow characteristics and the updated dynamic load matrix to obtain a storage behavior map.

[0131] In the embodiments of the present invention, a Python script is used to generate a simulated data set according to the updated dynamic load matrix. Each row in the updated dynamic load matrix is traversed to extract the load feature vector corresponding to that time period. According to the information such as the read-write ratio and access address distribution in the load feature vector, corresponding simulated data is generated. For example, if the load feature vector indicates that the read operation ratio is 70% and the write operation ratio is 30% during this time period, then 70% random read data and 30% random write data are generated. The access address is generated according to the address distribution characteristics in the load feature vector, such as uniform distribution, normal distribution or other specific distributions. The simulated data generated for each time period is stored as a binary file, and the binary files for all time periods constitute the simulated data set.

[0132] Using an FPGA test platform, the simulated data set is written into the storage chip under test, and the data in the storage chip is read. During the simulation process, the start time and end time of each read-write operation are recorded, and the latency of each read-write operation is calculated. At the same time, any errors that occur are recorded, such as data verification errors, write failures, etc. The recorded latency and error information are saved as a CSV file. According to the electrical characteristic curve generated in step S26, the storage behavior simulation is optimized. For example, if the electrical characteristic curve shows that the voltage fluctuates greatly under high load in the chip, then during the simulation process, according to the real-time load intensity, the influence of the corresponding voltage fluctuation on the read-write latency is simulated, and the adjusted latency data is recorded in the CSV file, and finally the simulated behavior data is obtained.

[0133] Use a Python script to perform fine-grained annotation on the simulated behavior data. Read the data in the CSV file, and add detailed labels to each read-write operation record, including operation type (read / write), data size, access address, latency, error type (if any), etc. The annotated data is saved as a new CSV file, constituting the fine-labeled behavior data.

[0134] Use a Python script and statistical analysis libraries (such as NumPy, SciPy) to analyze the fine-labeled behavior data. First, count the latency data of all read-write operations and draw a latency distribution histogram to show the number of operations in different latency ranges. Then, analyze the recorded error information to identify common error patterns, such as bit flip errors, data loss errors, etc. The number of occurrences of each error pattern is counted as a vector, constituting the error pattern feature vector. Finally, calculate the throughput (the amount of data read and written per unit time) for each time period and draw a throughput fluctuation curve to show the change trend of throughput over time.

[0135] Use a Python script to perform locality analysis on the fine-label behavior data. Temporal locality analysis: Statistically analyze the time intervals between multiple accesses to the same address, and calculate the average and variance of the access time intervals as the temporal locality data. Spatial locality analysis: Statistically analyze the access frequencies of adjacent addresses, and calculate the ratio of the access frequency of adjacent addresses to the access frequency of random addresses as the spatial locality data. Based on the temporal locality data (average access time interval and variance) and the spatial locality data (ratio of access frequencies of adjacent addresses), calculate locality characteristic parameters, such as the temporal locality coefficient and the spatial locality coefficient.

[0136] Integrate the latency statistical histogram, error pattern feature vector, throughput fluctuation curve, and locality characteristic parameters to form a comprehensive data stream feature. A feature vector or other data structure can be used to represent the data stream feature. For example, the histogram can be converted into a vector form, the fluctuation curve can be converted into a series of feature point coordinates, and these data can be combined with the error pattern feature vector and locality characteristic parameters into a larger feature vector as the final data stream feature.

[0137] Use Python's Matplotlib library or other visualization tools to construct a storage behavior map based on the data stream feature and the updated dynamic load matrix. Use different load conditions (such as read / write frequencies, data sizes, read / write ratios, etc.) in the updated dynamic load matrix as the abscissa or different dimensions, and use the various metrics in the data stream feature (such as average latency, maximum latency, error rate, throughput, temporal locality coefficient, spatial locality coefficient, etc.) as the ordinate or represent them using visual elements such as color and size. Generate multi-dimensional charts, heatmaps, or other visual forms of storage behavior maps to intuitively display the changing trends of key metrics such as data latency, error rate, throughput, etc., and locality characteristics of the chip under different load conditions. For example, a heatmap can be used to show the distribution of the average latency under different load conditions, a line chart can be used to show the trend of throughput changing with the load, and a scatter plot can be used to show the distribution of locality characteristic parameters. This will provide a comprehensive visual representation clearly showing the response characteristics of the chip under various workloads.

[0138] Preferably, step S4 includes the following steps:

[0139] Step S41: Perform real-time monitoring of the storage chip under test under dynamic load according to the updated dynamic load matrix to obtain real-time temperature and power consumption data;

[0140] Step S42: Extract thermal power consumption feature vectors from the real-time temperature and power consumption data;

[0141] Step S43: Perform thermal stability analysis based on the thermal power consumption feature vector and the storage behavior map to obtain a thermal stability index;

[0142] Step S44: Perform energy efficiency ratio analysis based on the thermal power consumption feature vector and the storage behavior map to obtain an energy efficiency ratio index;

[0143] Step S45: Construct a thermal energy consumption feature matrix based on the thermal stability index, the energy efficiency ratio index, and the updated dynamic load matrix to obtain a thermal energy consumption feature matrix.

[0144] As an example of the present invention, referring to Figure 2 as shown, in this example, step S4 includes:

[0145] Step S41: Perform real-time monitoring of the storage chip under test under dynamic load according to the updated dynamic load matrix to obtain real-time temperature and power consumption data;

[0146] In the embodiment of the present invention, an infrared thermal imager and a power analyzer are used to perform real-time temperature and power consumption monitoring on the storage chip under test running on the FPGA test platform. Align the infrared thermal imager with the chip under test, set the acquisition frequency to 1 Hz, record the temperature distribution data on the chip surface, and save the temperature data as a thermal map sequence file. At the same time, use the power analyzer to record the power consumption data of the chip at a sampling frequency of 1 Hz and save the power consumption data as a CSV file. Associate the thermal map sequence file and the power consumption data file to form real-time temperature and power consumption data, ensuring that each time point contains the corresponding temperature distribution and power consumption value. The test process is synchronized with the application of dynamic load, and the same updated dynamic load matrix (output of step S25) is used to drive the load.

[0147] Step S42: Extract thermal power consumption features from the real-time temperature and power consumption data to obtain a thermal power consumption feature vector;

[0148] In the embodiment of the present invention, Python scripts are used to process the real-time temperature and power consumption data. Read the thermal map sequence file, and extract the maximum temperature, average temperature, and the temperature of the core area of the chip at each time point. The definition of the core area can be determined according to the chip design drawing. At the same time, read the power consumption data CSV file and extract the average power consumption and peak power consumption at each time point. Combine the maximum temperature, average temperature, core area temperature, average power consumption, and peak power consumption at each time point into a five-dimensional vector as the thermal power consumption feature vector at that time point. Save the thermal power consumption feature vectors of all time points as a new CSV file.

[0149] Step S43: Perform thermal stability analysis based on the thermal power consumption feature vector and the storage behavior map to obtain a thermal stability index;

[0150] In the embodiments of the present invention, a Python script is used to perform thermal stability analysis by combining the thermal power consumption feature vector and the storage behavior map. The temperature range of the chip is divided into multiple intervals, such as 25°C - 35°C, 35°C - 45°C, 45°C - 55°C, etc. For each temperature interval, the corresponding performance index data in the storage behavior map is extracted, such as average latency, maximum latency, error rate, etc. The changing trends of the performance indexes in different temperature intervals are analyzed, for example, observing whether the average latency increases with the increase of temperature and whether the error rate increases with the increase of temperature. According to the analysis results, thermal stability indexes are calculated, such as the change rate of the performance indexes in different temperature intervals, the influence degree of temperature on the performance indexes, etc. The calculated thermal stability indexes are saved to a file.

[0151] Step S44: Perform energy efficiency ratio analysis based on the thermal power consumption feature vector and the storage behavior map to obtain the energy efficiency ratio index;

[0152] In the embodiments of the present invention, a Python script is used to perform energy efficiency ratio analysis by combining the thermal power consumption feature vector and the storage behavior map. For each time point, the energy efficiency ratio of the chip is calculated, such as power consumption per unit throughput (power consumption divided by throughput) or energy consumption per unit data read / write operation (power consumption divided by the amount of read / written data). The calculated energy efficiency ratio data is associated with the corresponding load conditions (from the updated dynamic load matrix). The changing trends of the energy efficiency ratio with load and temperature are analyzed, for example, observing whether the energy efficiency ratio decreases with the increase of load and whether it decreases with the increase of temperature. The analysis results are presented in the form of a chart, and energy efficiency ratio indexes are calculated, such as the average energy efficiency ratio under different load conditions, the change rate of the energy efficiency ratio with temperature, etc.

[0153] Step S45: Construct a thermal energy consumption feature matrix based on the thermal stability index, the energy efficiency ratio index, and the updated dynamic load matrix to obtain the thermal energy consumption feature matrix;

[0154] In the embodiments of the present invention, a Python script is used to integrate the thermal stability index, the energy efficiency ratio index, and the load feature data in the updated dynamic load matrix into a matrix to form the thermal energy consumption feature matrix. Each row of the matrix represents a time period, and each column represents different features, including load features (such as read / write frequency, data size, read / write ratio, etc.), thermal stability index, and energy efficiency ratio index. The constructed thermal energy consumption feature matrix is saved as a CSV file for subsequent comprehensive evaluation of chip quality.

[0155] Preferably, step S43 includes the following steps:

[0156] Step S431: Divide the temperature intervals according to the thermal power consumption feature vector to obtain temperature interval data;

[0157] Step S432: Extract interval performance data from the storage behavior map according to the temperature interval data to obtain an interval performance data set;

[0158] Step S433: Use the finite element analysis method to construct a thermal model based on the storage chip to be measured to obtain a chip thermal model;

[0159] Step S434: Verify and calibrate the chip thermal model according to the thermal power consumption feature vector to obtain a calibrated chip thermal model;

[0160] Step S435: Perform dynamic thermal characteristic analysis according to the interval performance data set and the calibrated chip thermal model to obtain dynamic thermal characteristic data;

[0161] Step S436: Calculate the thermal stability index according to the dynamic thermal characteristic data to obtain the thermal stability index.

[0162] As an example of the present invention, refer to Figure 3 As shown, in this example, step S43 includes:

[0163] Step S431: Divide the temperature range according to the thermal power consumption feature vector to obtain temperature interval data;

[0164] In the embodiment of the present invention, Python scripts and the NumPy library are used to process the thermal power consumption feature vector. Read the thermal power consumption feature vector CSV file and extract the highest temperature data at all time points. According to the distribution of the highest temperature data, the temperature range is divided into five intervals, such as 25°C - 35°C, 35°C - 45°C, 45°C - 55°C, 55°C - 65°C, and 65°C - 75°C. Each interval contains the time point data within this temperature range. Save each temperature interval and its contained time point information in dictionary format to form temperature interval data.

[0165] Step S432: Extract interval performance data from the storage behavior map according to the temperature interval data to obtain an interval performance data set;

[0166] In the embodiment of the present invention, Python scripts are used to extract the corresponding performance data from the storage behavior map according to the temperature interval data. For each temperature interval, extract the performance index data corresponding to all time points within this interval, such as average latency, maximum latency, and error rate. Save each temperature interval and its corresponding performance index data as a separate CSV file, and all CSV files form an interval performance data set.

[0167] Step S433: Use the finite element analysis method to construct a thermal model based on the storage chip to be measured to obtain a chip thermal model;

[0168] In the embodiments of the present invention, a thermal model of the storage chip to be tested is constructed using COMSOL Multiphysics finite element analysis software. The CAD model of the chip is imported, and the material properties of the chip are defined, such as thermal conductivity, specific heat capacity, etc. The boundary conditions of the chip are set, such as heat dissipation coefficient, ambient temperature, etc. According to the structure and working principle of the chip, the heat sources inside the chip are defined, such as the heat generation power in the core area. The heat transfer module of COMSOL is used for mesh generation and solution to obtain the temperature distribution of the chip. The constructed thermal model is saved as a COMSOL model file.

[0169] Step S434: Verify and calibrate the chip thermal model according to the thermal power consumption eigenvector to obtain the calibrated chip thermal model;

[0170] In the embodiments of the present invention, the core area temperature data in the thermal power consumption eigenvector is imported into the COMSOL Multiphysics software and compared with the simulation results of the chip thermal model. If there is a large deviation between the simulation results and the measured data, the parameters of the thermal model are adjusted, such as the heat source power, heat dissipation coefficient, etc., until the simulation results match the measured data. The calibrated thermal model is saved as a new COMSOL model file as the calibrated chip thermal model.

[0171] Step S435: Perform dynamic thermal characteristic analysis according to the interval performance dataset and the calibrated chip thermal model to obtain dynamic thermal characteristic data;

[0172] In the embodiments of the present invention, Python scripts and COMSOL Multiphysics software are used for dynamic thermal characteristic analysis. For each temperature interval, the load characteristic data in the interval performance dataset is imported into the calibrated chip thermal model for transient thermal simulation. The chip temperature distribution data at each time point is recorded, and the temperature curves of the key areas are extracted. Analyze the relationship between the temperature curves of the key areas and the performance index data, such as analyzing the impact of temperature fluctuations on read / write latency and error rate. The temperature data, performance index data, and their relationships obtained from the simulation are saved as files to form dynamic thermal characteristic data.

[0173] Step S436: Calculate the thermal stability index according to the dynamic thermal characteristic data to obtain the thermal stability index;

[0174] In the embodiments of the present invention, Python scripts are used to process the dynamic thermal characteristic data. The temperature fluctuations in the key areas of the chip and the changes in the performance indicators in different temperature ranges are analyzed. Thermal stability indicators are calculated, such as the degree of influence of temperature fluctuations on the performance indicators and the stability of the performance indicators in different temperature ranges. Statistical analysis methods can be adopted, such as calculating the correlation coefficient between temperature fluctuations and changes in performance indicators and calculating the variance of performance indicators in different temperature ranges. The calculated thermal stability indicators are saved to a file.

[0175] Preferably, step S435 includes the following steps:

[0176] Step S4351: Perform dynamic load temperature simulation according to the interval performance data set and the calibrated chip thermal model to obtain dynamic temperature distribution data;

[0177] Step S4352: Obtain the chip structure function data; extract the temperature of the key area according to the dynamic temperature distribution data and the chip structure data to obtain the temperature curve of the key area;

[0178] Step S4353: Calculate the transient thermal response index according to the temperature curve of the key area to obtain the transient thermal response index;

[0179] Step S4354: Analyze the influence of the load mode according to the updated dynamic load matrix and the calibrated chip thermal model to obtain the load mode influence data;

[0180] Step S4355: Integrate the transient thermal response index with the dynamic thermal characteristic data according to the load mode influence data to obtain the dynamic thermal characteristic data.

[0181] In the embodiments of the present invention, Python scripts are used to control the COMSOL Multiphysics software to perform dynamic load temperature simulation. For each temperature range, the load characteristic data (such as read / write frequency, data size) in the interval performance data set is used as input parameters and applied to the calibrated chip thermal model. Set the transient analysis parameters in COMSOL, such as the time step, simulation duration, etc. Run the simulation to obtain the temperature distribution data of the chip at different time points. Save the temperature distribution data of each time point as a separate heat map file, and all the heat map files constitute the dynamic temperature distribution data.

[0182] Obtain chip structure and function data from the chip design document, including information such as the location, size, and material properties of each functional module of the chip. Use a Python script to read the chip structure and function data, and define the key regions of the chip based on these data, such as the memory cell array, control circuit, I / O interface, etc. Use a Python script to read the dynamic temperature distribution data and extract the average temperature of the key regions at each time point. Plot the data of the average temperature of each key region changing with time as a curve to obtain the key region temperature curve.

[0183] Use a Python script and a signal processing library (such as SciPy) to analyze the key region temperature curve. Calculate transient thermal response metrics, such as the temperature rise time (the time required for the temperature to rise from 10% to 90%), temperature overshoot (the magnitude by which the temperature exceeds the steady-state value), and temperature stabilization time (the time when the temperature reaches the steady-state value and remains within a certain range). Save the calculated transient thermal response metrics to a file.

[0184] Based on the updated dynamic load matrix, generate multiple load matrix variants. Each variant represents a different load pattern, for example, changing the read / write ratio, adjusting the access address distribution, etc. Use a Python script to control the COMSOL Multiphysics software, apply each load matrix variant to the calibrated chip thermal model for transient thermal simulation. Record the temperature changes of the key regions of the chip under each load pattern. Compare and analyze the temperature changes under different load patterns, such as comparing the maximum temperature, average temperature, and temperature fluctuation range of the key regions under different load patterns. Save the temperature change data and the comparative analysis results under different load patterns as files to form the load pattern impact data.

[0185] Use a Python script to integrate the transient thermal response metrics, load pattern impact data, and dynamic temperature distribution data. Associate the transient thermal response metrics, key region temperature curves, and dynamic temperature distribution data under different load patterns to form a comprehensive dataset called the dynamic thermal characteristics data. Save the dynamic thermal characteristics data as a file, such as in HDF5 format, for subsequent analysis and processing.

[0186] Preferably, step S4352 is specifically as follows:

[0187] Define the key regions for the chip structure and function data to obtain the key region coordinate information;

[0188] Perform temperature data mapping on the dynamic temperature distribution data and the key region coordinate information to obtain the regional temperature mapping data;

[0189] Perform time-series temperature extraction on the regional temperature mapping data to obtain the key region time-series temperature data;

[0190] Generate a temperature curve for the timing temperature data of the key area to obtain the key area temperature curve.

[0191] In the embodiment of the present invention, Python scripts and an image processing library (such as OpenCV) are used to process the chip structure function data. Read the chip layout information, which includes the positions and sizes of each functional module of the chip. According to the division of the functional modules of the chip and the requirements of thermal performance analysis, define key areas, such as a memory cell array, a control circuit, an I / O interface, etc. Use the image processing function of OpenCV to extract the coordinate range of each key area on the chip layout, such as the upper left and lower right coordinates of a rectangular box. Save the name and coordinate range of each key area in dictionary format to form the key area coordinate information.

[0192] Use Python scripts to map the dynamic temperature distribution data with the key area coordinate information. Read the heat map file for each time point, which contains the temperature distribution data on the chip surface. According to the key area coordinate information, extract the temperature data corresponding to each key area. Save the temperature data of each time point and each key area in matrix form to form the area temperature mapping data.

[0193] Use Python scripts to process the area temperature mapping data. For each key area, extract the temperature data of this area at all time points. Arrange the temperature data of each key area in chronological order to form a time series, which constitutes the key area timing temperature data. Save the timing temperature data of each key area as a separate CSV file.

[0194] Use the Matplotlib library of Python to generate a temperature curve according to the key area timing temperature data. Read the CSV file of the timing temperature data for each key area. Use time as the abscissa and temperature as the ordinate to plot the curve of the temperature change of each key area over time. Save the generated temperature curve as an image file, such as PNG or SVG format, and associate it with the corresponding key area name to form the key area temperature curve.

[0195] Preferably, step S4354 is specifically:

[0196] Define load mode parameters according to the updated dynamic load matrix to obtain a set of load mode parameters;

[0197] Generate dynamic load matrix variants according to the updated dynamic load matrix and the set of load mode parameters to obtain a set of load matrix variants;

[0198] Perform multi-mode thermal simulation according to the set of load matrix variants and the calibrated chip thermal model to obtain a multi-mode temperature data set;

[0199] Conduct a comparative analysis of thermal response indicators for multi-mode temperature datasets to obtain thermal response comparison data;

[0200] Summarize the influence rules of load modes based on the thermal response comparison data to obtain load mode influence data.

[0201] In the embodiments of the present invention, analyze and update the dynamic load matrix to determine the key load parameters affecting the chip thermal characteristics, such as read / write frequency, read / write ratio, data block size, access address distribution, etc. For each load parameter, define its value range and change step. For example, define the value range of the read / write frequency as 100 MHz to 500 MHz, with a step of 100 MHz; define the value range of the read / write ratio as 1:9 to 9:1, with a step of 2. Save all load parameters and their value range and step information in dictionary format to form a load mode parameter set.

[0202] Use a Python script to generate multiple variants of the dynamic load matrix based on the updated dynamic load matrix and the load mode parameter set. Traverse each load parameter in the load mode parameter set, and generate a series of parameter values within its defined value range according to the specified step. For each parameter value, copy a copy of the updated dynamic load matrix and modify the parameter in the copied matrix. For example, modify the read / write frequency to 200 MHz, 300 MHz, 400 MHz, and 500 MHz to generate four different variants of the dynamic load matrix. Save all the generated variants of the dynamic load matrix as a list to form a load matrix variant set.

[0203] Use a Python script to control the COMSOL Multiphysics software to perform thermal simulations on each variant of the dynamic load matrix in the load matrix variant set. Use the load characteristic data in each variant of the dynamic load matrix as input parameters and apply them to the calibrated chip thermal model. Conduct transient thermal analysis in COMSOL and record the chip temperature distribution data at each time point. Save the temperature distribution data corresponding to each variant of the dynamic load matrix as a separate file, such as in HDF5 format. All the files form a multi-mode temperature dataset.

[0204] Analyze the multi-mode temperature dataset using Python scripts and data analysis libraries (such as Pandas). Extract the temperature data of the key areas of the chip under each load mode, and calculate the corresponding thermal response metrics, such as the maximum temperature, average temperature, temperature rise time, temperature overshoot, and temperature stabilization time. Compare and analyze the thermal response metrics under different load modes, such as comparing the maximum temperature and temperature rise time at different read / write frequencies, and comparing the average temperature and temperature stabilization time at different read / write ratios, etc. Save the comparison results of the thermal response metrics under different load modes in the form of tables or charts to form the thermal response comparison data.

[0205] Analyze the thermal response comparison data and summarize the influence rules of different load modes on the thermal characteristics of the chip. For example, analyze the influence rule of the read / write frequency on the maximum temperature, the influence rule of the read / write ratio on the average temperature, the influence rule of the data block size on the temperature rise time, etc. Express the summarized influence rules in the form of text descriptions, formulas, or charts, and explain them in combination with the actual chip working scenario. Save this information as a document to form the load mode influence data.

[0206] Preferably, step S5 includes the following steps:

[0207] Step S51: Standardize the feature data of the updated dynamic load matrix, electrical characteristic curve, storage behavior map, and thermal energy consumption characteristic matrix to obtain a standardized feature dataset;

[0208] Step S52: Determine the weights of the standardized feature dataset to obtain the feature weights;

[0209] Step S53: Construct a quality evaluation model based on the standardized feature dataset and the feature weights to obtain the quality evaluation model;

[0210] Step S54: Calculate the comprehensive quality score of the standardized feature dataset using the quality evaluation model to obtain the comprehensive quality score;

[0211] Step S55: Classify and screen the chips according to the comprehensive quality score to obtain the chip classification result.

[0212] In the embodiments of the present invention, Python scripts and the Scikit-learn library are used to standardize the feature data of the updated dynamic load matrix, electrical characteristic curve data, storage behavior atlas data, and thermal energy consumption feature matrix. Each data file is read, and the data is converted into the NumPy array format. The Min-Max normalization method is adopted to scale the data range of each feature to between 0 and 1. The formula is: X_scaled = (X - X_min) / (X_max - X_min), where X is the original feature data, X_scaled is the standardized feature data, and X_min and X_max are the minimum and maximum values of this feature respectively. The standardized data is saved as a new CSV file to form a standardized feature dataset.

[0213] The Analytic Hierarchy Process (AHP) is used to determine the weights of each feature in the standardized feature dataset. An AHP hierarchical structure model is constructed, with "storage chip quality" as the target layer, performance, reliability, power consumption, and thermal stability as the criterion layer, and each feature in the standardized feature dataset as the index layer. Domain experts are invited to make pairwise comparisons between the criterion layer and the index layer, and a judgment matrix is constructed based on the comparison results. Python scripts and the AHP library are used to calculate the eigenvector and the maximum eigenvalue of the judgment matrix, and a consistency test is performed. According to the calculation results, the weight of each feature is determined, and the weight value is saved to a file.

[0214] Using Python scripts and the Scikit-learn library, a quality assessment model based on Support Vector Machine (SVM) is constructed according to the standardized feature dataset and feature weights. The standardized feature dataset is used as the training data, and the pre-set chip quality levels (such as excellent, qualified, unqualified) are used as the target variables. The feature weights are used to weight the training data, so that the features with higher weights have a greater impact on the model training. The grid search method is used to optimize the hyperparameters of the SVM model, such as the kernel function type, regularization parameter, etc. After training, the trained SVM model is saved as a file to form a quality assessment model.

[0215] Using Python scripts, the quality assessment model is loaded. The standardized feature dataset is read. The loaded quality assessment model is used to predict each sample in the standardized feature dataset to obtain the comprehensive quality score of each sample. The comprehensive quality scores are saved as a CSV file.

[0216] Use a Python script to read the comprehensive quality score. Pre-define the chip quality levels and their corresponding score ranges, for example: excellent (0.9 - 1.0), qualified (0.7 - 0.9), unqualified (0 - 0.7). According to the pre-defined score ranges, classify each chip into the corresponding quality level. Save the chip ID and the corresponding quality level as a CSV file to form the chip grading result.

[0217] Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Thus, all changes falling within the meaning and scope of the equivalent elements of the application document are intended to be encompassed within the present invention.

[0218] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

Claims

1. A quality assessment method for an embedded storage chip, characterized in that: The following steps are involved: Step S1: collecting application scenario data according to a pre-selected target application scenario to obtain an application scenario data set; extracting load features from the application scenario data set to obtain a load feature vector; Using a machine learning algorithm, a load prediction model is trained according to the load feature vector to obtain a load prediction model; a dynamic load matrix is ​​generated according to the load prediction model to obtain a dynamic load matrix; Step S2: applying a dynamic load to the memory chip to be tested according to the dynamic load matrix to obtain real-time load status data; Collect electrical performance data of the memory chip to be tested to obtain original electrical performance data; extract electrical performance characteristics of the original electrical performance data to obtain electrical performance characteristic data; Performing feature correlation processing on the electrical performance feature data and the real-time load status data to obtain an electrical performance feature vector; according to The electrical performance characteristic vector is used to identify the potential performance bottleneck of the chip to obtain the performance bottleneck identification result; the load prediction model is adaptively adjusted according to the performance bottleneck identification result to obtain the adjusted load parameters; the dynamic load matrix is ​​dynamically updated according to the load prediction model and the adjusted load parameters to obtain the updated dynamic load matrix; the load state is generated in real time according to the updated dynamic load matrix to obtain the real-time updated load state data; the electrical characteristic curve is generated according to the real-time updated load state data and the electrical performance characteristic vector to obtain the electrical characteristic curve; Step S3: Generate simulation data according to the updated dynamic load matrix to obtain a simulation data set; simulate the storage behavior of the memory chip to be tested using the simulation data set, and optimize the storage behavior simulation according to the electrical characteristic curve to obtain simulation behavior data; finely mark the read and write events of the simulation behavior data to obtain precise marked behavior data; Perform delay distribution statistics on the precise standard behavior data to obtain a delay statistics histogram; Perform error pattern recognition on the precise labeled behavior data to obtain the error pattern feature vector; Perform throughput fluctuation analysis on precise standard behavior data to obtain a throughput fluctuation curve; perform time locality analysis on precise standard behavior data to obtain time locality data; perform spatial locality analysis on precise standard behavior data to obtain spatial locality data; generate locality feature parameters based on time locality data and spatial locality data to obtain locality feature parameters; perform data flow feature synthesis on delay statistical histogram, error pattern feature vector, throughput fluctuation curve and locality feature parameters to obtain data flow features; The storage behavior map is constructed according to the data flow characteristics and the updated dynamic load matrix to obtain the storage behavior map; Step S4 includes the following steps: Step S41: performing real-time monitoring of the memory chip under dynamic load according to the updated dynamic load matrix to obtain real-time temperature and power consumption data; Step S42: extracting heat power consumption characteristics from the real-time temperature power consumption data to obtain a heat power consumption characteristic vector; Step S43: performing thermal stability analysis according to the thermal power consumption characteristic vector and the storage behavior map to obtain a thermal stability index; Step S44: performing energy efficiency analysis according to the thermal power consumption characteristic vector and the storage behavior map to obtain an energy efficiency index; Step S45: constructing a thermal energy consumption characteristic matrix according to the thermal stability index, the energy efficiency ratio index and the updated dynamic load matrix to obtain a thermal energy consumption characteristic matrix; Step S5: Standardize the feature data of the updated dynamic load matrix, electrical characteristic curve, storage behavior map and thermal energy consumption feature matrix to obtain a standardized feature data set; determine the weights of the standardized feature data set to obtain feature weights; construct a quality assessment model based on the standardized feature data set and the feature weights to obtain a quality assessment model; use the quality assessment model to calculate the comprehensive quality score of the standardized feature data set to obtain a comprehensive quality score; perform chip grading and screening based on the comprehensive quality score to obtain a chip grading result.

2. The quality assessment method of an embedded storage chip according to claim 1, characterized in that: Step S43 includes the following steps: Step S431: dividing the temperature interval according to the thermal power consumption characteristic vector to obtain temperature interval data; Step S432: extracting interval performance data from the storage behavior map according to the temperature interval data to obtain an interval performance data set; Step S433: using a finite element analysis method to construct a thermal model according to the memory chip to be tested, to obtain a chip thermal model; Step S434: verifying and calibrating the chip thermal model according to the thermal power consumption feature vector to obtain a calibrated chip thermal model; Step S435: performing dynamic thermal characteristic analysis according to the interval performance data set and the calibrated chip thermal model to obtain dynamic thermal characteristic data; Step S436: Calculate the thermal stability index according to the dynamic thermal characteristic data to obtain the thermal stability index.

3. The quality assessment method of an embedded storage chip according to claim 2, characterized in that: Step S435 includes the following steps: Step S4351: Perform dynamic load temperature simulation according to the interval performance data set and the calibrated chip thermal model to obtain dynamic temperature distribution data; Step S4352: Acquire chip structure function data; extract key area temperature according to dynamic temperature distribution data and chip structure data to obtain key area temperature curve; Step S4353: Calculate the transient thermal response index according to the temperature curve of the key area to obtain the transient thermal response index; Step S4354: performing load mode impact analysis according to the updated dynamic load matrix and the calibrated chip thermal model to obtain load mode impact data; Step S4355: integrating dynamic thermal characteristic data of the transient thermal response index according to the load mode impact data to obtain dynamic thermal characteristic data.

4. The method for evaluating the quality of an embedded storage chip according to claim 3, characterized in that: Step S4352 is specifically as follows: Define key areas of chip structure and function data to obtain key area coordinate information; Perform temperature data mapping on the dynamic temperature distribution data and key area coordinate information to obtain regional temperature mapping data; Perform time series temperature extraction on the regional temperature mapping data to obtain the key regional time series temperature data; The temperature curve of the key area is generated by the time series temperature data of the key area to obtain the temperature curve of the key area.

5. The method for evaluating the quality of an embedded storage chip according to claim 3, characterized in that: Step S4354 is specifically as follows: Defining load mode parameters according to the updated dynamic load matrix to obtain a load mode parameter set; Generate dynamic load matrix variants according to the updated dynamic load matrix and the load pattern parameter set to obtain a load matrix variant set; Perform multi-mode thermal simulation according to the load matrix variation set and the calibrated chip thermal model to obtain a multi-mode temperature data set; Conduct comparative analysis of thermal response indicators on multi-mode temperature data sets to obtain thermal response comparison data; The load mode influence rules are summarized based on the thermal response comparison data to obtain the load mode influence data.

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