Method for reducing leakage current of small memory chip

Abstract

The application provides a method for reducing leakage of a small storage chip, and belongs to the technical field of semiconductor chips. The method comprises the following steps: obtaining current leakage data, original leakage data and function test data of a chip to be detected, and establishing a leakage analysis model; determining whether a leakage point of the chip to be detected is a polysilicon spacing according to the original leakage data, the current leakage data, the pre-constructed leakage analysis model and the function test data; if yes, performing physical sectioning on the chip to be detected to obtain a section measurement result, and determining whether a current growth interval of a metal silicide in the chip to be detected exceeds a calibration growth interval; if yes, performing mask revision optimization on the chip to be detected, performing tape-out verification on the mask revision optimization result, and determining a target mask revision result from the tape-out verification result. The application can prevent the metal silicide between two polysilicon from side-penetrating, thereby avoiding the leakage of storage bits caused by the too-close polysilicon spacing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chips, in particular to a method for reducing leakage of small storage chips. BACKGROUND

[0002] With the advancement of semiconductor manufacturing process, chip miniaturization has become the mainstream direction of chip manufacturing. Storage chips, also known as memory chips, are integrated circuit chips that store data. Storage chips are an important part of computer systems and are mainly used to temporarily or permanently store data and instructions. Storage chips are used to store and retrieve data in computer systems to achieve fast access and data processing functions of computer systems and provide support for normal operation of computer systems. Among them, small storage chips can make each wafer cut more chips, thereby reducing the production cost of small storage chips; small storage chips can also shorten the current path and reduce the resistance to reduce the power consumption and heat generation of small storage chips. However, the reduction of the area of the storage chip may cause the storage chip to fail due to storage bit leakage, thereby causing the small storage chip to fail. Therefore, it is urgent to solve the problem of storage bit leakage caused by the reduction of the area of the storage chip to improve the production yield of the small storage chip.

[0003] In related technologies, a layer of metal silicide will be formed between the two polysilicon of the storage chip to realize the alignment of the source, drain and gate of the storage chip. However, when producing small storage chips based on related technologies, the distance between the two polysilicon is too small, causing the metal silicide grown between the two polysilicon to be side-penetrated, thereby causing the storage chip to leak storage bits. SUMMARY

[0004] The purpose of the present application is to provide a method for reducing leakage of small storage chips, which can prevent metal silicide between two polysilicon from side-penetrating, thereby avoiding storage bit leakage caused by too close distance between polysilicon.

[0005] Embodiments of the present application are implemented as follows:

[0006] In a first aspect, the present application provides a method for reducing leakage of small storage chips, the method comprising:

[0007] Obtaining current leakage data of a to-be-detected chip and original leakage data of an original chip corresponding to the to-be-detected chip, and establishing a leakage analysis model, wherein the to-be-detected chip is a chip obtained by area reduction on the original chip;

[0008] performing function test on the chip to be detected to obtain function test data of the chip to be detected, and determining whether the leakage point of the chip to be detected is a polysilicon spacing according to the original leakage data, the current leakage data, the pre-constructed leakage analysis model, and the function test data;

[0009] If yes, performing physical dissection on the chip to be detected to obtain cross-section measurement results of the chip to be detected, and determining whether the current growth interval of the metal silicide in the chip to be detected exceeds the calibrated growth interval according to the cross-section measurement results;

[0010] If yes, performing mask revision optimization on the chip to be detected, performing tape-out verification on the mask revision optimization results, determining target mask revision results from the tape-out verification results, and performing test verification on the target mask revision results, the target mask revision results including mask revision parameter information.

[0011] As a possible implementation manner, the mask revision optimization on the chip to be detected includes:

[0012] performing mask revision optimization on the chip to be detected based on a preset mask revision step to obtain the chip to be detected after mask revision optimization.

[0013] As a possible implementation manner, the tape-out verification on the mask revision optimization results and the determination of the target mask revision results from the tape-out verification results include:

[0014] performing mask revision optimization on the chip to be detected multiple times based on a preset mask revision step, and obtaining leakage data and function test data of the chip to be verified after each mask revision optimization;

[0015] determining verification results corresponding to each chip to be verified according to the leakage data and the function test data of each chip to be verified;

[0016] determining the target mask revision results according to the verification results corresponding to each chip to be verified.

[0017] As a possible implementation manner, the determination of the target mask revision results according to the verification results corresponding to each chip to be verified includes:

[0018] if the leakage current in the leakage data of a target chip to be verified among the chips to be verified reaches a preset threshold value, and each test item in the function test data of the target chip to be verified is qualified, then the target chip to be verified is determined as the target mask revision results.

[0019] As a possible implementation manner, the function test on the chip to be detected to obtain the function test data of the chip to be detected includes:

[0020] Consistency detection is performed on the to-be-detected chip to obtain functional test data of the to-be-detected chip.

[0021] As a possible implementation manner, according to the original leakage data, the current leakage data, the pre-constructed leakage analysis model and the functional test data, it is determined whether the leakage point of the detection chip is a polysilicon pitch, comprising:

[0022] According to the comparison result of the original leakage data and the current leakage data, the leakage direction of the to-be-detected chip is determined.

[0023] According to the current leakage data and the pre-constructed leakage analysis model, the leakage source of the to-be-detected chip is determined.

[0024] According to the functional test data, the leakage point of the to-be-detected chip is determined.

[0025] It is determined whether the leakage point of the to-be-detected chip is a polysilicon pitch.

[0026] As a possible implementation manner, according to the comparison result of the original leakage data and the current leakage data, the leakage direction of the to-be-detected chip is determined, comprising:

[0027] The gate-to-drain leakage data in the original leakage data is compared with the gate-to-drain leakage data in the current leakage data to obtain a first comparison result.

[0028] The channel leakage data in the original leakage data is compared with the channel leakage data in the current leakage data to obtain a second comparison result.

[0029] The junction leakage data in the original leakage data is compared with the junction leakage data in the current leakage data to obtain a third comparison result.

[0030] According to the maximum value in the first comparison result, the second comparison result and the third comparison result, the leakage direction of the to-be-detected chip is determined.

[0031] As a possible implementation manner, according to the current leakage data and the pre-constructed leakage analysis model, the leakage source of the to-be-detected chip is determined, comprising:

[0032] The current leakage data is input into the pre-constructed leakage analysis model to obtain the leakage source of the to-be-detected chip, and the pre-constructed leakage analysis model comprises: a gate-to-drain leakage analysis item, a channel leakage analysis item and a junction leakage analysis item.

[0033] As a possible implementation manner, according to the functional test data, the leakage point of the to-be-detected chip is determined, comprising:

[0034] According to the qualified rate corresponding to each test item in the functional test data, a leakage point of the chip to be detected is determined, and the leakage point is marked on a wafer on which the chip to be detected is located.

[0035] As a possible implementation, a cross-sectional measurement result of the chip to be detected is acquired, and whether the current growth interval of the metal silicide in the chip to be detected exceeds the marked growth interval is determined according to the cross-sectional measurement result and a preset growth interval, including:

[0036] According to the cross-sectional measurement result of the chip to be detected, a polysilicon spacing and the current growth interval of the metal silicide in the chip to be detected are determined.

[0037] According to the comparison result of the current growth interval and the marked growth interval, whether the current growth interval of the metal silicide in the chip to be detected exceeds the marked growth interval is determined.

[0038] The beneficial effects of the embodiments of the present application include:

[0039] The method for reducing leakage of a small storage chip provided by the embodiments of the present application acquires original leakage data of an original chip before area reduction of a chip to be detected on a wafer and current leakage data of the chip to be detected after the area reduction through a data test structure deployed on the wafer, and preconstructs a leakage analysis model; functional tests are performed on each chip to be detected after the area reduction on the wafer to obtain functional test data of each chip to be detected; whether the leakage point of the chip to be detected is a polysilicon spacing is determined according to the original leakage data and the current leakage data of the chip to be detected before and after the area reduction, the preconstructed leakage analysis model, and the functional test data; when it is determined that the leakage point of the chip to be detected is the polysilicon spacing, a physical cross-sectional diagram of the chip to be detected is further acquired, whether the chip to be detected has a too-close polysilicon spacing and whether the current growth interval of the metal silicide of a too-long polysilicon spacing exceeds a marked growth interval are determined according to a cross-sectional measurement result of the chip to be detected; when the chip to be detected has both the too-close polysilicon spacing and the current growth interval of the metal silicide of the too-long polysilicon spacing exceeding the marked growth interval, a mask revision optimization is performed on the chip to be detected, a storage chip obtained through each mask revision optimization is verified through a tape-out, and a target mask revision result is determined from a plurality of tape-out verification results; the target mask revision result is further tested and verified to ensure the reliability of the target mask revision result. The mask revision optimization limits the growth interval of the metal silicide in the polysilicon spacing through a mask and radioactive light. In this way, the effect of preventing the metal silicide between two polysilicon from side-penetrating and avoiding the leakage of storage bits caused by the too-close polysilicon spacing can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those of ordinary skill in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0041] Figure 1 The flow chart of the first method for reducing leakage of small storage chip provided by the embodiments of the present application;

[0042] Figure 2 The flow chart of the second method for reducing leakage of small storage chip provided by the embodiments of the present application;

[0043] Figure 3 The structural schematic diagram of the storage chip before mask optimization provided by the embodiments of the present application;

[0044] Figure 4 The structural schematic diagram of the storage chip after mask optimization provided by the embodiments of the present application;

[0045] Figure 5 The schematic diagram of the mask optimization result provided by the embodiments of the present application;

[0046] Figure 6 The comparative result schematic diagram of the leakage data of the storage chip before and after mask optimization provided by the embodiments of the present application;

[0047] Figure 7 The distribution diagram of the consistency test result of the storage chip provided by the embodiments of the present application;

[0048] Figure 8 The distribution diagram of the consistency test result of another storage chip provided by the embodiments of the present application;

[0049] Figure 9 The flow chart of the third method for reducing leakage of small storage chip provided by the embodiments of the present application;

[0050] Figure 10 The comparative result schematic diagram of the leakage data of the storage chip before and after area reduction provided by the embodiments of the present application;

[0051] Figure 11 The structural schematic diagram of the leakage analysis model provided by the embodiments of the present application;

[0052] Figure 12 The flow chart of the fourth method for reducing leakage of small storage chip provided by the embodiments of the present application;

[0053] Figure 13A flow chart of a fifth method for reducing leakage of a small storage chip according to an embodiment of the present application is provided.

[0054] Figure 14 A physical profile of a storage chip according to an embodiment of the present application is provided.

[0055] Figure 15 A physical profile of a storage chip according to another embodiment of the present application is provided.

[0056] Figure 16 A flow chart of a manufacturing process for reducing leakage of a small storage chip according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0057] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0058] Therefore, the detailed description of the embodiments of the present application provided below in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0059] At present, a small storage chip can enable more storage chips to be cut from each wafer, thereby reducing the production cost of the small storage chip. The small storage chip can shorten the current path of an internal integrated circuit and reduce the resistance, so as to reduce the power consumption and heat generation of the small storage chip. Among them, a layer of metal silicide will be grown between two polysilicon of the storage chip to realize the alignment of the source, drain and gate of the storage chip and enhance the conductivity of the source, drain and gate. However, this scheme often has a too small distance between the two polysilicon, which causes the metal silicide grown between the two polysilicon to be side-penetrated, thereby causing the storage chip to have too strong conductivity and causing the storage chip to have storage bit leakage.

[0060] To this end, the embodiment of the present application provides a method for reducing leakage of a small storage chip, original leakage data and current leakage data of each to-be-detected chip deployed on a wafer are acquired through a data test structure arranged on the wafer, and a leakage analysis model is constructed in advance; a function test is performed on each to-be-detected chip to obtain function test data of each to-be-detected chip; whether a leakage point of the to-be-detected chip is a polysilicon spacing is determined according to the original leakage data, the current leakage data, the function test data of each to-be-detected chip and the leakage analysis model constructed in advance; if yes, a physical sectioning is performed on the to-be-detected chip, and whether a metal silicide between the two polysilicon of the storage chip is side-penetrated is determined according to a sectioning measurement result of the to-be-detected chip; if yes, a mask revision optimization is performed on the to-be-detected chip, a tape-out verification is performed on a mask revision result, an optimal target mask revision result is determined from a plurality of tape-out verification results, and the target mask revision result is further tested to ensure that the performance of the target mask revision result is stable and reliable. In this way, the metal silicide between the two polysilicon can be prevented from being side-penetrated, and the effect of storage bit leakage caused by too close polysilicon spacing can be avoided.

[0061] The method for reducing leakage of a small storage chip provided by the embodiment of the present application is explained and described in detail below in combination with the accompanying drawings.

[0062] Figure 1 A flowchart of a method for reducing leakage of a small storage chip provided by the present application is shown in FIG. 1. Figure 1 The embodiment of the present application provides a method for reducing leakage of a small storage chip, which comprises the following steps.

[0063] In S101, current leakage data of a to-be-detected chip and original leakage data of an original chip corresponding to the to-be-detected chip are acquired, and a leakage analysis model is established, wherein the to-be-detected chip is a chip obtained after area reduction of the original chip.

[0064] Optionally, a plurality of storage chips can be cut from each wafer, when the area of the storage chip is reduced, more storage chips can be cut from each wafer on the basis of the original wafer, leakage data of each to-be-detected chip on the wafer is collected through a data test structure arranged on the wafer. The number of the data test structures arranged on the wafer is much smaller than the number of the storage chips cut from the wafer, that is, one data test structure can collect leakage data of a plurality of storage chips, and the number of the data test structures is not limited in the present application.

[0065] Optionally, the original chip is used to indicate a memory chip obtained by initial cutting of a wafer, and the to-be-detected chip is used to indicate a memory chip obtained by reducing the area of the original chip. All original chips on the wafer after reducing the area are used as the to-be-detected chip. The original leakage data of the original chip and the current leakage data of the to-be-detected chip are obtained through the data test structure deployed on the wafer. The original leakage data is used to indicate the leakage data of the memory chip obtained by initial cutting of the wafer under the action of each detection voltage. The original leakage data includes leakage data such as leakage current and leakage resistance of the original chip. The current leakage data is used to indicate the leakage data of the original chip after reducing the area under the action of each detection voltage. It should be noted that the leakage data of the memory chip before and after reducing the area is detected by the present application through multiple detection voltages. The leakage voltage interval of the memory chip can be investigated to ensure the reliability of the small memory chip in mass production.

[0066] Optionally, based on the original leakage data of a large number of original memory chips obtained by initial cutting and the leakage data of a large number of memory chips obtained by reducing the area, a leakage analysis model is constructed. The leakage analysis model includes multiple leakage analysis items. The current leakage data and the original leakage data of the to-be-detected chip are input into the leakage analysis model, and the leakage direction and the leakage source of the to-be-detected chip can be obtained.

[0067] S102, function test is performed on the to-be-detected chip to obtain function test data of the to-be-detected chip, and whether the leakage point of the to-be-detected chip is a polysilicon spacing is determined according to the original leakage data, the current leakage data, the pre-constructed leakage analysis model, and the function test data.

[0068] Optionally, the function test can be a CP test. The CP test is performed on each to-be-detected chip, and the position of the to-be-detected chip is calibrated on the wafer according to the function test data of the to-be-detected chip. The function test of the to-be-detected chip includes voltage test, current test, timing test, storage function test, etc. When the test result corresponding to the function test data of the to-be-detected chip is qualified, the chip is calibrated as qualified on the wafer. When the test result corresponding to the function test data of the to-be-detected chip is failed or unqualified, the chip is calibrated as unqualified on the wafer. It should be noted that the qualified memory chip and the unqualified memory chip can be calibrated by different colors, such as marking the unqualified memory chip with red and the qualified memory chip with blue, etc. The present application does not make specific limitation on this.

[0069] Optionally, according to the original leakage data and the current leakage data of each to-be-detected chip before and after the area reduction, the pre-constructed leakage analysis model, and the functional test data, it is determined whether the leakage point of each to-be-detected chip and the leakage source are polycrystalline silicon spacing. The polycrystalline silicon spacing is used to indicate the spacing between two polycrystalline silicon in the storage chip, and the two polycrystalline silicon in the storage chip are used to indicate two control tubes of the storage chip. When the polycrystalline silicon spacing is too close, the metal silicide between the two polycrystalline silicon in the storage chip may be side-penetrated, thereby causing the conductivity of the storage chip to suddenly increase, and the risk of storage bit leakage of the storage chip to occur.

[0070] In addition, based on the functional test data of each to-be-detected chip on the wafer, the production yield of the storage chip after the area reduction obtained by cutting the wafer is determined, and according to the ratio of the number of the to-be-detected chips that pass the calibration to the number of the to-be-detected chips that fail the calibration on the wafer, the failure rate of the wafer is determined. When the failure rate of the wafer is large and the calibration points of the to-be-detected chips that fail the calibration on the wafer are in pieces, the to-be-detected chips on the wafer need to be optimized.

[0071] S103, if yes, the to-be-detected chip is physically dissected to obtain a cross-sectional measurement result of the to-be-detected chip, and according to the cross-sectional measurement result, it is determined whether the current growth interval of the metal silicide in the to-be-detected chip exceeds the calibration growth interval.

[0072] Optionally, the to-be-detected chip is physically dissected to obtain a cross-sectional schematic diagram of each to-be-detected chip, the growth interval of the metal silicide in the cross-sectional schematic diagram is measured, that is, the length, width and other information of the metal silicide are measured, and the spacing between the two transistors of each to-be-detected chip is measured to obtain a cross-sectional measurement result of the to-be-detected chip. The cross-sectional measurement result of the to-be-detected chip is used to indicate the spacing measurement result between the two transistors of the to-be-detected chip and the growth interval of the elongated metal silicide in the to-be-detected chip.

[0073] Optionally, the position of the metal silicide growing between the two transistors in the to-be-detected chip can be determined by PFA positioning, and the elongated metal silicide in the polycrystalline silicon spacing is measured by a measurement tool to obtain the current growth interval of the metal silicide.

[0074] Optionally, the current growth interval is used to indicate the actual growth range of the metal silicide between the two transistors of the to-be-detected chip at the current time, that is, the length, width and other information of the metal silicide between the two transistors of the to-be-detected chip at the current time; the calibration growth interval is used to indicate the safe growth interval of the metal silicide between the two transistors of the to-be-detected chip that will not cause channel leakage of the to-be-detected chip, that is, if the actual growth interval of the elongated metal silicide between the two transistors of the to-be-detected chip at the current time is within the calibration growth interval, it is determined that the metal silicide is not side-penetrated.

[0075] Optionally, according to the profile measurement result of the chip to be detected and the comparison result of the calibration growth interval, it is determined whether the actual growth interval of the metal silicide between the two transistors of the chip to be detected at the current time exceeds the limit of the calibration growth interval.

[0076] S104, if yes, the chip to be detected is optimized by mask revision, the mask revision optimization result is verified by wafer production, the target mask revision result is determined from the wafer production verification result, and the target mask revision result is tested and verified. The target mask revision result includes mask revision parameter information.

[0077] Optionally, when the polysilicon distance in the chip to be detected is too close, the metal silicide between the two transistors occurs side penetration, and then causes the chip to be detected to leak, the chip to be detected is optimized by mask revision optimization process. The storage chip produced after each mask revision optimization is used as a chip to be verified. The chip to be verified is verified by wafer production to obtain the target mask revision result. The target mask revision result is used to indicate that there is no leakage data in the chip to be detected after mask revision optimization, and the functional test data of the chip to be detected after mask revision optimization is qualified.

[0078] Optionally, the target mask revision result is tested and verified to verify whether there is a leakage current in the chip to be verified after target mask revision optimization under the action of each detection voltage, and the function of the chip to be verified after target mask revision optimization is tested. When there is no leakage data in the chip to be detected after target mask revision optimization, and each functional test result is qualified, small storage chips can be quantitatively produced according to the mask revision parameter information in the target mask revision result. The mask revision parameter information is used to indicate the mask interval and light intensity corresponding to the chip to be detected in the target mask revision result and other information.

[0079] In the embodiment of the present application, the original leakage data of the original chip before the reduced area of the chip to be detected on the wafer and the current leakage data of the chip to be detected after the reduced area are obtained through the data test structure deployed on the wafer, and a leakage analysis model is constructed in advance; the function test data of each chip to be detected is obtained by performing function test on each chip to be detected after the reduced area; whether the leakage point of the chip to be detected is a polysilicon spacing is determined according to the original leakage data and the current leakage data of the chip to be detected before and after the reduced area, the leakage analysis model constructed in advance, and the function test data; when it is determined that the leakage point of the chip to be detected is a polysilicon spacing, the physical profile of the chip to be detected needs to be further obtained, and whether the polysilicon spacing is too close and whether the current growth interval of the metal silicide in the polysilicon spacing is out of the calibrated growth interval are determined according to the profile measurement result of the chip to be detected; when the chip to be detected has both the polysilicon spacing too close and the current growth interval of the metal silicide in the polysilicon spacing out of the calibrated growth interval, the photomask revision optimization is performed on the chip to be detected, the storage chip obtained after each photomask revision optimization is verified by wafer production, and the target photomask revision result is determined from the wafer production verification result; and the test verification is further performed on the target photomask revision result to obtain the photomask revision result with the best effect. The photomask revision optimization is to limit the growth interval of the metal silicide in the polysilicon spacing through the photomask and radioactive light. In this way, the metal silicide side penetration between two polysilicon can be prevented, and the effect of preventing the storage bit leakage caused by the polysilicon spacing too close can be achieved.

[0080] In a possible implementation manner, the operation of performing photomask revision optimization on the chip to be detected in step S104 can be specifically as follows:

[0081] The photomask revision optimization is performed on the chip to be detected based on the preset photomask revision step to obtain the chip to be detected after the photomask revision optimization.

[0082] Optionally, the preset photomask revision step is used to indicate the parameters of the photomask revision of the chip to be detected once, such as the light intensity and the light duration when the photomask revision optimization is performed on the chip to be detected once, and the like. The photomask revision optimization is performed on the chip to be detected based on the preset photomask revision step to limit the metal silicide from growing in the range of the photomask, thereby avoiding the metal silicide side penetration.

[0083] Optionally, the photomask revision optimization is performed on the chip to be detected based on the preset photomask revision step to obtain the chip to be detected after the photomask revision optimization.

[0084] In an optional implementation manner, referring to Figure 2 The operation of verifying the photomask revision optimization result to obtain the target photomask revision result in step S104 can be specifically as follows:

[0085] S201, perform multiple mask revision optimization on the to-be-tested chip based on a preset mask revision step, and obtain leakage data and functional test data of the to-be-verified chip after each mask revision optimization.

[0086] Optionally, multiple mask revisions are performed on the to-be-tested chip based on a preset mask revision step, and a corresponding storage chip is obtained after each mask revision optimization, which is also a to-be-verified chip. For example, the current growth interval of the metal silicide between the two transistors of the to-be-verified chip A after area reduction is 1.2 cm. After the first mask revision optimization, the growth interval of the metal silicide between the two transistors of the to-be-tested chip is 1.1 cm, that is, a to-be-verified chip a with a metal silicide growth interval of 1.1 cm is obtained. After the second mask revision optimization, the growth interval of the metal silicide between the two transistors of the storage chip is 1.0 cm, that is, a to-be-verified chip b with a metal silicide growth interval of 1.0 cm is obtained.

[0087] Optionally, the leakage data of the to-be-verified chip obtained after each mask optimization is obtained through the data test structure deployed on the wafer, and the to-be-tested chip obtained after each mask revision optimization is subjected to consistency test to obtain the functional test data of the to-be-verified chip after mask revision optimization.

[0088] S202, determine the verification result corresponding to each to-be-verified chip according to the leakage data and the functional test data of each to-be-verified chip.

[0089] Optionally, the leakage data of each to-be-verified chip is input into a pre-constructed leakage analysis model for leakage analysis, and the performance of each to-be-verified chip is determined according to the functional test data of each to-be-verified chip. According to the leakage data analysis result and the functional test data analysis result of each to-be-verified chip, the verification result corresponding to each to-be-verified chip is obtained.

[0090] S202, determine the target mask revision result according to the verification result corresponding to each to-be-verified chip.

[0091] Optionally, from the tape-out verification results corresponding to the plurality of to-be-verified chips obtained after the plurality of mask revisions of the to-be-tested chip, a to-be-verified chip with the best mask revision effect is selected as the target mask revision result corresponding to the to-be-tested chip. The target mask revision result is used to indicate that there is no metal silicide side-penetration between the two transistors after the mask revision optimization, thereby causing the storage chip to have storage bit leakage and functional damage.

[0092] In an optional embodiment, the operation of the above step S203 can be specifically:

[0093] If the leakage current in the leakage data of the target to-be-verified chip among the to-be-verified chips reaches the preset threshold value, and each test item in the functional test data of the target to-be-verified chip is qualified, the target to-be-verified chip is determined as the target mask revision result.

[0094] Optionally, the preset threshold value is a current threshold value preset by a user, and the preset threshold value is used to indicate a leakage current limit value of the to-be-detected chip. When the leakage current in the leakage data of the to-be-detected chip reaches the preset threshold value, it is determined that the to-be-detected chip does not have a leakage current. The preset threshold value can be 0A, 0.01 mA, etc., which is not limited in the present application.

[0095] Optionally, the target to-be-verified chip indicates a to-be-verified chip with the best leakage treatment effect among a plurality of to-be-verified chips obtained by optimizing a to-be-detected chip through a plurality of mask revisions. One to-be-detected chip corresponds to at least one to-be-verified chip. Similarly, one to-be-verified chip has at least one target to-be-verified chip with the best leakage treatment effect.

[0096] Optionally, when the leakage current in the leakage data of the target to-be-verified chip among the plurality of to-be-verified chips obtained by optimizing the to-be-detected chip through a plurality of mask revisions reaches the preset threshold value, and each test item in the functional test data of the target to-be-verified chip is qualified, that is, the target to-be-verified chip does not have a leakage current, and the voltage detection result, the current detection result, the timing detection result, and the functional detection result of the target to-be-verified chip are all qualified, the target to-be-verified chip is taken as the target mask revision result of the to-be-detected chip.

[0097] Figure 3 A structure diagram of a storage chip before mask optimization is provided in the present application, see Figure 3 The present application provides a storage chip, and a metal silicide Silicide is arranged in the space between two polysilicon in the storage chip.

[0098] Figure 4 A structure diagram of a storage chip after mask optimization is provided in the present application, see Figure 4 The present application provides a storage chip, and a metal silicide Silicide is arranged in the space between two polysilicon in the storage chip.

[0099] Figure 5 A schematic diagram of a mask optimization model is provided in the present application, see Figure 5 After the to-be-detected chip on the wafer is optimized by the mask optimization model, the unqualified rate of the to-be-detected chip on the wafer is obviously reduced.

[0100] Figure 6A comparison result diagram of leakage data of a storage chip before and after mask optimization is provided in the present application, see Figure 6 The leakage data of the storage chip before and after mask optimization provided by the embodiments of the present application is obviously reduced.

[0101] In an optional implementation, the operation of performing function test on the to-be-tested chip in step S102 to obtain function test data of the to-be-tested chip can be specifically as follows:

[0102] The consistency of the to-be-tested chip is detected to obtain the function test data of the to-be-tested chip.

[0103] Optionally, the consistency of the to-be-tested chip on the wafer is detected to obtain the function test data of the to-be-tested chip, such as current detection result, voltage detection result, timing detection result, and each function test result.

[0104] Figure 7 A distribution diagram of consistency test result of a storage chip is provided in the present application, see Figure 7 The pass rate of the to-be-tested chip distributed at the edge of the wafer is relatively low.

[0105] Figure 8 Another distribution diagram of consistency test result of a storage chip is provided in the present application, see Figure 8 The pass rate of the to-be-tested chip distributed at the right lower middle area of the wafer is relatively low.

[0106] In an optional implementation, see Figure 9 The operation of step S102 can be specifically as follows:

[0107] S901, determining the leakage direction of the to-be-tested chip according to the comparison result of the original leakage data and the current leakage data.

[0108] Optionally, according to the comparison result of the leakage current in the original leakage data and the leakage current in the current leakage data, the leakage direction of the to-be-tested chip can be determined, that is, the leakage current which is obviously increased relative to the original leakage current is taken as the leakage trend of the to-be-tested chip, that is, the leakage of the to-be-tested chip becomes more serious.

[0109] It is worth noting that the current leakage data of each detection chip is compared with the original leakage data of the detection chip, and the comparison of the leakage data is based on the comparison of the leakage data under the same detection voltage.

[0110] S902, determining the leakage source of the to-be-tested chip according to the current leakage data and the pre-constructed leakage analysis model.

[0111] Optionally, the current leakage data of the chip to be detected is input into the pre-constructed leakage analysis model, and the leakage source of the chip to be detected can be determined. The leakage source of the chip to be detected can be gate-to-drain leakage, can also be channel leakage caused by metal silicide side penetration, and can also be junction leakage. The present application does not make specific limitation thereto. It should be noted that the leakage source is used to indicate the factor or fuse that causes the leakage of the reduced chip to be detected.

[0112] S903, determining the leakage point of the chip to be detected according to the functional test data.

[0113] Optionally, the leakage point is used to indicate the physical position of the chip to be detected on the wafer. According to the functional test data of each chip to be detected, whether each chip to be detected passes the test is marked on the wafer. According to the marking results of each chip to be detected on the wafer, the leakage point of the chip to be detected is determined.

[0114] S904, determining whether the leakage point of the chip to be detected is a polysilicon spacing.

[0115] Optionally, according to the leakage point of each chip to be detected marked on the wafer, it is judged whether the leakage point of each chip to be detected is a polysilicon spacing.

[0116] Figure 10 A comparison result schematic diagram of leakage data of a storage chip before and after the area is reduced is provided for the present application, see Figure 10 According to the comparison of the leakage data of the storage chip before and after the area is reduced, it can be determined that the current leakage data of the chip to be detected is significantly increased relative to the original leakage data.

[0117] Figure 11 A structure schematic diagram of a leakage analysis model is provided for the present application, see Figure 11 According to the leakage current between the transistor SG and the transistor CG, it is determined that the chip to be detected has too close polysilicon spacing, and the long metal silicide in the polysilicon spacing occurs side penetration, resulting in leakage data of the chip to be detected.

[0118] In an optional embodiment, see Figure 12 The operation of step S901 can be specifically:

[0119] S1201, comparing the gate-to-drain leakage data in the original leakage data with the gate-to-drain leakage data in the current leakage data to obtain a first comparison result.

[0120] Optionally, the gate-to-drain leakage data is used to indicate leakage data in the chip to be detected caused by gate-to-drain leakage, and the gate-to-drain leakage data in the current leakage data of the chip to be detected is compared with the gate-to-drain leakage data in the original leakage data of the original chip corresponding to the chip to be detected, to determine whether the gate-to-drain leakage data in the current leakage data of the chip to be detected after the area reduction is increased.

[0121] S1202, compare the channel leakage data in the original leakage data with the channel leakage data in the current leakage data to obtain a second comparison result.

[0122] Optionally, the channel leakage data is used to indicate leakage data in the chip to be detected caused by metal silicide side-punching through polysilicon, and the channel leakage data in the current leakage data of the chip to be detected is compared with the channel leakage data in the original leakage data of the original chip corresponding to the chip to be detected, to determine whether the channel leakage data in the current leakage data of the chip to be detected after the area reduction is increased.

[0123] S1203, compare the junction leakage data in the original leakage data with the junction leakage data in the current leakage data to obtain a third comparison result.

[0124] Optionally, the junction leakage data is used to indicate leakage data in the chip to be detected caused by PN junction leakage, and the junction leakage data in the current leakage data of the chip to be detected is compared with the junction leakage data in the original leakage data of the original chip corresponding to the chip to be detected, to determine whether the junction leakage data in the current leakage data of the chip to be detected after the area reduction is increased.

[0125] S1204, determine the leakage direction of the chip to be detected according to the maximum value among the first comparison result, the second comparison result, and the third comparison result.

[0126] In an optional implementation, the operation of step S902 can be specifically:

[0127] inputting the current leakage data into a pre-constructed leakage analysis model to obtain the leakage source of the chip to be detected, the pre-constructed leakage analysis model including a gate-to-drain leakage analysis item, a channel leakage analysis item, and a junction leakage analysis item.

[0128] Optionally, the current leakage data of the chip to be detected is input into the pre-constructed leakage analysis model, so that the specific reason causing the chip to be detected to generate the leakage data can be determined. The pre-constructed leakage analysis model includes a gate-to-drain leakage analysis item, a channel leakage analysis item and a junction leakage analysis item. The gate-to-drain leakage analysis item is used to analyze the gate-to-drain leakage data of the chip to be detected. The channel leakage analysis item is used to analyze the channel leakage data of the chip to be detected. The junction leakage analysis item is used to analyze the junction leakage data of the chip to be detected. The gate-to-drain leakage analysis item has the characteristics of the gate of the storage chip causing the drain leakage. The channel leakage analysis item has the characteristics of the metal silicide side of the storage chip causing the leakage. The junction leakage analysis item has the characteristics of the PN junction of the storage chip causing the leakage of the storage chip.

[0129] In an optional embodiment, the operation of step S903 can be specifically as follows:

[0130] According to the qualified rate of each test item in the functional test data, the leakage point of the chip to be detected is determined, and the leakage point is marked on the wafer on which the chip to be detected is located.

[0131] Optionally, according to the test results of each test item in the functional test data of the chip to be detected, each chip to be detected is marked on the wafer. Only when all the test items in the functional test data of the chip to be detected are qualified, the chip to be detected can be marked as a qualified storage chip on the wafer.

[0132] Optionally, according to the functional test data or the CP test result of the chip to be detected, the chip to be detected is marked on the wafer on which the chip to be detected is located.

[0133] In an optional embodiment, referring to Figure 13 , the operation of step S103 can be specifically as follows:

[0134] S1301, according to the cross-section measurement result of the chip to be detected, the polysilicon interval and the current growth interval of the metal silicide in the chip to be detected are determined.

[0135] Optionally, the cross-section of the chip to be detected is measured by means of a measurement tool, so as to obtain the interval size between two transistors in the chip to be detected and the current growth interval of the metal silicide between the two transistors in the chip to be detected.

[0136] S1302, according to the comparison result of the current growth interval and the marked growth interval, it is determined whether the current growth interval of the metal silicide in the chip to be detected exceeds the marked growth interval.

[0137] Optionally, according to the size comparison and the position area comparison between the current growth interval and the calibration growth interval, it can be determined whether the current growth interval of the metal silicide which is commonly long between the two transistors in the to-be-detected chip exceeds the calibration growth interval, that is, whether the metal silicide which is commonly long between the two transistors side penetrates.

[0138] Figure 14 A physical cross-sectional view of a storage chip is provided in the present application, see Figure 14 The current growth interval of the metal silicide which is commonly long between the two polysilicon spacings of the storage chip provided in the embodiments of the present application does not exceed the calibration growth interval, that is, the polysilicon spacing of the storage chip after the area reduction is too close, but the metal silicide which is commonly long between the polysilicon spacings does not side penetrate.

[0139] Figure 15 Another physical cross-sectional view of a storage chip is provided in the present application, see Figure 15 The current growth interval of the metal silicide which is commonly long between the two polysilicon spacings of the storage chip provided in the embodiments of the present application exceeds the calibration growth interval, that is, the polysilicon spacing of the storage chip after the area reduction is too close, and the metal silicide which is commonly long between the polysilicon spacings side penetrates.

[0140] Figure 16 A manufacturing process flow chart for reducing the leakage of a small storage chip is provided in the present application, see Figure 16 The specific manufacturing process for reducing the leakage of the small storage chip provided in the embodiments of the present application is as follows: according to the leakage data of a large number of storage chips before and after the area reduction, a leakage analysis model is constructed; the storage chips after the area reduction are subjected to CP testing to obtain the consistency test results of the storage chips after the area reduction, and the wafer yield is determined according to the functional test data of each storage chip on the wafer after the area reduction; the storage chips after the area reduction are subjected to physical sectioning to obtain the cross-sectional structure diagram of the storage chips after the area reduction, and the cross-sectional diagram of the storage chip is measured by means of a measuring tool to obtain the polysilicon spacing in the storage chip after the area reduction and the current growth interval of the metal silicide which is commonly long in the polysilicon spacing; according to the leakage data of the storage chips before and after the area reduction, the pre-constructed leakage analysis model, the cross-sectional measurement results and the functional test results, it is determined whether the storage chips after the area reduction meet the conditions for mask optimization; and after the conditions are met, the to-be-detected chip is subjected to SAB mask revision optimization, and the wafer produced by the mask revision is tested and verified to obtain the target mask revision result.

[0141] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0142] The above descriptions are only the preferred embodiment of the present application, but not for limiting the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reducing leakage current in a small memory chip, comprising: The method comprises: obtaining current leakage data of a chip to be detected and original leakage data of an original chip corresponding to the chip to be detected, and establishing a leakage analysis model, wherein the chip to be detected is a chip obtained by area reduction on the original chip; performing a function test on the chip to be detected to obtain function test data of the chip to be detected, and determining whether a leakage point of the chip to be detected is a polysilicon spacing according to the original leakage data, the current leakage data, a pre-constructed leakage analysis model and the function test data; if yes, performing physical dissection on the chip to be detected to obtain cross-sectional measurement results of the chip to be detected, and determining whether a current growth range of a metal silicide in the chip to be detected exceeds a calibrated growth range according to the cross-sectional measurement results; if yes, performing photomask revision optimization on the chip to be detected, performing tape-out verification on a photomask revision optimization result, determining a target photomask revision result from the tape-out verification result, and performing test verification on the target photomask revision result, wherein the target photomask revision result comprises photomask revision parameter information.

2. The method of claim 1, wherein the step of reducing leakage current of the small memory chip is characterized by, The photomask revision optimization on the chip to be detected comprises: performing photomask revision optimization on the chip to be detected based on a pre-set photomask revision step to obtain a chip to be detected after photomask revision optimization.

3. The method of claim 1, wherein the step of reducing leakage current of the small memory chip is characterized by, The tape-out verification on the photomask revision optimization result and the determination of the target photomask revision result from the tape-out verification result comprise: performing multiple times of photomask revision optimization on the chip to be detected based on the pre-set photomask revision step, and obtaining leakage data and function test data of each chip to be verified after each time of photomask revision optimization; determining a verification result corresponding to each chip to be verified according to the leakage data and the function test data of each chip to be verified; determining the target photomask revision result according to the verification result corresponding to each chip to be verified.

4. The method of claim 3, wherein the step of applying a voltage to the small memory chip is performed by applying a voltage to the small memory chip in a range of 0.5 to 1.5 volts. The determination of the target photomask revision result according to the verification result corresponding to each chip to be verified comprises: if leakage current in the leakage data of a target chip to be verified among the chips to be verified reaches a pre-set threshold value and each test item in the function test data of the target chip to be verified is qualified, then the target chip to be verified is determined as the target photomask revision result.

5. The method of claim 1, wherein the step of reducing leakage current of the small memory chip is characterized by, The function test on the chip to be detected to obtain the function test data of the chip to be detected comprises: performing consistency detection on the chip to be detected to obtain the function test data of the chip to be detected.

6. The method of claim 1, wherein the step of reducing leakage current of the small memory chip is characterized by, The determination of whether the leakage point of the chip to be detected is the polysilicon spacing according to the original leakage data, the current leakage data, the pre-constructed leakage analysis model and the function test data comprises: determining a leakage direction of the chip to be detected according to a comparison result of the original leakage data and the current leakage data; determining a leakage source of the chip to be detected according to the current leakage data and the pre-constructed leakage analysis model; determining the leakage point of the chip to be detected according to the function test data; determining whether the leakage point of the chip to be detected is the polysilicon spacing.

7. The method of claim 6, wherein the step of applying a voltage to the small memory chip is performed by applying a voltage to the small memory chip in a range of 0.5 to 1.5 volts. The method comprises the following steps: comparing the gate-to-drain leakage data in the original leakage data with the gate-to-drain leakage data in the current leakage data to obtain a first comparison result; comparing the channel leakage data in the original leakage data with the channel leakage data in the current leakage data to obtain a second comparison result; comparing the junction leakage data in the original leakage data with the junction leakage data in the current leakage data to obtain a third comparison result; determining the leakage direction of the chip to be detected according to the maximum value among the first comparison result, the second comparison result and the third comparison result.

8. The method of claim 6, wherein the step of reducing leakage current of the small memory chip is characterized by, The method comprises the following steps: inputting the current leakage data into the pre-constructed leakage analysis model to obtain the leakage source of the chip to be detected, wherein the pre-constructed leakage analysis model comprises a gate-to-drain leakage analysis item, a channel leakage analysis item and a junction leakage analysis item.

9. The method of claim 6, wherein the step of reducing leakage current of the small memory chip is characterized by, The method comprises the following steps: determining the leakage point of the chip to be detected according to the qualified rate of each test item in the functional test data, and marking the leakage point on the wafer on which the chip to be detected is located.

10. The method of claim 1, wherein the step of reducing leakage current of the small memory chip is characterized by, The method comprises the following steps: determining the polysilicon spacing and the current growth interval of the metal silicide in the chip to be detected according to the cross-section measurement result of the chip to be detected; determining whether the current growth interval of the metal silicide in the chip to be detected exceeds the calibration growth interval according to the comparison result of the current growth interval and the calibration growth interval.

Images