Method of forming semiconductor structure
By forming a specific hierarchical structure on the wafer and exposing the grinding stop layer using the grinding buffer layer technology, the problems of surface inhomogeneity and etching step adjustment in traditional processes are solved, and a more uniform and precise semiconductor structure formation is achieved.
Patent Information
- Application Number
- CN202411965727.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-23
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-04
AI Technical Summary
The traditional process of grinding the oxide layer cannot provide a sufficiently uniform surface, resulting in manual adjustment of the etching process, and the thickness of different wafers is unstable, affecting the uniformity of the etching steps.
By forming an anti-reflection layer, an oxide layer and a grinding stop layer on the wafer, and under the action of the grinding buffer layer, the buffer layer is partially removed, exposing the grinding stop layer, and then exposing the photoresist pattern by etching.
A more uniform semiconductor structure formation is achieved, reducing the need for manual adjustment of the etching process, and improving the uniformity and precision of the semiconductor structure.
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Figure CN119764172A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for forming a semiconductor structure. Background Art
[0002] Converting LF patterns into semiconductor structures usually involves forming photoresist patterns and various oxide layers on a wafer. Thereafter, the oxide layers are ground and etched for subsequent processes to convert the pattern. One of the oxide layers can serve as a buffer layer to protect the underlying structure from damage and corrosion caused by grinding and / or etching.
[0003] However, conventional processes for grinding the oxide layer do not provide a sufficiently uniform surface, so adjustments to the subsequent etching process are generally required. The thickness of different wafers is not stable and the thickness uniformity within a wafer is poor, resulting in the etching step requiring manual adjustments to the etching process time. Summary of the invention
[0004] According to an embodiment of the present invention, a method for forming a semiconductor structure includes forming an anti-reflective layer on a photoresist pattern on a wafer, forming an oxide layer on the anti-reflective layer and the photoresist pattern, wherein the oxide layer has a protrusion overlapping the photoresist pattern, forming a grinding stop layer along the upper surface of the oxide layer, forming a buffer layer on the grinding stop layer, grinding the buffer layer so that at least a portion of the buffer layer is removed and the grinding stop layer is exposed, and etching the buffer layer, the grinding stop layer and the oxide layer to expose the photoresist pattern.
[0005] In some embodiments, grinding the buffer layer is performed to expose the grinding stop layer on the protruding portions of the oxide layer.
[0006] In some embodiments, grinding the buffer layer is performed to remove an upper portion of the buffer layer that does not overlap the photoresist pattern.
[0007] In some embodiments, grinding the buffer layer is performed such that an upper surface of the buffer layer that does not overlap the photoresist pattern is coplanar with an upper surface of the grinding stop layer on the protrusion of the oxide layer.
[0008] In some embodiments, grinding the buffer layer is performed such that the upper surface of the oxide layer overlapping the photoresist pattern is recessed and exposed through the grinding stop layer.
[0009] In some embodiments, after grinding the buffer layer, the buffer layer has a thickness in a range of 50 nanometers to 60 nanometers.
[0010] In some embodiments, polishing the buffer layer includes dispensing a polishing liquid and a surfactant.
[0011] In some embodiments, the friction force of the grinding stop layer against the grinding liquid is different from the friction force of the buffer layer against the grinding liquid.
[0012] In some embodiments, the material of the grinding stop layer includes silicon nitride and the material of the buffer layer includes tetraethoxysilane (TEOS) oxide.
[0013] In some embodiments, the slurry is dispensed at a rate ranging from 50 milliliters per minute to 60 milliliters per minute.
[0014] In some embodiments, the surfactant is dispensed at a rate ranging from 200 milliliters per minute to 350 milliliters per minute.
[0015] In some embodiments, the method of forming a semiconductor structure further includes forming a nitride layer on the wafer, and before forming the photoresist pattern, forming an anti-reflective layer on the nitride layer.
[0016] In some embodiments, the anti-reflection layer is a dielectric coating film, and the material of the anti-reflection layer includes carbon.
[0017] In some embodiments, the buffer layer has a thickness in a range from 150 nanometers to 250 nanometers.
[0018] According to an embodiment of the present invention, a method for forming a semiconductor structure includes forming a nitride layer on a wafer, forming an anti-reflective layer on the nitride layer, forming a photoresist pattern on the anti-reflective layer, forming an oxide layer on the anti-reflective layer and the photoresist pattern, wherein the oxide layer has a protrusion overlapping with the photoresist pattern, forming a grinding stop layer along the upper surface of the oxide layer, forming a buffer layer on the grinding stop layer, and grinding the buffer layer to remove at least a portion of the buffer layer and expose the grinding stop layer.
[0019] In some embodiments, grinding the buffer layer is performed to expose the grinding stop layer on the protruding portions of the oxide layer.
[0020] In some embodiments, grinding the buffer layer is performed to remove an upper portion of the buffer layer above an upper surface of the grinding stop layer on the protruding portion of the oxide layer.
[0021] In some embodiments, grinding the buffer layer is performed such that an upper surface of the buffer layer that does not overlap the photoresist pattern is coplanar with an upper surface of the grinding stop layer.
[0022] In some embodiments, polishing the buffer layer includes dispensing a polishing liquid and a surfactant.
[0023] In some embodiments, the friction force of the grinding stop layer against the material of the grinding liquid is different from the friction force of the oxide layer against the material of the grinding liquid.
[0024] In the above method of forming a semiconductor structure, by using a grinding stop layer, the grinding process performs better, resulting in a more uniform semiconductor structure, and thus manual adjustment of the etching process (eg, etching process time adjustment) is generally not required.
[0025] It is to be understood that both the foregoing general description and the following detailed description are by way of example, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The present invention can be more fully understood by reading the detailed description of the following embodiments, with reference to the accompanying drawings:
[0027] Figure 1 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present invention.
[0028] Figures 2 to 7 are cross-sectional views of various stages in a method of forming a semiconductor structure according to some embodiments of the present invention.
[0029] Figure 8 and Fig. 9 are cross-sectional views of various stages of a method of forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION
[0030] Reference will now be made in detail to the embodiments of the invention, examples of which are described in conjunction with the accompanying drawings, wherein the same reference numerals throughout the drawings and the description are used to refer to the same or like parts.
[0031] Figure 1 A flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 1 In step S1, a photoresist pattern is formed on an anti-reflection layer on a wafer. Next, in step S2, an oxide layer is formed on the anti-reflection layer and the photoresist pattern, and next, in step S3, a grinding stop layer is formed along an upper surface of the oxide layer. Then. In step S4, a buffer layer is formed on the grinding stop layer. After that, in step S5, the buffer layer is ground so that at least a portion of the buffer layer is removed and the grinding stop layer is exposed. Thereafter, in step S6, the buffer layer, the grinding stop layer and the oxide layer are etched so that the photoresist pattern is exposed.
[0032] Each of the aforementioned steps S1 to S6 may include a plurality of detailed steps. The method for forming a semiconductor structure may further include other steps, which may be included between step S1 and step S6, and may include other steps before step S1 and after step S6. In the following description, the aforementioned steps S1 to S6 will be explained in more detail.
[0033] Figures 2 to 7The semiconductor structure 100 is formed according to some embodiments of the present invention (see Figure 7 ) is a cross-sectional diagram of the various stages of the method. Figure 2 , a photoresist pattern 140 is formed on the anti-reflection layer 130 on the wafer. In the present embodiment, the wafer 110 includes an array region 112, a peripheral region 114, and a device region 116. The device region 116 may include a sense amplifier (SA) circuit and / or a sub-word line driver (SWD) circuit, and the photoresist pattern 140 overlaps the device region 116.
[0034] The photoresist pattern 140 is used to transfer a pattern or layout, such as a LF pattern for the semiconductor structure 100. Although the photoresist pattern 140 is illustrated as having two portions overlapping each other, Figure 2 The number, arrangement and appearance of the photoresist layer 140 of the two device regions 116 of the wafer 110 are not limited thereby.
[0035] In the present embodiment, before the photoresist pattern 140 is formed, the nitride layer 120 is formed on the wafer 110, and the anti-reflection layer 130 is formed on the nitride layer 120. The nitride layer 120 and the anti-reflection layer 130 allow the photoresist pattern 140 to be more accurately formed by absorbing a standard wave during the development of the photoresist pattern 140. In some embodiments, the anti-reflection layer 130 is a dielectric anti-reflective coating (DARC) film, and the material of the anti-reflection layer 130 includes carbon.
[0036] After the photoresist pattern 140 is formed, an oxide layer 150 is formed on the photoresist pattern 140 and the anti-reflection layer 130. The oxide layer 150 has a protrusion 152 overlapping the photoresist pattern 140. In this embodiment, the oxide layer 150 is formed using atomic layer deposition (ALD). The material of the oxide layer 150 includes silicon oxide.
[0037] Afterwards, refer to Figure 3 The grinding stop layer 160 is formed along the upper surface of the oxide layer 150. In this embodiment, the grinding stop layer 160 is formed using an atomic layer deposition process. The material of the grinding stop layer 160 includes silicon nitride.
[0038] After the grinding stop layer is formed, refer to Figure 4, a buffer layer 170 is formed on the grinding stop layer 160. The buffer layer 170 has an upper portion 172 above the upper surface 162 of the grinding stop layer 160 on the protrusion 152. In the present embodiment, the buffer layer 170 is formed by depositing tetraethoxysilane (TEOS) oxide. In other words, the material of the buffer layer 170 includes tetraethoxysilane oxide. The buffer layer 170 has a thickness T1, and the thickness T1 ranges from 150 nanometers to 250 nanometers, for example, 200 nanometers.
[0039] Afterwards, refer to Figure 5 , the buffer layer 170 is ground so that at least a portion of the buffer layer 170 is removed and the grinding stop layer 160 is exposed. In this embodiment, the upper portion of another buffer layer 170 that does not overlap the photoresist pattern 140 is removed. The grinding of the buffer layer 170 uses a chemical mechanical planarization (CMP) process. In this embodiment, grinding the buffer layer 170 is performed to expose the grinding stop layer 160 on the protrusion 152 of the oxide layer 150. That is, the upper portion 172 of the buffer layer 170 is removed. After grinding the buffer layer 170, the thickness T2 of the buffer layer 170 overlapping the array area 112 of the wafer 110 may be in the range of 45 nanometers to 65 nanometers, such as 50 nanometers.
[0040] Polishing the buffer layer 170 includes dispensing a slurry and a surfactant. In some embodiments, polishing the buffer layer 170 includes a chemical mechanical planarization process using a slurry and a surfactant. In this embodiment, the rate of slurry dispensing is in the range of 50 mm to 60 mm per minute, such as 55 mm per minute. The rate of surfactant dispensing is in the range of 200 mm to 350 mm per minute, such as 220 mm per minute. The down force applied in the chemical mechanical planarization process of polishing the buffer layer 170 is reduced.
[0041] The polishing buffer layer 170 includes an end-point detection (EPD) process, and the end-point detection process detects a torque change of the motor of the polishing device. In the present invention, because the difference between the material of the polishing stop layer 160 (i.e., silicon nitride) and the buffer layer 170 (i.e., tetraethoxysilane oxide) is that the friction force of the polishing stop layer 160 against the polishing liquid and the friction force of the buffer layer 170 against the polishing liquid are different. Finally, by applying the end-point detection process and the detection process to detect the torque change of the motor of the polishing device, because the polishing stop layer 160 on the protrusion 152 of the oxide layer 150 is exposed, when the first torque change is detected and the polishing stop layer 160 on the protrusion 152 of the oxide layer 150 is exposed, the polishing process can be stopped reliably.
[0042] In this embodiment, the use of the polishing stop layer 160, the use of the surfactant and the use of the endpoint detection process reduce the step height of the surface of the oxide layer 150 and improve the precision of the polishing buffer layer 170. Therefore, the within-wafer (WiW) uniformity of the semiconductor structure 100 can be controlled and applied by the aforementioned theory.
[0043] Reference Figure 6 In another embodiment, grinding the buffer layer 170 includes dispensing the surfactant at a rate ranging from 200 ml / min to 350 ml / min, e.g., 330 mm / min, and the applied down force is not reduced. By increasing the flow rate of the surfactant, erosion of the buffer layer 170 on the peripheral region 114 of the wafer 110 is reduced, and the upper surface of the buffer layer 170 that does not overlap the photoresist pattern 140 (e.g., the buffer layer 170 on the peripheral region 114 of the wafer 110) is coplanar with the upper surface 162 of the grinding stop layer 160 on the protrusion 152 of the oxide layer 150. Therefore, the wafer-to-wafer (WtW) uniformity of the semiconductor structure 100 is also improved by the theory of this embodiment.
[0044] Afterwards, refer to Figure 7 , the buffer layer 170, the grinding stop layer 160, and the oxide layer 150 are etched to expose the photoresist pattern 140. After etching the buffer layer 170, the grinding stop layer 160, and the oxide layer 150, the upper surface of the oxide layer 150 and the photoresist pattern 140 allow for further processing to transfer the pattern to the semiconductor structure 100. Because the grinding process for the buffer layer 170, as described above, is more precise and better controlled, the etching process for the buffer layer 170, the grinding stop layer 160, and the oxide layer 150 may not require adjustment of process time and / or other parameters. For example, the etching step does not require manual adjustment of the etching time.
[0045] Figure 8 and Fig. 9 is a cross-sectional view of various stages of a method of forming a semiconductor structure 100 according to another embodiment of the present invention. Figure 4 and Figure 8 ,exist Figure 4 After the structure is formed, the buffer layer 170 is polished so that the upper surface of the oxide layer 150 overlapping the photoresist pattern 140 is recessed and exposed through the polishing stop layer 160. That is, after the buffer layer 170 is polished, the protruding portion 152 of the oxide layer 150 is removed. In this embodiment, the buffer layer 170 is polished to remove the entire buffer layer 170 and expose the polishing stop layer 160 not on the protruding portion 152 of the oxide layer 150.
[0046] In this embodiment, the endpoint detection process is also applied to detect the torque change of the motor of the polishing device due to the polishing stop layer 160 not on the protrusion 152 of the oxide layer 150. In particular, when the polishing stop layer 160 not on the protrusion 152 of the oxide layer 150 is exposed, a second change in torque can be detected.
[0047] Afterwards, refer to Fig. 9 , the grinding stop layer 160 and the oxide layer 150 are etched to expose the photoresist pattern 140. In this way, the semiconductor structure 100a is formed. Because the grinding process for the buffer layer 170 is accurate and easy to control as described above, the process of etching the grinding stop layer 160 and the oxide layer 150 does not require adjustment of process time and / or parameters. In the present embodiment, slight erosion of the photoresist pattern 140 may occur, but this erosion affects the formation of the semiconductor structure 100a. The grinding process used in the present embodiment improves the intra-wafer uniformity of the semiconductor structure 100a, the wafer-to-wafer uniformity of the semiconductor structure 100a, the grain-to-grain uniformity of the semiconductor structure 100a, and the grinding precision.
[0048] In summary, as described above in the theory of forming a semiconductor structure, by using a polishing stop layer, the performance of the polishing process is increased, resulting in better uniformity of the semiconductor structure, and thus adjustments (such as process time adjustments) of the etching process are generally not required.
[0049] Although the present invention has been described in considerable detail with reference to specific embodiments herein, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.
[0050] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims.
[0051]
Explanation of symbols
[0052] 100,100a:Semiconductor structure
[0053] 110: Wafer
[0054] 112: Array area
[0055] 114: Surrounding area
[0056] 116: Installation area
[0057] 120: Nitride layer
[0058] 130: Anti-reflection layer
[0059] 140: photoresist pattern, photoresist layer
[0060] 150: Oxide layer
[0061] 152: protrusion
[0062] 160: Grinding stop layer
[0063] 162: Upper surface
[0064] 170: Buffer layer
[0065] 172: Upper part
[0066] S1, S2, S3, S4, S5, S6: Steps
[0067] T1, T2: thickness.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: forming an anti-reflection layer of a photoresist pattern on a wafer; forming an oxide layer on the anti-reflection layer and the photoresist pattern, wherein the oxide layer has a protrusion overlapping the photoresist pattern; forming a grinding stop layer along an upper surface of the oxide layer; forming a buffer layer on the grinding stop layer; grinding the buffer layer so that at least a portion of the buffer layer is removed and the grinding stop layer is exposed; as well as The buffer layer, the grinding stop layer and the oxide layer are etched to expose the photoresist pattern.
2. The method for forming a semiconductor structure according to claim 1, wherein: Grinding the buffer layer is performed to expose the grinding stop layer on the protruding portion of the oxide layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: Grinding the buffer layer is performed to remove an upper portion of the buffer layer that does not overlap the photoresist pattern.
4. The method for forming a semiconductor structure according to claim 2, wherein: The buffer layer is polished so that an upper surface of the buffer layer that does not overlap the photoresist pattern is coplanar with an upper surface of the polishing stop layer on the protruding portion of the oxide layer.
5. The method for forming a semiconductor structure according to claim 1, wherein: The buffer layer is polished to make the upper surface of the oxide layer overlapping the photoresist pattern recessed and exposed through the polishing stop layer.
6. The method for forming a semiconductor structure according to claim 1, wherein: After grinding the buffer layer, the buffer layer has a thickness in a range of 50 nanometers to 60 nanometers.
7. The method for forming a semiconductor structure according to claim 1, wherein: Grinding the buffer layer includes dispensing a grinding liquid and a surfactant.
8. The method for forming a semiconductor structure according to claim 7, wherein: The friction force of the grinding stop layer against the grinding liquid is different from the friction force of the buffer layer against the grinding liquid.
9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the grinding stop layer includes silicon nitride and the material of the buffer layer includes tetraethoxysilane oxide.
10. The method for forming a semiconductor structure according to claim 7, wherein: The slurry is dispensed at a rate ranging from 50 ml per minute to 60 ml per minute.
11. The method for forming a semiconductor structure according to claim 7, wherein: The surfactant is dispensed at a rate ranging from 200 milliliters per minute to 350 milliliters per minute.
12. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a nitride layer on the wafer; and Before forming the photoresist pattern, the anti-reflection layer is formed on the nitride layer.
13. The method for forming a semiconductor structure according to claim 1, wherein: The anti-reflection layer is a dielectric coating film, and a material of the anti-reflection layer includes carbon.
14. The method for forming a semiconductor structure according to claim 1, wherein: The buffer layer has a thickness in a range from 150 nanometers to 250 nanometers.
15. A method for forming a semiconductor structure, characterized in that: include: forming a nitride layer on the wafer; forming an anti-reflection layer on the nitride layer; forming a photoresist pattern on the anti-reflection layer; forming an oxide layer on the anti-reflection layer and the photoresist pattern, wherein the oxide layer has a protrusion overlapping the photoresist pattern; forming a grinding stop layer along an upper surface of the oxide layer; forming a buffer layer on the grinding stop layer; as well as The buffer layer is polished to remove at least a portion of the buffer layer and expose the polishing stop layer.
16. The method for forming a semiconductor structure according to claim 15, wherein: Grinding the buffer layer is performed to expose the grinding stop layer on the protruding portion of the oxide layer.
17. The method for forming a semiconductor structure according to claim 16, wherein: Grinding the buffer layer is performed to remove an upper portion of the buffer layer above an upper surface of the grinding stop layer on the protruding portion of the oxide layer.
18. The method for forming a semiconductor structure according to claim 16, wherein: Grinding the buffer layer is performed so that an upper surface of the buffer layer that does not overlap the photoresist pattern is coplanar with an upper surface of the grinding stop layer.
19. The method for forming a semiconductor structure according to claim 15, wherein: Grinding the buffer layer includes dispensing a grinding liquid and a surfactant.
20. The method for forming a semiconductor structure according to claim 19, wherein: The friction force of the grinding stop layer against the material of the grinding liquid is different from the friction force of the oxide layer against the material of the grinding liquid.