Carbon nanotube device
By forming protruding structures and undercut grooves on the dielectric layer of the integrated circuit, depositing carbon nanotubes and using graphite carbon layer to prevent adhesion, the problem of insufficient density and alignment of carbon nanotubes in the prior art is solved, and lower resistance and higher electronic device performance are achieved.
Patent Information
- Application Number
- CN202411312979.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-30
- Filing Date
- 2024-09-20
- Publication Date
- 2025-04-04
AI Technical Summary
The prior art is difficult to effectively improve the density and alignment of carbon nanotubes in field-effect transistors (FETs) in integrated circuits, resulting in a large resistance to the current channel and affecting the performance of electronic devices.
By forming a protruding structure on the dielectric layer of the integrated circuit and forming an undercut groove between the protruding structures, carbon nanotubes are deposited into the grooves, and the graphite carbon layer is used to prevent the carbon nanotube from adhesion, thereby improving the density and alignment of the carbon nanotubes.
The density and alignment of carbon nanotubes in FETs are increased, the resistance of the current channel is reduced, and the performance of electronic devices is improved.
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Figure CN119764173A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to carbon nanotube devices. Background Art
[0002] Carbon nanotubes are cylindrical molecules composed of one or more layers of carbon atoms. The diameter of single-walled carbon nanotubes with single-atom walls can be less than one nanometer. Multi-walled carbon nanotubes can contain multiple concentrically linked nanotubes with diameters between a few nanometers and one hundred nanometers. Carbon nanotube lengths range from a few nanometers to a few millimeters. Carbon nanotubes can have electrical properties such as high thermal conductivity and electrical conductivity, which makes carbon nanotubes an attractive candidate for use in photonic and electronic devices (such as light sources and detectors and transistors). Summary of the invention
[0003] In one example, a method includes forming a first layer of a first material on a dielectric layer of an integrated circuit, forming a second layer of a second material on the first layer, and patterning the second layer to expose the first layer. Through the patterned second layer, etching the exposed first layer to form protrusion structures of the first layer and the second layer and undercut grooves located between adjacent protrusion structures in the protrusion structures. The first layer of each protrusion structure has a first width, the second layer of each protrusion structure has a second width, and the second width is greater than the first width. The method also includes depositing carbon nanotubes into the undercut grooves between adjacent protrusion structures in the protrusion structures.
[0004] In another example, a method includes forming a first layer of a first material on a dielectric layer of an integrated circuit, forming a second layer of a second material on the first layer, and patterning the second layer to expose the first layer. Etching the exposed first layer through the patterned second layer to form protrusion structures of the first layer and the second layer and grooves between adjacent protrusion structures in the protrusion structures. The method also includes forming a graphitic carbon layer on at least a portion of the second layer of the protrusion structures, and depositing carbon nanotubes into the grooves between the adjacent protrusion structures in the protrusion structures. The method may further include removing the protrusion structures by etching to leave a plurality of aligned rows of carbon nanotubes on the surface of the dielectric.
[0005] In another example, a transistor includes a source, a drain, and first and second arrays of carbon nanotubes. The first array of carbon nanotubes has a first width, a first end connected to the source, and a second end connected to the drain. The second array of carbon nanotubes is adjacent to the first array of carbon nanotubes and is separated by a first spacing. The first width is greater than the first spacing. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1is a flow chart of an example method for disposing carbon nanotubes on an integrated circuit.
[0007] Figure 2 , 3 , 4, 5, 6, 7, 8, 9, 10 and 11 are diagrams showing Figure 1 A schematic diagram of an example operation of the method.
[0008] Fig.12 Is manufactured with use Figure 1 A flow chart of an example method of depositing carbon nanotube transistors.
[0009] Fig.13 , 14 , 15, 16, 17, 18 and 19 are diagrams showing Fig.12 A schematic diagram of an example operation of the method.
[0010] Fig. 20 It shows that according to Fig.12 Schematic diagram of an example of a method for fabricating a transistor with carbon nanotubes and a top gate.
[0011] Fig.21 It shows that according to Fig.12 Schematic diagram of an example of a method for fabricating a transistor with carbon nanotubes and a global back gate. DETAILED DESCRIPTION
[0012] Electronic devices such as field effect transistors (FETs) may include carbon nanotubes that are electrically connected between two current terminals (e.g., source and drain) of the FET to provide a conductive path between the current terminals. Both the number of carbon nanotubes between the current terminals and the alignment of the carbon nanotubes relative to the current terminals may affect the resistance of the current path formed by the carbon nanotubes. Specifically, where more carbon nanotubes are positioned within the footprint of the transistor, the current path formed by the carbon nanotubes can carry more current and the resistance of the current path can be reduced. Also, where the carbon nanotubes are more aligned with the longitudinal axis of the FET, this can provide the shortest path between the current terminals, and the distance that the current travels between the current terminals can be reduced / minimized, thereby further reducing the resistance of the current path.
[0013] The example technology to be described herein can increase the number of carbon nanotubes deposited between the current terminals of the FET while improving the alignment of the carbon nanotubes with the longitudinal axis of the FET. Specifically, a protrusion structure extending between the current terminals of the FET is formed on a dielectric layer. Each protrusion structure may include a second layer and a first layer (or link layer), wherein the first layer is located between the second layer and the dielectric layer. The second layer may have a first width, and the first layer may have a second width, wherein the first width is greater than the second width. The protrusion structures adjacent to the second layer may be spaced apart by a first distance, and the protrusion structures adjacent to the first layer may be spaced apart by a second distance longer than the first distance.
[0014] In some instances, the first width of the second layer and the first distance between the protrusion structures adjacent to the second layer can be the same and reflect the minimum line width of the photolithography process used to pattern and etch the second layer. The etching of the second layer can be performed using an isotropic etchant. After the second layer is patterned and the first layer is exposed, an anisotropic etchant or an isotropic etchant but the etching time is extended to overetch the exposed first layer to form an undercut groove under the patterned second layer. In some instances, the undercut can reach 50% of the first width of the second layer of each protrusion structure. The undercut can increase the width of the groove between the protrusion structures adjacent to the first layer, thereby achieving carbon nanotube diffusion and thus achieving a larger surface coverage.
[0015] In some examples, the second layer of the protrusion structure can be coated with a graphite carbon layer with low adhesion to carbon nanotubes. During etching of the bottom layer, the graphite carbon layer can also serve as an etch stop layer of the second layer to promote over-etching / undercutting of the exposed first layer. In addition, the graphite carbon layer can be grown on the top metal layer to have a well-defined thickness, for example, less than 1nm, so that the first distance between the protrusion structures adjacent to the second layer (which reduces the thickness of the graphite carbon layer) can also be clearly defined, and the first distance across the protrusion structure can be substantially uniform. After forming the protrusion structure, the carbon nanotubes in the solution can be deposited (for example, immersed, rotated, and slipped) in the grooves and undercut areas between the protrusion structures. The space between the patterned second layer protrusion structures can serve as a guide to guide and align the carbon nanotubes to the undercut grooves below the second layer to form a film. The graphite carbon coated on the second layer can prevent the carbon nanotubes from adhering to the second layer and promote the carbon nanotubes to slide into the grooves.
[0016] The alignment of the carbon nanotubes can be set by the shear rate and the first distance between adjacent protruding structures of the second layer. After the carbon nanotubes are deposited into the grooves and undercut regions and the films are formed in the grooves and undercut regions, the protruding structures can be removed. In the case of such an arrangement, the width of each carbon nanotube film in the FET can be greater than the spacing between the top metal lines or the spacing between adjacent carbon nanotube films.
[0017] By setting the first distance to the minimum line width, and by coating the second layer with a graphitic carbon layer having a well-controlled thickness, the first distance between adjacent protrusion structures of the second layer can be minimized and can be substantially uniform across the protrusion structures. Such an arrangement can maximize (or at least increase) the alignment of the carbon nanotubes in the FET.
[0018] In addition, using the techniques described herein for forming undercut grooves, the width of the grooves (the second distance between adjacent protrusion structures of the first layer) can be increased above the first distance between adjacent protrusion structures of the second layer, which can increase the density of carbon nanotubes. Compared to the case where no undercut grooves are formed and the groove width is the same as the first distance, the described techniques can increase the number of carbon nanotubes deposited between adjacent protrusion structures while improving (or at least maintaining) the alignment of the carbon nanotubes.
[0019] Figure 1 1 is a flow chart of an example method 100 of placing carbon nanotubes on an integrated circuit (IC). Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. Figure 2-11 is a schematic diagram illustrating states of an IC in an example operation of method 100 .
[0020] In block 102 , a material 202 is provided to form an integrated circuit 200 . Figure 2 A cross-sectional view of IC 200 is shown. Material 202 can be a semiconductor substrate and can include a processing layer, a buried oxide (BOX) layer, an epitaxial layer, and / or other layers that can include any of a variety of electronic devices. The processing layer can be bulk silicon or other semiconductor or insulating materials. The BOX layer, which can be omitted in some examples, can be part of a silicon-on-insulator (SOI) substrate. Although the epitaxial layer in the example shown can be lightly doped p-type silicon (active silicon), the processing layer and the epitaxial layer can be any other combination of n-type or p-type materials. In some examples, material 202 can be a backside contact metal.
[0021] In block 104, a dielectric layer 204 is disposed on the material 202. In some examples of the integrated circuit 200, the dielectric layer 204 may be a silicon dioxide layer.
[0022] In block 106, a first layer 302 is formed on dielectric layer 204. First layer 302 may include a metal (eg, aluminum or other metal) or a dielectric material (eg, silicon dioxide). Advantageously, aluminum is widely available in semiconductor manufacturing and may be used for first layer 302. Figure 3 A first layer 302 is shown on dielectric layer 204. Where first layer 302 is a metal layer, in some examples of method 100, first layer 302 may be deposited using physical vapor deposition (PVD).
[0023] In block 108, second layer 402 is formed on first layer 302 such that first layer 302 is between second layer 402 and dielectric layer 204. Second layer 402 may include a metal such as nickel, cobalt, copper, palladium, ruthenium, platinum, or a binary alloy thereof, or another metal in various instances of integrated circuit 200. Figure 4 A second layer 402 is shown on the first layer 302. In some examples of method 100, the second layer 402 can be deposited using PVD. In some examples, both the second layer 402 and the first layer 302 can be formed as part of a back end of line (BEOL) process and can be part of forming an interconnect structure on the material 202.
[0024] In block 110 , the first layer 302 and the second layer 402 are patterned and etched to form a protruding structure extending between current terminals (eg, source and drain) of the FET. Figure 5 A protrusion structure 502 is shown that is produced by etching the first layer 302 and the second layer 402. In the protrusion structure 502, the width of the second layer 402 may be greater than the width of the first layer 302, so that the protrusion structure 502 has a mushroom shape or a "T" shape, thereby forming an undercut groove 504 between adjacent protrusion structures 502. For example, the patterned second layer 402 of the protrusion structure 502 may have a width w t , the patterned first layer 302 of the protrusion structure 502 may have a width w b , where w t More than w b The adjacent protrusion structures 502 of the patterned second layer may be spaced apart by a distance d t , and adjacent protrusion structures of the first layer may be spaced apart by more than d t The distance d b . Distance d b The width of the undercut groove 504 may be defined and may also be greater than the width w of the patterned second layer. tAs described below, the patterned second layer 402 of protrusion structures 502 can act as a guide and provide a sliding surface on which the carbon nanotubes can slide through the spaces between adjacent protrusion structures into the undercut grooves below the second layer to form a film. The carbon nanotubes will be deposited in the undercut grooves 504.
[0025] In some examples, the first layer 302 and the second layer 402 can be etched in different etching processes and using reactive ion etching. For example, the etching of the second layer can be performed using an anisotropic etchant, such as a reactive ion etching process using, for example, Cl2 / Ar chemistry. After the second layer 402 is patterned and the first layer is exposed, the exposed first layer 302 can be undercut using an isotropic etchant or by an anisotropic etchant but with an extended etching time to form an undercut recess below the patterned second layer 402.
[0026] In some examples, the width w of the patterned second layer 402 of the protrusion structure 502 is t The distance d between the protrusion structure 502 adjacent to the patterned second layer 402 t may be the same and reflect the minimum line width of the photolithography process used to pattern and etch the second layer 402. For example, where the minimum line width of the photolithography process used to pattern the second layer 402 is 45 nanometers (nm), the width w t and distance d t It can be 45nm. b Greater than w t and the width w of the patterned first layer 302 b As explained below, such an arrangement allows for the t (plus other factors, such as the length of the carbon nanotubes) to set the alignment of the carbon nanotubes in the undercut grooves 504 while allowing more carbon nanotubes to be deposited in the widened undercut grooves 504.
[0027] In block 112, a graphitic carbon layer, such as graphene, is formed on at least some of the surfaces of the second layer 402. The graphitic carbon may be deposited or grown on the surface of the second layer 402 using, for example, a plasma enhanced chemical vapor deposition process tuned to deposit the graphitic carbon on a catalytic surface of a metal (e.g., nickel, cobalt) of the second layer 402 that enhances or promotes the growth / deposition of the graphitic carbon on the surface. The deposition / growth of the graphitic carbon may be at a relatively low temperature (e.g., at BEOL temperatures, such as about 300 degrees Celsius), and the thickness of the graphitic carbon deposited thereby may be less than 1-2 nm. The graphitic carbon layer has low adhesion to the carbon nanotubes and may prevent the carbon nanotubes from adhering to the surface of the second layer 402. Figure 6A graphite carbon layer 602 is shown deposited on the surface of the second layer 402. Figure 6 As shown, the thickness of the graphite carbon layer 602 can reduce the distance d between the adjacent protrusion structures 502 of the second layer 402. t However, compared to other materials that have low adhesion to carbon nanotubes (e.g., methyl compounds or other hydrocarbon compounds), the thickness of the graphite carbon layer can be relatively thin and well controlled according to the growth / deposition process. The formation of the thin graphite carbon layer may be due to, for example, the fact that graphite carbon is very non-reactive and can be grown by a thermal catalytic process or by plasma-assisted growth at low temperatures, and a single layer or a small number of layers of graphite carbon can be grown depending on the material and thickness of the second layer 402. Therefore, the distance d between adjacent protrusion structures 502 of the second layer 402 is t can also be well controlled, and the distance d t It may be substantially uniform across IC 200 .
[0028] In block 114 , carbon nanotubes are deposited in the spaces (trenches) between the protruding structures 502 . Figure 7 The integrated circuit 200 is shown immersed in a solution 702 containing carbon nanotubes 704. Alternatively, the solution 702 can flow over the surface of the integrated circuit 200 along the longitudinal axis of the protruding structures 502. The graphitic carbon 602 prevents the carbon nanotubes 704 from adhering to the surface of the second layer 402. In some examples, the carbon nanotubes 704 can be coated with a polymer. The carbon nanotubes 704 are attracted and settle on the dielectric layer 204, sliding off the graphitic carbon 602 to settle into the undercut recesses 504 between adjacent protruding structures 502.
[0029] The carbon nanotube 704 is oriented relative to the longitudinal axis of the FET ( Figure 8 The alignment of the protrusions 502 of the second layer 402 can be determined by the shear rate and the distance d between the protrusions 502 adjacent to each other. t By setting the distance d t is set to a minimum line width, and by coating the second layer with a graphite carbon layer having a well-controlled thickness, the distance d between adjacent protrusion structures 502 of the second layer 402 is t The ? can be minimized and can be substantially uniform across the protrusion structure. Such an arrangement can maximize (or at least increase / improve) the alignment of the carbon nanotubes in the FET.
[0030] Also, each of the undercut grooves 504 has a distance d between the adjacent protrusion structures 502 of the first layer 302. b The defined width can be larger than d t . With no undercut groove and groove width d b With distance d tCompared to the same situation, the formation of undercut grooves 504 allows more carbon nanotubes to be deposited between adjacent protrusion structures while improving (or at least maintaining) the alignment of the carbon nanotubes. The angle of the carbon nanotubes 704 relative to the protrusion structure 502 can be close to zero degrees, where the maximum angle depends on the length of the shortest carbon nanotube 704 and the distance d t .
[0031] In some examples of method 100, integrated circuit 200 may be dipped into solution 702 multiple times to further increase the number of carbon nanotubes 704 deposited between protruding structures 502. Other techniques for depositing carbon nanotubes 704 may be used in some examples of method 100.
[0032] Figure 8 2 is a top view of the integrated circuit 200, wherein the carbon nanotubes 704 are deposited on the dielectric layer 204 between the protruding structures 502. The width of the array of carbon nanotubes 704 (or the film of carbon nanotubes) disposed between the protruding structures 502 can be determined by the distance d between the adjacent protruding structures 502 of the first layer 302. b The spacing between adjacent arrays / films of carbon nanotubes 704 can be determined by the width w of the first layer 302 of the protruding structure 502. b Defined. Undercut at 50% and width w t and distance d t When both are the same as the minimum line width, the width of the array of carbon nanotubes 704 may be twice the minimum line width, and the spacing between adjacent arrays / films of carbon nanotubes 704 may be half the minimum line width.
[0033] In block 116, the protruding structure 502 is removed from the integrated circuit 200. Removal of the protruding structure 502 may include initial removal of the graphite carbon 602, or etching the grain boundaries of the graphite carbon 602 using an oxidizing agent such as ozone, H2O2, or HNO3 to open an etch path in the graphite carbon 602. Ammonium persulfate, (NH4)2S2O8, may be used to etch the first layer 302 and the second layer 402 through the grain boundaries while rotating the integrated circuit 200, followed by washing the reaction product. (NH4)2S2O8 does not etch the carbon nanotubes 704. Fig. 9 and 10 The integrated circuit 200 is shown after the protruding structure 502 has been removed. The carbon nanotubes 704 remain on the surface of the integrated circuit 200.
[0034] In block 118 , a layer of insulating material (a dielectric layer, such as a silicon dioxide layer) is disposed on the carbon nanotubes 704 . Fig.11 A dielectric layer 1102 is shown disposed on the carbon nanotubes 704 .
[0035] Fig.121 is a flow chart of an example method 1200 for manufacturing a transistor having carbon nanotubes deposited using method 100. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may perform only some of the actions shown. Figure 13-18 An example of various operations of method 1200 is shown. Fig.13 An example integrated circuit 1300 is shown including a semiconductor substrate 1302 and an insulating layer 1304 (eg, a silicon dioxide layer on the semiconductor substrate 1302 ).
[0036] In block 1202 , a gate 1402 is formed on the insulating layer 1304 . Fig.14 A gate 1402 is shown disposed on the insulating layer 1304. The formation of the gate 1402 may include depositing a metal or polysilicon layer on the insulating layer 1304, and etching the layer to form the gate 1402.
[0037] In block 1204 , a dielectric layer is disposed over the gate 1402 . Fig.15 A dielectric layer 1502 is shown disposed over the gate 1402. In the example of the integrated circuit 1300, the dielectric layer 1502 may be hafnium dioxide, silicon dioxide, or other dielectric material.
[0038] In block 1206, carbon nanotubes are deposited on dielectric layer 1502. The carbon nanotubes may be deposited according to method 100 to provide a carbon nanotube array aligned in a selected direction, wherein the width of the carbon nanotube array is greater than the space separating adjacent carbon nanotube arrays. Fig.16 Carbon nanotubes 1602 are shown deposited on dielectric layer 1502 over gate 1402 .
[0039] In block 1208 , source and drain electrodes are formed on the carbon nanotubes 1602 . Fig.17 Source 1702 and drain 1704 are shown formed on carbon nanotubes 1602 and dielectric layer 1502. Source 1702 and drain 1704 can be formed by depositing a metal layer (e.g., palladium for p-type devices, or low work function metals (e.g., scandium and yttrium) for n-type devices) on carbon nanotubes 1602 and dielectric layer 1502 and etching the metal to form source 1702 and drain 1704. Fig.19 A perspective view of a transistor including a source 1702, a drain 1704, carbon nanotubes 1602, a dielectric layer 1502, and a gate 1402 is shown.
[0040] In block 1210 , an insulating layer is disposed over the source 1702 , the drain 1704 , and the carbon nanotubes 1602 . Fig.18An insulating layer 1802 is shown disposed over the source 1702, drain 1704, and carbon nanotubes 1602. The insulating layer 1802 may be hafnium dioxide, silicon dioxide, or other dielectric material.
[0041] Fig.19 is a perspective view of an example of an integrated circuit 1300 fabricated according to method 1200 .
[0042] Fig. 20 is a perspective view of transistors fabricated on integrated circuit 2000 . Fig. 20 The transistor is similar to Fig.19 1402, but includes a top gate 2002 instead of a bottom gate 1402. The method 1200 may include operations to produce a carbon nanotube-based transistor having a bottom gate and / or a top gate.
[0043] Fig.21 is a perspective view of transistors fabricated on integrated circuit 2100. Fig.21 The transistor is similar to Fig.19 1402, but includes a global bottom gate 2102 instead of a local bottom gate 1402. The method 1200 may include operations to produce a carbon nanotube-based transistor having a local or global bottom gate and / or a top gate.
[0044] In addition to transistors, carbon nanotubes arranged as described herein can be used in a variety of other applications. For example, carbon nanotubes arranged as described herein can be used in sensor devices (e.g., pressure sensors, temperature sensors, gas sensors, etc.), photonic devices (e.g., photon sources, photon detectors, etc.), and other devices.
[0045] Although the use of specific transistors is described herein, other transistors (or other devices, such as photonic devices) may be used instead, with little or no changes to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs), or even on a dielectric substrate.
[0046] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to that available before replacement of components.
[0047] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.
[0048] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.
Claims
1. A method comprising: forming a first layer of a first material on a dielectric layer of the integrated circuit; forming a second layer of a second material on the first layer; patterning the second layer to expose the first layer; Etching the exposed first layer through the patterned second layer to form protrusion structures of the first layer and the second layer and undercut grooves located between adjacent protrusion structures in the protrusion structures, wherein the first layer of each protrusion structure has a first width, the second layer of each protrusion structure has a second width, and the second width is greater than the first width; as well as Carbon nanotubes are deposited into the undercut grooves between adjacent ones of the protrusion structures. 2 . The method of claim 1 , further comprising forming a graphitic carbon layer on the patterned second layer and before depositing the carbon nanotubes. The method of claim 1 , further comprising removing the protruding structure after depositing the carbon nanotubes. The method of claim 1 , further comprising forming a dielectric layer on the carbon nanotubes. The method of claim 1 , further comprising longitudinally aligning the carbon nanotubes with the protruding structures. The method of claim 1 , wherein the first material comprises aluminum or a dielectric material.
7. The method of claim 1, wherein the second material comprises at least one of: nickel, cobalt, copper, palladium, ruthenium, platinum, or a binary alloy thereof. The method of claim 1 , wherein the first width is smaller than a minimum line width of the patterned second layer.
9. A method comprising: forming a first layer of a first material on a dielectric layer of the integrated circuit; forming a second layer of a second material on the first layer; patterning the second layer to expose the first layer; etching the exposed first layer through the patterned second layer to form protrusion structures of the first layer and the second layer and grooves between adjacent protrusion structures among the protrusion structures; as well as forming a graphite carbon layer on at least a portion of the second layer of the protrusion structure; as well as Carbon nanotubes are deposited into the grooves between the adjacent ones of the protrusion structures. 10 . The method of claim 9 , wherein the first layer of each protruding structure has a first width, the second layer of each protruding structure has a second width, and the second width is greater than the first width. The method of claim 10 , wherein the first width is smaller than a minimum line width. 12 . The method of claim 9 , further comprising removing the protruding structure after depositing the carbon nanotubes.
13. The method of claim 9, further comprising forming a dielectric layer on the carbon nanotubes.
14. The method of claim 9, further comprising longitudinally aligning the carbon nanotubes with the protruding structures. The method of claim 9 , wherein the first material comprises aluminum or a dielectric material.
16. The method of claim 9, wherein the second material comprises at least one of nickel, cobalt, copper, palladium, ruthenium, platinum, or a binary alloy thereof.
17. A transistor comprising: Source and drain; a first array of carbon nanotubes having a first width, a first end connected to the source, and a second end connected to the drain; as well as a second array of carbon nanotubes adjacent to the first array of carbon nanotubes and spaced apart by a first spacing; The first width is greater than the first spacing.
18. The transistor of claim 17, wherein the first width is at least twice the first pitch.
19. The transistor of claim 17, further comprising a gate disposed below the first array of carbon nanotubes.
20. The transistor of claim 17, further comprising an insulating layer over the first and second arrays of carbon nanotubes.