Manufacturing method of semiconductor packaging structure, manufacturing method of semiconductor structure and semiconductor device

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor packaging structure, a manufacturing method of a semiconductor structure and a semiconductor device. The manufacturing method of the semiconductor packaging structure comprises the following steps: providing a wafer; forming a plurality of first stacks on the wafer; each first stack comprises a chip or a plurality of stacked chips; filling a gap between two adjacent first stacks with a first dielectric layer; the material of the first dielectric layer is different from that of the chip; forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks; each second stack comprises one chip or a plurality of stacked chips; removing the first dielectric layer; a gap between two adjacent first stacks and a gap between two adjacent second stacks are filled with an encapsulation layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor packaging structure, a method for manufacturing a semiconductor structure, and a semiconductor device. Background Art

[0002] With the development of large-scale integrated circuits, the characteristic size of circuits is constantly shrinking, and chips are developing in the three-dimensional (3D) direction and entering the post-Moore era, thus meeting the requirements of high integration, fast transmission speed, and low power consumption. It is necessary to improve the device yield and reliability of three-dimensional stacked chips. Summary of the invention

[0003] In view of this, embodiments of the present application provide a method for manufacturing a semiconductor packaging structure, a method for manufacturing a semiconductor structure, and a semiconductor device.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure, the manufacturing method comprising: providing a wafer; forming a plurality of first stacks on the wafer; each first stack includes a chip or a plurality of chips arranged in a stack; filling a first dielectric layer in a gap between two adjacent first stacks; the material of the first dielectric layer is different from the material of the chip; forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks; each second stack includes a chip or a plurality of chips arranged in a stack; removing the first dielectric layer; filling an encapsulation layer in a gap between two adjacent first stacks and in a gap between two adjacent second stacks.

[0005] In some embodiments, filling a first dielectric layer in a gap between two adjacent first stacks includes: forming a first dielectric material layer between the two adjacent first stacks and on the top surface of the first stack; removing the first dielectric material layer located on the top surface of the first stack, and the retained first dielectric material layer located in the gap between the two adjacent first stacks constitutes the first dielectric layer.

[0006] In some embodiments, forming a first dielectric material layer between two adjacent first stacks and on the top surface of the first stack includes: depositing the first dielectric material layer using a chemical vapor deposition process; the first dielectric material layer includes an air gap structure; or coating the first dielectric material layer using a spin coating process.

[0007] In some embodiments, removing the first dielectric layer includes: removing the first dielectric layer by an ashing process; wherein the material of the first dielectric layer is an organic compound; the organic compound includes carbon, polyimide or photopolymer.

[0008] In some embodiments, multiple first stacks are formed on a wafer, including: bonding the multiple first stacks to the wafer using a melt bonding process or a hybrid bonding process; and multiple second stacks corresponding to the multiple first stacks are formed on the multiple first stacks, including: bonding the multiple second stacks to the multiple first stacks using a melt bonding process or a hybrid bonding process.

[0009] In some embodiments, filling the gap between two adjacent first stacks and the gap between two adjacent second stacks with an encapsulation layer includes: using a mold to form a closed space around the first stack and the second stack; the closed space includes the gap between the two adjacent first stacks and the gap between the two adjacent second stacks; injecting an encapsulation material layer into the closed space; after the encapsulation material layer is formed, removing the mold to obtain the encapsulation layer.

[0010] In some embodiments, after forming multiple second stacks corresponding to the multiple first stacks on the multiple first stacks, the manufacturing method further includes: filling a second dielectric layer in the gap between two adjacent second stacks; the material of the second dielectric layer is different from the material of the chip; forming multiple third stacks corresponding to the multiple second stacks on the multiple second stacks; each third stack includes a chip or multiple chips arranged in a stack; removing the first dielectric layer, the manufacturing method further includes: removing the second dielectric layer; filling the gap between two adjacent first stacks and the gap between two adjacent second stacks with an encapsulation layer, the manufacturing method further includes: filling the gap between two adjacent third stacks with an encapsulation layer.

[0011] In some embodiments, before filling the first dielectric layer in the gap between two adjacent first stacks, the manufacturing method further includes: forming a first protective layer that at least covers the side walls of the first stack; the material of the first protective layer is different from the material of the first dielectric layer; before filling the second dielectric layer in the gap between two adjacent second stacks, the manufacturing method further includes: forming a second protective layer that at least covers the side walls of the second stack; the material of the second protective layer is different from the material of the first dielectric layer.

[0012] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the manufacturing method comprising: obtaining a semiconductor packaging structure according to any one of the manufacturing methods provided in the first aspect, cutting a wafer along the scribe lines of the wafer of the semiconductor packaging structure to obtain a plurality of semiconductor structures; each semiconductor structure comprises a plurality of chips stacked together.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a substrate; a semiconductor structure obtained according to the manufacturing method provided in the second aspect; and the semiconductor structure is located on the substrate and connected to the substrate.

[0014] In each embodiment of the present application, the first dielectric layer located in the gap between two adjacent first stacks connects the multiple first stacks into an integral structure, and the integral structure provides a stable carrier for forming a second stack corresponding to the first stack on the first stack to ensure the completion of the stacking between the second stack and the first stack; the material of the first dielectric layer is different from the material of the chip, and damage to the chip can be reduced or avoided when the first dielectric layer is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A One of the cross-sectional schematic diagrams showing the permanent filling of the gap between the chips;

[0016] Figure 1B The second cross-sectional schematic diagram of permanently filling the gap between chips;

[0017] Figure 1C A schematic cross-sectional view of temporarily filling the gap between chips;

[0018] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application;

[0019] FIG. 3A to FIG. 3F A schematic cross-sectional view of a manufacturing side of a semiconductor packaging structure provided by an embodiment of the present application;

[0020] FIG. 4A to FIG. 4D A schematic cross-sectional view of a manufacturing method of another semiconductor packaging structure provided by an embodiment of the present application;

[0021] Figure 5A and Figure 5B A schematic cross-sectional view of a manufacturing method of a semiconductor structure provided in an embodiment of the present application;

[0022] Figure 6 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will combine the implementation methods and drawings of this application to clearly and completely describe the technical solutions in the implementation methods of this application. The described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] The three-dimensional directions mainly include wafer to wafer (W2W), die to wafer (D2W), and die to die (D2D). In the D2W process, after the die is stacked, the gaps between the chips need to be filled to ensure the completion of the subsequent process. The methods for filling the gaps between the chips include permanent filling and temporary filling.

[0027] Figure 1A One of the cross-sectional views of permanently filling the gap between chips. Figure 1B The second cross-sectional diagram of permanently filling the gap between chips. Figure 1C Schematic diagram of a cross section showing temporary filling of the gap between chips.

[0028] refer to Figure 1A , one of the cases where the gap between chips is permanently filled, the chips 202 are stacked on the wafer 102, and the interconnect structure 302 is located between the chips 202 and the wafer 102, and the interconnect structure 302 is used to connect the circuits of the chips 202 ( Figure 1A Not shown) and the corresponding circuit in wafer 102 ( Figure 1A (not shown). After the chips 202 are stacked, a dielectric layer 401 may be deposited in the gaps between the chips 202 by a chemical vapor deposition (CVD) process. The material of the dielectric layer 401 may be silicon oxide.

[0029] refer to Figure 1B , the second case of permanently filling the gap between the chips, the chips 202 are stacked on the wafer 102, the interconnection structure 302 is located between the chips 202 and the wafer 102, and the interconnection structure 302 is used to connect the circuits of the chips 202 ( Figure 1B Not shown) and the corresponding circuit in wafer 102 ( Figure 1B(not shown). After the chips 202 are stacked, a molding layer 402 may be formed in the gaps between the chips 202 by a molding process. The material of the molding layer 402 may be a molding compound, a molding underfill, an epoxy molding compound (EMC), a resin, the like, or a combination thereof.

[0030] refer to Figure 1C , temporarily filling the gap between chips, the chip 202 is stacked on the wafer 102, the interconnect structure 302 is located between the chip 202 and the wafer 102, and the interconnect structure 302 is used to connect the circuit of the chip 202 ( Figure 1C Not shown) and the corresponding circuit in wafer 102 ( Figure 1C The sacrificial layer 403 may be deposited in the gaps between the chips 202 by chemical vapor deposition, and after subsequent processes (such as stacking another chip on top of the chip 202 to form a plurality of chip stacks on the wafer ( Figure 1C After that, it is necessary to remove the sacrificial layer 403 in the gap between the chips 202. Since the material of the sacrificial layer 403 (e.g., silicon oxide or silicon nitride) is the same as the material contained in the chip 202 (the material constituting the chip 202 includes silicon oxide or silicon nitride), the chip 202 may also be damaged while removing the sacrificial layer 403.

[0031] In the D2W process, it is necessary to take into account both the removal of the sacrificial layer and the protection of the chip. In view of this, the embodiments of the present application provide a method for manufacturing a semiconductor packaging structure, a semiconductor structure and a method for manufacturing the same.

[0032] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application.

[0033] In a first aspect, the present invention provides a method for manufacturing a semiconductor package structure, referring to Figure 2 , the manufacturing method comprises the following steps:

[0034] Step S101, providing a wafer;

[0035] Step S102, forming a plurality of first stacks on a wafer; each first stack includes one chip or a plurality of chips arranged in a stack;

[0036] Step S103, filling a first dielectric layer in the gap between two adjacent first stacks; the material of the first dielectric layer is different from that of the chip;

[0037] Step S104, forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks; each second stack includes one chip or a plurality of chips in a stacked arrangement;

[0038] Step S105, removing the first dielectric layer;

[0039] Step S106 : filling a gap between two adjacent first stacks and a gap between two adjacent second stacks with an encapsulation layer.

[0040] It should be understood that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0041] FIG. 3A to FIG. 3F A cross-sectional schematic diagram of a manufacturing method of a semiconductor packaging structure provided in an embodiment of the present application. FIG. 3A to FIG. 3F The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; FIG. 3A to FIG. 3F The steps shown in the figure can be adjusted in sequence according to actual needs.

[0042] Here and below, for the convenience of describing the embodiments of the present application, the first direction and the second direction are represented as two orthogonal directions parallel to the wafer plane; the third direction is a direction perpendicular to the wafer plane or the third direction is a direction parallel to the wafer thickness (or the direction in which the chip and the wafer are stacked). For example, the first direction can be represented as the X direction in the accompanying drawings; the second direction can be represented as the Y direction in the accompanying drawings; and the third direction can be represented as the Z direction in the accompanying drawings.

[0043] Combine the following Figure 2 and FIG. 3A to FIG. 3F The method for manufacturing the bonding structure provided in the embodiment of the present application is described in detail.

[0044] Step S101 is executed to provide a wafer.

[0045] refer to Figure 3A In some embodiments, the wafer 102 may be a carrier wafer or a device wafer.

[0046] Step S102 is executed to form a plurality of first stacks.

[0047] refer to Figure 3AIn some embodiments, forming a plurality of first stacks ST1 on the wafer 102 includes: bonding the plurality of first stacks ST1 and the wafer 102 using a fusion bonding process or a hybrid bonding process.

[0048] In some embodiments, a hybrid bonding process is used to sequentially bond the plurality of chips 202 onto the wafer 102 to form a first stack ST1 including the plurality of chips 202 .

[0049] In some embodiments, the bonding interface obtained by the hybrid bonding process ( Figure 3A The bonding interface (not shown) may include a bonding interface between metal layers and a bonding interface between dielectric layers. In an optional embodiment, the bonding interface obtained by the melt bonding process may include a bonding interface between metal layers and metal layers, a bonding interface between metal layers and dielectric layers, and a bonding interface between dielectric layers.

[0050] Although the number of first stacks ST1 formed on the wafer 102 is not three (eg, Figure 3A As shown), alternatively, one, two or more than three first stacks ST1 are formed on the wafer 102; each first stack ST1 includes two stacked chips 202 (such as Figure 3A As shown), alternatively, the first stack ST1 may be one chip 202 or three or more chips 202 stacked together.

[0051] refer to Figure 3AIn some embodiments, wafer 102 is a device wafer, and wafer 102 and chip 202 may include different types of semiconductor chips. For example, wafer 102 may include a logic chip, and chip 202 may include a memory chip. Alternatively, wafer 102 and chip 202 may include the same type of semiconductor chips. For example, both wafer 102 and chip 202 may include a logic chip or a memory chip. For example, a portion of wafer 102 may include a logic chip, and another portion of chip 202 may include a memory chip. Alternatively, chip 202 may include the same type of semiconductor chips. For example, wafer 102 is a logic chip or a memory chip. The logic chip may be, for example, a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application specific integrated circuit (ASIC). The memory chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or may be a non-volatile memory chip, such as a resistive random access memory (RRAM) chip. In other embodiments, the wafer 102 is a carrier wafer, and the chip 202 may include semiconductor chips of the same or different types.

[0052] refer to Figure 3A , the substrate of the device wafer ( Figure 3A The material of the substrate (not shown) may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0053] The substrate includes functional circuits ( Figure 3A Not shown), interconnect structure ( Figure 3ANot shown). Among them, the deposition process includes but is not limited to physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process and the like. The functional circuit may include a variety of active devices and passive devices (such as capacitors, resistors, inductors and the like) that meet the desired structural and functional requirements of the design. The functional circuit may include an NMOS device or a PMOS device. The interconnect structure includes an interconnect layer located in the insulating layer, and the interconnect layer connects the functional circuit. The material of the insulating layer (also referred to as the dielectric layer herein) includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The material of the interconnect layer includes but is not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof. The interconnect layer may be a conductive via and a conductive distribution layer connected to each other.

[0054] Step S103 is executed to form a first dielectric layer.

[0055] In some embodiments, filling a first dielectric layer in a gap between two adjacent first stacks comprises: referring to Figure 3B , forming a first dielectric material layer between two adjacent first stacks and on the top surface of the first stack; referring to Figure 3C , the first dielectric material layer located on the top surface of the first stack is removed, and the first dielectric material layer retained in the gap between two adjacent first stacks constitutes the first dielectric layer.

[0056] In some embodiments, a first dielectric material layer 204 is formed between two adjacent first stacks ST1 and on the top surface of the first stack ST1, including: Figure 3B , a first dielectric material layer 204 is deposited by a chemical vapor deposition (CVD) process; the first dielectric material layer 204 includes an air gap structure AG; or, a first dielectric material layer is coated by a spin-on coating (SoC) process (in this case Figure 3B not shown).

[0057] In some embodiments, the first dielectric material layer 204 may be an organic compound different from the material contained in the chip 202. For example, the material of the first dielectric layer may include carbon, (PolyImide, PI) or (PhotoResist, PR).

[0058] refer to Figure 3BIn some embodiments, a plasma enhanced chemical vapor deposition (PECVD) process is used to deposit carbon between two adjacent first stacks ST1 and on the top surface of the first stack ST1. The PECVD process parameters can be controlled (for example, the deposition rate is higher than a preset threshold) to achieve carbon early sealing, and an air gap structure AG is formed in the carbon. In this way, a first dielectric material layer 204 including the air gap structure AG is obtained, and the first dielectric material layer 204 includes carbon.

[0059] In some other embodiments, PI or PR is coated between two adjacent first stacks ST1 and on the top surface of the first stack ST1 (in this case, Figure 3B (not shown) In this way, a first dielectric material layer 204 is obtained, and the first dielectric material layer 204 includes PI or PR.

[0060] refer to Figure 3C The first dielectric material layer 204 (see Figure 3B ) is planarized to obtain a first dielectric layer 206 filling between two adjacent first stacks ST1. The material of the first dielectric layer 206 is inherited from the first dielectric material layer 204, for example, the material of the first dielectric layer 206 is carbon with an air gap structure AG.

[0061] refer to Figure 3D In some embodiments, a plurality of second stacks ST2 corresponding to the plurality of first stacks ST1 are formed on the plurality of first stacks ST1, including: bonding the plurality of second stacks ST2 and the plurality of first stacks ST1 by a fusion bonding process or a hybrid bonding process.

[0062] Compared with the situation where there is a gap between the chips 202 of the first stack ST1, by filling the first dielectric layer 206 in the gap between the chips 202 of the first stack ST1, the first dielectric layer 206 connects the two adjacent chips 202 into an integral structure, and the overall structure provides a stable carrier for forming a second stack ST2 corresponding to the first stack ST1 on the first stack ST1, so as to ensure the completion of the bonding between the second stack ST2 and the first stack ST1.

[0063] In some embodiments, a hybrid bonding process is used to sequentially bond the plurality of chips 202 onto the first stack ST1 to form a second stack ST2 including the plurality of chips 202 .

[0064] In some embodiments, the bonding interface obtained by the hybrid bonding process ( Figure 3D The bonding interface (not shown) may include a bonding interface between metal layers and a bonding interface between dielectric layers. In an optional embodiment, the bonding interface obtained by the melt bonding process may include a bonding interface between metal layers and metal layers, a bonding interface between metal layers and dielectric layers, and a bonding interface between dielectric layers.

[0065] Although the number of stacked chips 202 included in the second stack ST2 is shown as two (eg Figure 3D As shown), alternatively, the second stack ST2 may be one chip 202 or three or more chips 202 that are stacked.

[0066] refer to Figure 3D and Figure 3E In some embodiments, removing the first dielectric layer includes: removing the first dielectric layer 206 by an ashing process (refer to Figure 3D ); wherein the material of the first dielectric layer is an organic compound; the organic compound includes carbon, polyimide or photopolymer.

[0067] On the one hand, since the material of the first dielectric layer 206 (e.g., carbon, polyimide, or photopolymer) is different from the material of the chip 202 (e.g., the material constituting the chip 202 includes silicon oxide or silicon nitride), the damage to the chip 202 can be reduced or avoided when the first dielectric layer 206 is removed. On the other hand, since the first dielectric layer 206 has an air gap structure AG (refer to Figure 3D ), can be removed more easily or quickly, which can reduce or avoid damage to the chip 202 during the process of removing the first dielectric layer 206.

[0068] refer to Figure 3E and Figure 3F In some embodiments, the gap between two adjacent first stacks ST1 and the gap between two adjacent second stacks ST2 are filled with the encapsulation layer 208 (refer to Figure 3F ), including: using the model ( Figure 3E and Figure 3F (not shown) forms a closed space around the first stack ST1 and the second stack ST2 ( Figure 3E and Figure 3F The enclosed space includes a gap between two adjacent first stacks ST1 and a gap between two adjacent second stacks ST2; an encapsulation material layer ( Figure 3E and Figure 3F After the encapsulation material layer is formed, the mold is removed to obtain the encapsulation layer 208.

[0069] That is, the encapsulation material layer can be injected into the gap between the chips 202 through a molding process, and the encapsulation material layer is formed to obtain the encapsulation layer 208. The encapsulation material layer can be made of molding compound, molding underfill, epoxy molding material, resin, the like, or a combination thereof.

[0070] FIG. 4A to FIG. 4D A cross-sectional schematic diagram of another semiconductor packaging structure provided by an embodiment of the present application. It should be noted that: Figure 4A The semiconductor package structure shown is based on Figure 3D The semiconductor package structure shown is obtained as a basis.

[0071] In some embodiments, after forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks, the manufacturing method further comprises: referring to Figure 3D and Figure 4A , a second dielectric layer 207 is filled in the gap between two adjacent second stacks ST2; the material of the second dielectric layer 207 is different from that of the chip; Figure 4B , forming a plurality of third stacks ST3 corresponding to the plurality of second stacks ST2 on the plurality of second stacks ST2; each third stack ST3 includes one chip or a plurality of chips stacked; referring to Figure 4C , removing the first dielectric layer 206, the manufacturing method further includes: removing the second dielectric layer 207; referring to Figure 4D , filling the gap between two adjacent first stacks ST1 and the gap between two adjacent second stacks ST2 with an encapsulation layer, and the manufacturing method further includes: filling the gap between two adjacent third stacks ST3 with an encapsulation layer 208. The specific process of forming the second dielectric layer 207 can be referred to FIG. 3B to FIG. 3C The steps of obtaining the first dielectric layer 206 are shown in the figure, and will not be repeated here. The specific process of forming the third stack ST3, removing the second dielectric layer 207, and filling the encapsulation layer 208 between the gaps of two adjacent third stacks ST3 can be referred to respectively. Figure 3D , Figure 3E , Figure 3F The steps of obtaining the second stack ST2, removing the first dielectric layer 206, and forming the encapsulation layer 208 are shown for easy understanding and will not be described in detail here.

[0072] In some embodiments, the material of the second dielectric layer 207 may be the same as that of the first dielectric layer 206, for example, both include carbon. In an optional embodiment, the material of the second dielectric layer 207 may be different from that of the first dielectric layer 206, for example, the material of the second dielectric layer 207 includes PI or PR, and the material of the first dielectric layer 206 includes carbon. In some embodiments, both the second dielectric layer 207 and the first dielectric layer 206 have an air gap structure AG. In an optional embodiment, one of the second dielectric layer 207 and the first dielectric layer 206 has an air gap structure AG.

[0073] Understandably, Figure 4B The semiconductor package structure shown is in Figure 3D Based on the semiconductor package structure shown in the figure, FIG. 3B to FIG. 3D In some other embodiments, Figure 4B Based on the semiconductor package structure shown in FIG. 1 , a semiconductor package structure having a preset number of chip stacks is obtained by repeating a stacking cycle. Exemplarily, the preset number of chip stacks may be a chip stack having a total of 6 chips including a first stack ST1, a second stack ST2, and a third stack ST3, or a chip stack having more than 6 chips, for example, a chip stack having a total of 8 chips including four stacks ( Figure 4B (not shown) It should be noted that although Figure 4B 2 shows that the number of stacked chips 202 included in each stack (first stack ST1, second stack ST2 or third stack ST3) is two. Alternatively, each stack may be one chip or three or more chips in a stack. Figure 4B In the figure, it is shown that the number of each stack is the same, alternatively, the number of each stack can also be different. For example, the number of the first stack can be three, the number of the second stack can be two, and the number of the third stack can be one.

[0074] In the embodiments of the present application, on the one hand, the first dielectric layer is filled in the gap between the previous stacks (for example, the second stack ST2) completed on the wafer to connect the previous stacks completed into an integral structure, providing a stable carrier for bonding the next stack (for example, the third stack ST3), so as to facilitate bonding the next stack to the overall structure through a bonding process, and so on, which can ensure that a semiconductor packaging structure with a preset number of chip stacks (for example, a stack of 6 chips including the first stack ST1, the second stack ST2 and the third stack ST3) can be completed more stably / easily on the wafer; on the other hand, after completing the stacking of the preset number of chips, the first dielectric layer needs to be removed. Since the material of the first dielectric layer is different from the material contained in the chip, the damage to the chip can be reduced or avoided while removing the first dielectric layer. Furthermore, the first dielectric layer with an air gap structure can be removed more easily or quickly.

[0075] In some embodiments, before filling the first dielectric layer in the gap between two adjacent first stacks, the manufacturing method further includes: forming a first protection layer ( FIG. 3A to FIG. 3F The material of the first protective layer is different from the material of the first dielectric layer; before filling the second dielectric layer in the gap between two adjacent second stacks, the manufacturing method further includes: forming a second protective layer ( FIG. 3A to FIG. 3F The material of the second protection layer is different from that of the first dielectric layer.

[0076] The materials of the first protective layer and the second protective layer are different from the material of the first dielectric layer 206 (such as carbon, PI or PR), which can protect the chip 202 when removing the first dielectric layer 206, and can reduce or avoid damage to the chip 202 during the removal of the first dielectric layer 206.

[0077] Figure 5A and Figure 5B A schematic cross-sectional view of a semiconductor structure manufacturing method provided in an embodiment of the present application. It should be noted that: Figure 5A The semiconductor package structure shown is Figure 3F The semiconductor package structure shown can also be based on Figure 3F The semiconductor package structure shown is obtained.

[0078] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the manufacturing method comprising: obtaining a semiconductor packaging structure according to any one of the manufacturing methods provided in the first aspect, cutting a wafer 102 along a scribe line (SL) L1 and a scribe line L2 of the wafer of the semiconductor packaging structure to obtain a plurality of semiconductor structures 12; each semiconductor structure 12 comprises a plurality of chips 202 stacked together.

[0079] refer to Figure 5B In some example embodiments, the bonded wafer 102 and the plurality of chips 202 are cut along the scribe lines L1 and the scribe lines L2 to obtain a plurality of semiconductor structures 12. The wafer 102 includes a plurality of logic chips, and the chips in the chip stack (including a first stack ST1 and a second stack ST2) on a logic chip are memory chips. A logic chip and a chip stack on a logic chip may constitute a high bandwidth memory (HBM) DRAM. For example, the semiconductor structure 12 may include a logic chip and four memory chips stacked on a logic chip. The number of the plurality of chips 202 stacked in each semiconductor structure 12 may be one, two, three, or any number greater than four (e.g., six). In an optional embodiment, the wafer 102 may include a plurality of stacked logic chips.

[0080] Figure 6 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application. It should be noted that, compared with Figure 6 (a) shows the semiconductor structure, Figure 6 (b) The number of multiple chips in the semiconductor structure shown is different. Figure 6 The semiconductor structure shown in (b) can be understood as Figure 4D The scribe lines L1 and L2 of the wafer of the semiconductor package structure shown are obtained by cutting the wafer 102 .

[0081] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a substrate 14 ; a semiconductor structure 12 obtained according to the manufacturing method provided in the second aspect; the semiconductor structure 12 is located on the substrate 14 and connected to the substrate 14 .

[0082] The substrate 14 is used as a base of the semiconductor package structure, and may be a printed circuit board (PCB), a glass substrate, a ceramic substrate, or a board with wiring. The semiconductor structure 12 may be connected to the substrate 14 via micro-bumps 16 .

[0083] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0084] The above description is only a preferred implementation mode of the present application, and does not limit the protection scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Provide wafers; forming a plurality of first stacks on the wafer; Each of the first stacks includes one chip or a plurality of the chips arranged in a stack; Filling a first dielectric layer in a gap between two adjacent first stacks; The material of the first dielectric layer is different from the material of the chip; forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks; Each of the second stacks includes one chip or a plurality of chips arranged in a stack; removing the first dielectric layer; A gap between two adjacent first stacks and a gap between two adjacent second stacks are filled with an encapsulation layer.

2. The manufacturing method according to claim 1, characterized in that: Filling a first dielectric layer in a gap between two adjacent first stacks, comprising: forming a first dielectric material layer between two adjacent first stacks and on a top surface of the first stack; The first dielectric material layer located on the top surface of the first stack is removed, and the first dielectric material layer remaining in the gap between two adjacent first stacks constitutes the first dielectric layer.

3. The manufacturing method according to claim 2, characterized in that: A first dielectric material layer is formed between two adjacent first stacks and on a top surface of the first stack, comprising: The first dielectric material layer is deposited by chemical vapor deposition process; the first dielectric material layer includes an air gap structure; or, The first dielectric material layer is coated by a spin coating process.

4. The manufacturing method according to claim 1, characterized in that: Removing the first dielectric layer includes: The first dielectric layer is removed by an ashing process; wherein the material of the first dielectric layer is an organic compound; the organic compound includes carbon, polyimide or photopolymer.

5. The manufacturing method according to claim 1, characterized in that: Forming a plurality of first stacks on the wafer, comprising: bonding the plurality of first stacks to the wafer using a fusion bonding process or a hybrid bonding process; Forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks includes: bonding the plurality of second stacks to the plurality of first stacks by using a fusion bonding process or a hybrid bonding process.

6. The manufacturing method according to claim 1, characterized in that: Filling a gap between two adjacent first stacks and a gap between two adjacent second stacks with an encapsulation layer comprises: Using a mold to form a closed space around the first stack and the second stack; the closed space includes a gap between two adjacent first stacks and a gap between two adjacent second stacks; injecting a layer of encapsulating material into the enclosed space; After the encapsulation material layer is formed, the mold is removed to obtain the encapsulation layer.

7. The manufacturing method according to claim 1, characterized in that: After forming a plurality of second stacks corresponding to the plurality of first stacks on the plurality of first stacks, the manufacturing method further includes: Filling a second dielectric layer in a gap between two adjacent second stacks; the material of the second dielectric layer is different from that of the chip; forming a plurality of third stacks corresponding to the plurality of second stacks on the plurality of second stacks; each of the third stacks comprises one chip or a plurality of chips arranged in a stack; Removing the first dielectric layer, the manufacturing method further comprises: removing the second dielectric layer; The gap between two adjacent first stacks and the gap between two adjacent second stacks are filled with an encapsulation layer. The manufacturing method further includes: filling the gap between two adjacent third stacks with the encapsulation layer.

8. The manufacturing method according to claim 7, characterized in that: Before filling the first dielectric layer in the gap between two adjacent first stacks, the manufacturing method further includes: forming a first protective layer covering at least the sidewalls of the first stack; the material of the first protective layer is different from the material of the first dielectric layer; Before filling the second dielectric layer in the gap between two adjacent second stacks, the manufacturing method further includes: forming a second protection layer covering at least the sidewalls of the second stack; the material of the second protection layer is different from that of the first dielectric layer.

9. A method for manufacturing a semiconductor structure, characterized in that: include: The semiconductor package structure obtained by the manufacturing method according to any one of claims 1 to 8, The wafer of the semiconductor packaging structure is cut along the scribe lines of the wafer to obtain a plurality of the semiconductor structures; each of the semiconductor structures includes a plurality of chips stacked together.

10. A semiconductor device, characterized in that: include: substrate; A semiconductor structure obtained by the manufacturing method according to claim 9; the semiconductor structure is located on the substrate and connected to the substrate.

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