Method of binding dies for panel level processing

Abstract

The present disclosure provides a method of bonding dies for panel level processing. The PLP accurately binds the die to the die binding area of the alignment panel. High precision is achieved by providing a die bonding area with a local alignment mark. Precise binding of dies on an alignment carrier results in a reconstructed wafer with precise die positioning. The dies of the reconstructed wafer may be scanned by a die position check (DLC) scan based on die sub-blocks, thereby achieving high throughput of DLC. The DLC scans to generate a DLC file, wherein the DLC file comprises coordinate points of sub-blocks of the reconstructed wafer. In addition, a laser direct imaging (LDI) file may be generated using the sub-block circuit file aligned with the DLC file. The use of sub-block circuit files facilitates high throughput of generating LDI files with high precision since the reconstituted wafer is formed using an alignment carrier with local alignment marks.

Description

[0001] This application is a divisional application of a patent application with an application date of October 8, 2021, application number 202111178841.8, and invention name “Precise Reconstruction of Panel-Level Packaging”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of SG Provisional Application No. 10202009834T, filed on October 2, 2020, and is a continuation-in-part of pending U.S. Patent Application No. 16 / 814,861, filed on March 10, 2020, and U.S. Patent Application No. 16 / 814,861 claims the benefit of SG Provisional Application No. 10201902757X, filed on March 27, 2019, all of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0004] The present application relates to accurate reconstruction of panel-level packaging devices. In particular, the present application relates to the bonding of bare dies on a panel for high-precision panel-level packaging. Background Art

[0005] Panel-level packaging (PLP) of devices has attracted great interest in recent years. This is because a larger volume of dies can be packaged in parallel than with traditional wafer-level or substrate-level packaging technologies. PLP involves connecting or bonding individual dies on a large panel or carrier for die bonding. For example, the dies are arranged in a matrix on a panel or carrier, with rows and columns of dies. A molding compound wraps the dies, forming a mold panel or reconstituted wafer. Depending on its size, a carrier can accommodate significantly more dies than on a wafer, for example, 3 to 5 times or more dies than on a wafer. This increases packaging yield and reduces costs. After the dies are packaged, the reconstituted wafer is sawn or diced to separate the dies.

[0006] However, conventional techniques for forming reconstructed wafers result in inaccurate positioning of the die within the reconstructed wafer. The inaccuracy may be due, for example, to inaccurate alignment of the die to the carrier. In addition, the bonded die may move during processing, such as molding, further exacerbating inaccuracies in positioning the die within the reconstructed wafer. Due to the misalignment of the die in the reconstructed wafer, downstream processing, such as forming traces to complete the packaging process and sawing the reconstructed wafer to separate it into individual packages, may be misaligned. This misalignment of downstream processes results in reduced yields.

[0007] Therefore, based on the foregoing discussion, it is desirable to provide accurate positioning of dies in a reconstituted wafer to increase yield. Summary of the invention

[0008] Embodiments of the present application generally relate to panel-level packaging devices. In particular, the present application relates to precise reconstruction for panel-level packaging.

[0009] In one embodiment, a method for die location check (DLC) includes: providing a reconstructed wafer having a die block encapsulated in a molding compound. The die block includes a plurality of dies arranged in rows and columns to form a die matrix of the block. The plurality of dies include alignment dies and active dies. The method also includes scanning the reconstructed wafer. The scanning includes scanning the die block. The method also includes processing scan information of the die block. The processing includes identifying the position of the alignment die of the die block, assigning one of the alignment dies of the die block as the origin of a Cartesian coordinate system of the die block, wherein scanning the die block includes scanning the die block in a scanning manner of one sub-block at a time, wherein each sub-die block includes dies arranged in a sub-block matrix, the sub-block matrix includes fewer dies than the matrix of the die block, and assigning coordinate points to the sub-blocks of the die in the Cartesian coordinate system.

[0010] In another embodiment, a method for bonding die for panel level processing includes providing an alignment panel having a bonding surface, the bonding surface including a die bonding area for bonding a die thereto. The bonding surface includes a local alignment mark. The bonding surface includes a panel adhesive film for facilitating bonding the die to the die bonding area. The method also includes bonding a selected die to the selected die bonding area, including aligning the selected die with the selected die bonding area using the local alignment mark of the selected die bonding area, and bonding the selected die to the selected die bonding area when the selected die is aligned with the selected die bonding area.

[0011] These and other advantages and features of the embodiments disclosed herein will become apparent by reference to the following description and drawings.In addition, it should be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and form a part of the specification, wherein like numerals represent like parts, illustrate preferred embodiments of the application and, together with the description, serve to explain the principles of the various embodiments of the application.

[0013] Figure 1 A simplified top view of a semiconductor wafer is shown;

[0014] Figure 2a-2d An embodiment of processing a processed wafer is shown;

[0015] Figure 3a shows a simplified top view of an alignment panel in one embodiment;

[0016] Figure 3b shows a simplified top view of a portion of another embodiment of an alignment panel;

[0017] Figures 4a-4d An embodiment of a process for preparing an alignment panel is shown;

[0018] Figure 5a-5b An embodiment of matching a pattern of a CAD file to a die and an alignment panel is shown;

[0019] Figure 5c is a simplified illustration of an embodiment of aligning a die to an alignment panel for bonding;

[0020] Figure 6a-6e A simplified cross-sectional view illustrating an embodiment of a process for forming a reconstituted wafer and preparing the reconstituted wafer for further processing;

[0021] Figure 7a-7c An image depicting an embodiment of a die location check (DLC) process on a reconstituted wafer is shown;

[0022] Figure 7d Images showing different arrangements of sub-blocks;

[0023] Figure 8a-8c An embodiment of generating a laser direct imaging file for forming traces on the reconstructed wafer is shown;

[0024] Figure 8d Different arrangements of sub-block circuit files are shown;

[0025] Figures 9a-9f shows a simplified cross-sectional view illustrating an embodiment of a process for forming traces on a reconstituted wafer;

[0026] Figure 10a-10b A simplified top view showing an embodiment of a package having traces; and

[0027] Figure 11a-11b An embodiment of generating saw wire fiducials for cutting a reconstituted wafer is shown. DETAILED DESCRIPTION

[0028] Embodiments generally relate to panel-level packaged devices, such as panel-level packaged semiconductor devices or integrated circuits (ICs). In particular, the present application relates to high-precision bonding of dies or devices on a panel for panel-level packaging.

[0029] Figure 1A simplified top view of a semiconductor wafer 100 is shown. The wafer may be a lightly doped p-type silicon wafer. Other types of wafers may also be used. For example, the wafer may be a silicon carbide (SiC) wafer, a gallium nitride (GaN) wafer, a gallium arsenide (GaAs) wafer, or an indium phosphide (InP) wafer. Devices 110 are formed in parallel on the active surface of the wafer 100. The active surface may be the upper surface of the wafer 100. The passive surface may be the lower surface of the wafer.

[0030] The devices 110 are arranged in rows along a first direction (x) and in columns along a second direction (y). After the wafer is processed, the wafer is cut along a cutting line or saw line 180 using a wafer saw. For example, the wafer is cut along a first cutting line 1801 in the x direction and a second cutting line 1802 in the y direction to separate the devices 110 of the wafer 100 into individual devices or dies 110.

[0031] Figure 2a-2d A simplified cross-sectional view of a process for processing a processed wafer 200 is shown. Figure 2a , a cross-sectional view of a processed wafer 200 is shown. The processed wafer 200 includes a top or active wafer surface 201 and a bottom or passive wafer surface 202. By way of example, to simplify the description, the cross-sectional view of the processed wafer 200 includes three dies 210. It should be understood that the cross-sectional view may include other numbers of dies 210 and other elements not shown, such as die portions at the edge of the wafer. The processed wafer 200 may be an imported processed wafer from an external supplier. For example, a packaging supplier may receive a processed wafer 200 from an external supplier such as a wafer handling plant.

[0032] In one embodiment, a bare wafer is processed to form a processed wafer. For example, processing includes forming circuit components or elements of a bare die 210 on the surface of the wafer. The circuit components may include active and passive circuit components. Active components may include, for example, transistors, diodes, and triodes, while passive components include voltage elements, capacitors, resistors, and inductors. Other types of active and passive components may also be included. The circuit components may be formed using a series of processes, such as doping (e.g., implantation or diffusion), deposition (e.g., oxidation, chemical vapor deposition (CVD), electroplating, and sputtering), and patterning (e.g., photolithography and etching). Other techniques may also be used to form the circuit components.

[0033] A BEOL dielectric having multiple interconnect levels with wires coupled to via contacts is formed on a bare die substrate. For example, the BEOL dielectric covers the bare die substrate surface with circuit components. In one embodiment, the BEOL dielectric includes a low-k dielectric or dielectric layer that isolates wires of different interconnect levels. The low-k dielectric layer may also include an ultra-low-k dielectric layer. The low-k dielectric or dielectric layer may be collectively referred to as a low-k dielectric or dielectric layer and an ultra-low-k dielectric or dielectric layer. Other types of dielectric layers may also be useful. The circuit components and the BEOL dielectric are simply shown as a portion of a processing wafer 200. The top of the BEOL may be an active processing wafer surface 201.

[0034] The top of the BEOL dielectric may include a pad layer. In one embodiment, the pad layer includes a die bond pad 240. The die bond pad 240 may be, for example, an aluminum (Al) die bond pad 240. Other types of die bond pads 240, such as copper (Cu), nickel (Ni), palladium (Pd), gold (Au), chromium (Cr), or combinations or alloys thereof, including Al-Cu, may also be useful.

[0035] The die bonding pad 240 may be covered by a passivation layer 242. The passivation layer may be a passivation stack having multiple dielectric layers. For example, the passivation stack may include a combination of dielectric layers, such as silicon oxide and silicon nitride layers. Other types of dielectric layers may also be useful.

[0036] The passivation layer 242 may include a pad opening 244 to expose the die bonding pad 240. As shown, the pad opening 244 is smaller than the die bonding pad. For example, the top surface of the passivation layer 242 is located above the top surface of the die bonding pad 240, and the pad opening 244 is smaller than the die bonding pad 240. As shown, the passivation layer 242 covers the edge portion of the die bonding pad 240. For example, the pad opening 244 can be formed by an anisotropic etch such as reactive ion etching (RIE). Other types of etching can also be used to form the pad opening. The exposed portion of the top of the BEOL dielectric, the passivation layer 242, and the bonding pad 240 can be collectively referred to as the active processing wafer surface 201. In some cases, the active processing wafer surface 201 can include the top of the BEOL dielectric and the die pad 240, but without the passivation layer.

[0037] exist Figure 2bIn one embodiment, further processing of the processed wafer 200 includes forming a buffer layer 260 on the active processing wafer surface 201. For example, the buffer layer 260 is a wafer-level buffer layer 260 formed on the active processing wafer surface 201. The wafer-level buffer layer 260 is a dielectric buffer layer. The buffer layer 260 may include, for example, epoxy resin, polyimide, polybenzoxazole or other types of dielectric materials. The thickness of the buffer layer 260 may be about 10-100um, about 15-100um, about 20-100um, about 25-100um, about 45-100um or about 60-100um. Other thicknesses of the buffer layer 260 may also be useful.

[0038] In a preferred embodiment, the buffer layer 260 prevents or reduces the chipping or cracking of the BEOL dielectric from the wafer singulation process, such as dicing to separate the wafer 200 into individual dies 210. The buffer layer 260 can be tuned to have or have a Young's modulus and a fracture strength to reduce or prevent the chipping or cracking of the BEOL dielectric during the wafer singulation process. In one embodiment, the Young's modulus of the buffer layer 260 is about 10,000-25,000 MPa, about 14,000-25,000 MPa, about 15,000-25,000 MPa, about 16,000-25,000 MPa, about 15,000-25,000 MPa, or about 20,000-25,000 MPa. As for the fracture strength, it may be about 45-150 MPa, about 70-150 MPa, about 70-120 MPa, about 70-105 MPa, about 80-120 MPa, or about 90-120 MPa. The coefficient of thermal expansion (CTE) of the buffer layer 260 may be, for example, about 6-20 ppm / K. The buffer layer may have temperature stability in the range of -65-+300°C.

[0039] In one embodiment, the buffer layer 260 is a composite buffer layer 260, which includes a base buffer layer with filler particles. In one embodiment, the base buffer layer includes an organic polymer matrix material. For example, the base buffer layer may include a thermosetting plastic or a thermoplastic plastic, such as polyimide, epoxy resin, and other types of polymers. In one embodiment, the base buffer layer includes a resin, such as an epoxy resin or a cyanate ester. Preferably, the base buffer layer is a low viscosity resin, such as a biphenyl epoxy resin. Of course, other types of base buffer layers may also be useful.

[0040] In one embodiment, the filler is inorganic-based. For example, the filler can be silicon dioxide (SiO2), amorphous aluminum oxide (α-Al2O3) or a combination thereof. Other types of fillers are also possible. For example, the filler can be an organic-based or inorganic-based or a combination of organic-based fillers. For example, the filler can be a spherical filler. The filler of the composite buffer layer 260 is a filler of uneven size with a diameter ranging from about 0.5-12um or about 0.5-10um. Fillers of other sizes or shaped fillers may also be useful.

[0041] Various techniques may be used to form the buffer layer on the active process wafer surface 201. For example, the buffer layer 260 may be formed by spin coating or lamination. Other techniques, such as stitch coating, may also be useful. The technique used to form the buffer layer 260 may depend on the type of buffer layer.

[0042] refer to Figure 2c , the buffer layer 260 on the active processing wafer surface 201 of the processing wafer 201 is patterned to form a through hole opening 262. The through hole opening 262 exposes the die bonding pad 240. In one embodiment, the through hole opening 262 is formed by laser etching. The through hole opening 262 can also be formed by other processes. As shown in the figure, the through hole opening 262 can have an inclined or tapered sidewall profile. The sidewalls of the through hole opening 262 can also be non-inclined. In addition, as shown in the figure, the bottom of the through hole opening 262 is smaller than the die bonding pad 240. Preferably, the bottom of the through hole opening 262 is located approximately or as close as possible to the center portion of the die bonding pad 240.

[0043] like Figure 2d As shown, after forming the via openings 262 in the buffer layer 260 , the processed wafer 200 is divided into individual dies 210 . For example, the processed wafer 200 is sawn at the dicing lines to divide the wafer 200 into the individual dies 210 .

[0044] Figure 3a A simplified top view of an embodiment of an alignment carrier or panel 304 used in a PLP is shown. For example, the top view may be a top surface 305 of the alignment carrier on which the die is bonded for the PLP. For example, the top surface 305 may be referred to as the bonding surface of the alignment panel 304. The opposite surface of the top surface 305 is the bottom surface 306 of the alignment carrier 304. The bottom surface 306 may be referred to as the non-bonding surface of the alignment panel 304. As shown, the alignment panel 304 is rectangular. The alignment panel 304 may be formed into other shapes.

[0045] In a preferred embodiment, the alignment panel 304 is formed of a material having a low coefficient of expansion (CTE) to minimize linear changes during temperature changes. For example, the alignment panel 304 can be formed of a material having a CTE equal to or lower than 8ppm / K. In addition, the material should be strong enough to withstand handling during the bonding process. In addition, the material should preferably be magnetic so that the alignment panel 304 can be firmly held during the grinding process as part of the entire bonding process. For example, low CTE materials can include alloy 42 (CTE3-4.5ppm / K) and alloy 46 (CTE7-8ppm / K). Other types of low CTE materials can also be used to form the alignment panel 304. It is also useful to form the alignment panel 304 using other materials and materials with other CTEs (including materials with CTEs higher than 8ppm / K). The size of the alignment panel 304 can be approximately 700mm×700mm. It may also be useful to provide alignment panels with other sizes (larger or smaller).

[0046] In one embodiment, the bonding surface 305 of the alignment panel 304 includes an active area 314 having die bonding areas 330. The die bonding areas 330 may be arranged in a matrix format with rows and columns of the die bonding areas 330 in a first (row) and second (column) direction. For example, the row direction is the x-direction and the column direction is the y-direction.

[0047] As shown, the die bonding areas 330 in the active area 314 are arranged as a block or a matrix. The spacing of the die bonding areas in a block is the same. For example, the spacing (row spacing) of adjacent die bonding areas 330 in the row direction of the block is the same; the spacing (column spacing) of adjacent die bonding areas 330 in the column direction of the block is the same. The row spacing and column spacing can be the same or different from each other.

[0048] In some embodiments, the die binding areas 330 of the alignment panel 304 can be arranged in multiple blocks. For example, the die binding areas 330 of the alignment panel 304 can be arranged in 4 separate blocks of the die binding areas 330, such as a 2x2 block matrix or arrangement. Other numbers of blocks or arrangements of blocks may also be useful. For example, the alignment panel 304 may include an odd number of blocks arranged in a row or column format. For example, the blocks are physically separated by block spacing. For example, adjacent blocks are separated by block spacing. The block spacing is greater than the die spacing within the block (the spacing between rows and columns of dies). In the case where the alignment panel includes only one block, a block can be used to refer to all die binding areas of the alignment panel, or to all die binding areas 330 within a block of an alignment panel having multiple blocks.

[0049] The die is bonded to the die bonding area 330 of the block. In one embodiment, the die bonding area 330 includes a local die alignment mark or reference point 150. The local die alignment mark helps to align the die to bond them to the die attachment area 338 of the die bonding area 330. For example, each die bonding area 330 includes its own local die alignment mark 350, which is used to align and bond one or more dies to the die attachment area 338. The die attachment area 338 can be, for example, a die or a contour of a die when it is bonded thereto. As shown, the local die alignment mark 350 has a circular shape. The local die alignment mark 350 can also be of other shapes. Preferably, all local die alignment marks 350 have the same shape. However, it is understood that not all local die alignment marks 350 need to have the same shape.

[0050] In one embodiment, the local die alignment marks 350 are preferably located outside the die attach area 338. For example, the local die alignment marks 350, as shown, surround the die attach area 338. In some cases, the local die alignment marks 350 are set within the die attach area 338. In this case, the local die alignment marks 350 are not visible after the die is bonded because the die will cover them. In other embodiments, the local die alignment marks 350 can be set inside and outside the die attach area 338. Providing the local die alignment marks 350 outside the die attach area 338 facilitates post-welding inspection because they are visible after the die is welded.

[0051] The die bonding area 330 can accommodate a single die or multiple die, such as a multi-chip module (MCM). For example, each die bonding area 330 can include multiple die attachment areas. In the case of an MCM, providing local die alignment marks outside the die attachment areas of multiple die advantageously enables the local alignment marks 350 to be used together to bond multiple die to the die bonding area 330. If the local die alignment mark 350 is set in the die attachment area of ​​one of the dies, it may be necessary to provide additional local die alignment marks 350 for bonding other dies of the MCM to their respective die attachment areas within the die bonding area 330.

[0052] In one embodiment, the local die alignment mark 350 can be detected by a co-linear vision camera for alignment. Such a camera can be described in, for example, U.S. Patent No. 16 / 814,961, which is incorporated herein by reference for all purposes. The local die alignment mark 350 can be formed on the die bonding area 330 of the alignment panel 304 using, for example, laser drilling. Other techniques for forming the local die alignment mark 350 may also be useful. Preferably, the local die alignment mark 350 is a shallow mark that is easy to remove by grinding to recycle the alignment panel 304. For example, when a die is no longer produced, the local die alignment mark 350 can be removed and a new die bond for another or different type of die is formed.

[0053] Compared with the conventional method of calculating the die bonding position based on the global alignment mark, providing the local die alignment mark 350 for each die bonding area 330 improves the position accuracy of the die bonding. In addition, by providing the local die alignment mark 350, the influence of panel deformation or other positioning errors is minimized, and the positioning accuracy of the die on the alignment panel 304 is improved, thereby improving the production yield and scalability.

[0054] The die bonding area 330 of the block includes an alignment die bonding area 336 and an active die bonding area 331. The active die bonding area 331 accommodates an active die. For example, the active die is a common die sold for use. The alignment die bonding area 336 is similar to the active die bonding area 331, except that they are designated for alignment die. For example, the alignment die bonding area 336 accommodates an alignment die for alignment purposes. The alignment die can be a common die or an active die, such as a die bonded in the active die bonding area 331. For example, the alignment die can be an active die for alignment purposes.

[0055] Alternatively, the alignment die may be used specifically for alignment purposes. Providing specific alignment die may be advantageous because they can be easily distinguished from ordinary die or active die. In this case, the alignment die cannot be used for normal use. Preferably, the active surface of the alignment die is treated with features that are easily detected by the alignment camera. These features of the alignment die create contrast in the alignment image, making it easy to detect or distinguish from the active die.

[0056] In one embodiment, the block includes at least 2 alignment die bonding areas 336. It may also be useful to provide the block with other numbers of alignment die bonding areas 336. As shown, the block includes 4 alignment die bonding areas 336. 1-4The number of align die bonding areas may depend on, for example, the application. Align die bonding areas 336 are located in the block to facilitate determining the die location of the die in the block of the reconstituted wafer for further processing by a die location check (DLC) process.

[0057] In one embodiment, the die bonding area 336 is aligned 1-4 The die bonding area is located at the corner of the block. For example, the die bonding area 336 is aligned 1-4 The first and last die bonding areas 330 correspond to the first and last rows and the first and last columns of the block. It may also be useful to provide alignment die bonding areas 336 at other locations of the block. In the case where the alignment panel 304 includes multiple blocks, each block preferably has the same arrangement of alignment die bonding areas 336. However, it is understood that different blocks of the alignment panel 304 can have different arrangements of alignment die bonding areas 336, including the number and location of the alignment die bonding areas 336.

[0058] Figure 3b A simplified top view of a portion of another embodiment of an alignment panel 304 is shown. As shown, adjacent die bonding areas 330 of the alignment panel 304 abut each other. This arrangement enables local alignment marks 350 to be shared by adjacent die bonding areas 330. Sharing local alignment marks 350 between adjacent die bonding areas 330 reduces the footprint of the die bonding areas, allowing the alignment panel 304 to fit more die bonding areas 330.

[0059] As described above, the alignment panel is formed of a metal material having local die alignment marks. Using a metal material is advantageous because it allows the alignment panel to be securely held in place for processing using a magnetic table. For example, a magnetic table can be used to securely hold the alignment panel in place for grinding molding compounds.

[0060] In other embodiments, the alignment panel 304 may be formed of glass or other types of transparent materials. The local die alignment mark 350 may be formed on the transparent alignment panel 304. In other cases, the local die alignment mark 350 may be independent of the transparent alignment panel 304. For example, the local die alignment mark 350 may be formed on a separate marking sheet, such as paper or resin, and may be attached to the bottom or inactive surface of the transparent alignment panel 304. The use of an independent local die alignment mark 350 eliminates the need for a marking process on the alignment panel 304, thereby significantly reducing manufacturing costs.

[0061] Light from the camera module of the die bonder can penetrate the transparent alignment panel 304 to detect the local die alignment mark 350 on the mark sheet. The use of independent local die alignment mark 350 can be easily implemented, eliminating the need for a marking process on the alignment panel 304. In addition, providing the local die alignment mark 350 independent of the transparent alignment panel is advantageous because it avoids the need to mass-produce glass alignment panels with local die alignment marks 350. Since the glass alignment panel 304 is fragile and the marking process is expensive, this can significantly reduce costs.

[0062] Figures 4a-4d An example of a process for preparing an alignment panel is shown. Figure 4a , a bare alignment panel 404 is provided. The alignment panel 404 includes an opposing top surface 405 and a bottom surface 406. The alignment panel 404 can be formed of a low CTE material, such as Alloy 42 or Alloy 46. Other types of materials can also be used to form the alignment panel 404. For a 700mmX700mm panel, the thickness of the alignment panel 404 can be about 2mm. The alignment panel can also be other thicknesses. For example, the thickness can depend on the size and material of the alignment panel 404.

[0063] exist Figure 4b In the embodiment of the present invention, the top or binding surface 405 of the alignment panel 404 is prepared. In one embodiment, the panel preparation includes grinding the top surface 405 to produce a thickness parallel to the alignment panel 404. The grinding process ensures the flatness of the alignment panel 404 and produces a scratch-free top or active surface 405. In some embodiments, the bottom or non-binding surface 406 can be similarly ground to ensure that it is free of dents and burrs. In some embodiments, the binding surface 405 of the alignment panel 404 can be hardened to prevent scratches or panel discoloration.

[0064] Reference Figure 4c , local die alignment marks 450 are formed on the alignment panel 404. The local die alignment marks 450 can be formed based on the CAD design file of the alignment panel. In one embodiment, the local die alignment marks 450 are formed by laser drilling. The local die alignment marks 450 can also be formed by other techniques. For example, mechanical drilling, etching or other material removal processes can be used to form the local die alignment marks 450. In a preferred embodiment, the local die alignment marks 450 are formed using a high-precision system to ensure accurate hole-to-hole throwing. The spacing of the holes to the holes depends on the die size and layout of the alignment panel 404, for example. Preferably, the local die alignment marks 450 are shallow so that they can be recycled by, for example, grinding, removing them. The local die alignment marks 450 can be about 25um deep. The local die alignment marks 450 can also be other depths.

[0065] like Figure 4d As shown, tape 422 is applied to the active surface 405 of alignment panel 404. For example, tape 422 can be referred to as panel tape. Panel tape 422 is applied to the active surface 405 of alignment panel 405 to prepare for die bonding. For example, panel tape 422 covers active surface 405. In one embodiment, panel tape 422 is a thermosensitive or thermal release tape. Other types of panel tapes can also be used to facilitate die bonding. Panel tape 422 should be transparent enough to enable the camera of the bonding tool to detect local die alignment marks 450. For example, panel tape 422 can be transparent or translucent so that the light of the camera can penetrate panel tape 422 and detect local die alignment marks 450. In addition, the viscosity of panel tape 422 should be strong enough to keep the die in place once the die is aligned and placed thereon by the bonding tool. After using panel tape 422, alignment carrier 404 is ready for die bonding.

[0066] Figure 5a-5b An embodiment of matching the pattern of an AutoCAD (CAD) file to a die and an alignment panel is shown. Figure 5a , shows an image of a die 510 and an image of a die bonding area 530 of an alignment panel captured, for example, by an alignment module of a bonding tool.

[0067] With respect to die 510, the active surface includes die features 512. The die features 512 of the active surface of die 510 may be through-hole openings in a buffer layer. A corresponding CAD die file 513 of the die is shown. For example, the CAD die file 513 contains information related to die 510. For example, the CAD die file 513 includes CAD die features 514 corresponding to the die features 512 on die 510. The information contained in the CAD die file is based on green data. For example, green data refers to design data. In one embodiment, the CAD die file includes the coordinate positions of the die features. The coordinate positions of the die features may be the center points of the die features. For example, the file may be a text file including the coordinate positions corresponding to the centers of the die features.

[0068] In some cases, there may be different files containing die feature information. For example, there may be a design file containing the shape of the feature and a coordinate file containing the coordinates of the die features within the die. For example, the coordinate file may be a text file containing the coordinates corresponding to the center points of the die features. The coordinate file may be referred to as a CAD die file.

[0069] In one embodiment, CAD die reference points 516 are defined. Preferably, at least 2 CAD die reference points 516 are defined. As shown, CAD die reference points 516 include 2 die reference points. For example, the first and second CAD die reference points are vertically aligned. The CAD die reference points can also be arranged or numbered in other ways. CAD die reference points 516 are used for alignment purposes. By using 2 or more CAD die reference points 516, translation and angle (rotation) alignment can be achieved. The position of CAD die reference points 516 can be arbitrarily selected by, for example, a designer of die 510. The position of CAD die reference points 516 can be identified based on their relative position to CAD die features 514, including the outline or corners of the die.

[0070] As for the die bonding area 530, it includes a local die alignment mark 550. A corresponding CAD panel file 533 for aligning the die bonding area 530 on the panel is shown. For example, the CAD panel file 533 is a CAD file for a panel target, which is the die bonding area 530. For example, the CAD panel file 533 contains information related to the die bonding area 530. The CAD panel file 533 includes a CAD panel feature 537. The CAD panel feature 537 is located within the CAD die bonding area, which corresponds to the location of the local die alignment mark 550 of the die bonding area 530.

[0071] Similarly, there may be different files containing panel feature information. For example, there may be a design file containing feature shapes and a coordinate file containing the coordinates of panel features within the die bonding area. The coordinate file is, for example, a text file containing coordinates corresponding to the center points of panel features, such as local alignment marks 550. The coordinate file may be referred to as a CAD panel file.

[0072] In one embodiment, CAD panel reference points 539 are defined. Preferably, at least 2 CAD panel reference points 539 are defined. CAD panel reference points 539 are used for alignment purposes. As shown, the CAD panel file includes 2 CAD panel reference points 539. By using 2 or more CAD panel reference points 516, translation and angle (rotation) alignment can be achieved. In one embodiment, the position of the CAD panel reference point 539 is selected to correspond to the position of the CAD die reference point used for die bonding alignment. The position of the CAD panel reference point 539 can be identified based on their relative position to the CAD panel feature 537.

[0073] exist Figure 5b, CAD die file 513 is the best match for die 510. For example, CAD die feature 514 is the best match for die feature 512 of die 510. This results in die 510 having virtual die reference point 516 positioned on die 510 based on CAD die file 513. Similarly, CAD panel file 533 is the best match for die bonding area 530 on the alignment panel. For example, CAD panel feature 537 is the best match for local die alignment mark 550 on the alignment panel. This results in die bonding area 530 having virtual panel reference point 539. Virtual panel reference point 539 is positioned on die bonding area 530 of the alignment panel based on CAD panel file 533. When virtual die reference point 516 is aligned with virtual panel reference point 539, die 510 is aligned with die bonding area 530.

[0074] Figure 5c A simplified diagram of a die binder aligning a die for binding to an alignment carrier is shown. As shown, the alignment carrier 504 is mounted on a workbench of a die binder (not shown). The bonding head (not shown) of the die binder picks up the die for binding to the alignment carrier 504. The camera 596 of the die binder extends to a position for aligning the die 510 to the alignment carrier. In one embodiment, the camera 596 is a co-linear upward and downward camera. For example, the camera 596 looks up and images the active surface of the die 510 and looks down and images the alignment carrier 504 under the same line of sight. The camera images of the die and the alignment carrier are shown. For example, the camera image of the die 510 shows the die features 510, while the camera image of the alignment carrier shows the die bonding area 530 with the local die alignment mark 530.

[0075] The die binder includes a memory that stores a CAD die file and a CAD panel file. The CAD die file is best suited to the image of the die 510, while the CAD panel file is best suited to the die binding area 530 (such as the panel) aligned to the panel. Figure 5b In one embodiment, the die bonder's bonding head positions the die over the alignment panel so that the CAD die reference points are aligned with the CAD panel reference points, indicating that the die 510 is aligned with the die bonding area 530 on the alignment panel 504. When the die 520 is aligned with the die bonding area 530, the camera 596 retracts, allowing the bonding head to move vertically downward to bond the die 510 to the die bonding area 530.

[0076] In one embodiment, a block of the alignment panel 504 is bound to a die on a die binding area in a die-at-a-time manner. For example, a first die is bound to a first die binding area of ​​the block of the alignment panel 504. The first die and the first die binding area may be referred to as a selected die and a selected die binding area. Binding the selected die includes a die binder picking up a selected die, aligning the selected die to the selected die binding area, and binding the selected die to the selected die binding area. After the selected die is bound to the selected die binding area, the die binder determines whether there are other die binding areas in the block that need to be processed. If so, the die binder picks up the next selected die to bind to the next selected die binding area of ​​the block. The next selected die and the next selected die binding area become the selected die and the selected die binding area. The process of binding the selected die to the selected die binding area is repeated until all die binding areas of the block are processed. After the block processing is completed, the die binder determines whether there are other blocks of the alignment panel 504 that need to be processed. If so, the die binder processes the remaining blocks until all blocks of the alignment face 50 are processed.

[0077] As described above, the alignment panel includes local alignment marks formed at predetermined locations thereon with high precision. The local alignment marks and die features (e.g., via openings) are used as fiducials and are matched with corresponding CAD files (CAD die and CAD panel files) for reference of the die and alignment panel. The binder has upward and downward looking cameras to align the die to the alignment panel with the same line of sight. Various features enable the die to be placed with high throughput and high placement accuracy of 3um, + / -0.5um XY repeatability, and + / -004 o The theta repeatability allows precise bonding to alignment panels. In addition, pre-bonding and post-bonding inspections can be easily performed. Furthermore, high accuracy and high throughput increase yield and simplify downstream processing of reconstructed wafers, resulting in lower manufacturing costs and higher yields.

[0078] Figure 6a-6e is a simplified cross-sectional view depicting an embodiment of a process for forming a reconstituted wafer and preparing the reconstituted wafer for further processing. Figure 6a , the alignment panel 604 includes a panel bonding surface 605 and a panel non-bonding surface 606. The panel bonding surface includes a local die alignment mark 650 for a die bonding area thereon. The panel tape 622 is attached to the panel bonding surface 605. The die 610 is bonded to the die bonding area of ​​the alignment panel 604 by a die bonder. As described above, the die bonder aligns and bonds the die 610 to the die bonding area using the local alignment mark 650. The panel tape attaches the die to the die bonding area of ​​the alignment panel 604.

[0079] As shown, the alignment panel 604 includes a die 610. The die 610 includes an alignment die 612 and an active die 611. For example, the alignment die 612 can be located at a corner die bonding area of ​​the block. Therefore, the simplified cross-sectional view illustrates the first row, the last row, the first column, or the last column of the die 610 of the block.

[0080] Reference Figure 6b , the alignment panel combined with the die 610 is subjected to a molding process. For example, a molding compound 670 is formed over the alignment panel 604, covering it and the die. The molding compound 670 and the die 610 may be referred to as a molded panel or a reconstructed wafer 665, and the molding panel and the alignment panel 604 may be referred to as a panel assembly or a reconstructed wafer assembly. The molding compound 670 may be in the form of a powder / granule, a liquid, or a film. In one embodiment, compression molding is performed to form the molding compound 670. Other techniques for forming the molding compound 670 may also be useful. The molding process is a high temperature process. For example, the alignment panel 604 with the die 610 is subjected to high temperature and high pressure, such as about 150-180°C and 240-320TF. The material of the alignment carrier 604 can withstand the conditions of the molding process without deformation, warping, or damage. In addition, due to the low CTE material of the alignment carrier 604, the linear changes caused by temperature changes are minimized.

[0081] like Figure 6c As shown, the upper surface of the molding compound 670 of the reconstructed wafer 665 is ground using, for example, a grinder 608. The grinder, for example, includes a grinding wheel for grinding the top surface of the molding compound 670. The surface of the molding compound 670 can be ground so that the reconstructed wafer 665 has a desired or defined height and ensures a uniform thickness to relieve stress.

[0082] Reference Figure 6d , releasing the reconstructed wafer 665 from the alignment panel 604. In one embodiment, releasing the reconstructed wafer 665 from the alignment panel 604 includes subjecting the reconstructed wafer assembly to a high temperature process, such as approximately 210 degrees Celsius. The high temperature peeling process causes the panel tape 622 to lose its adhesive properties, thereby enabling the reconstructed wafer 665 to be separated from the tape 622 and the alignment panel 604. For example, the peeling process may include peeling the panel tape 622 from the alignment panel 604, followed by peeling the panel tape 622 from the reconstructed wafer 665. Alternatively, the release process may release the reconstructed wafer 665 from the panel tape 622, followed by peeling the panel tape 622 from the alignment panel. Other techniques for releasing the reconstructed wafer 665 from the reconstructed wafer assembly may also be useful.

[0083] In one embodiment, the released reconstituted wafer 665 is mounted on a carrier substrate 694, such as Figure 6eAs shown. Carrier substrate 694 is used as a substrate for downstream processing of reconstructed wafer 665. For example, the carrier substrate should be rigid enough to support reconstructed wafer 665 for downstream processing, such as forming interconnects or conductive traces on reconstructed wafer 665, and carrier substrate 694 can be formed of metal. For example, the carrier substrate can be similar to an alignment panel except that local die alignment marks are not required. Other types of materials can also be used to form carrier substrate 694.

[0084] The carrier tape 623 is applied to a surface, such as a top surface. For example, the carrier tape can be a thermal or thermal release tape. Other types of tapes can also be used to facilitate bonding the reconstructed wafer 665 to the carrier substrate 694. The reconstructed wafer is attached to the carrier substrate 694 using the carrier tape 623. In one embodiment, the active surface of the reconstructed wafer 665 is exposed (facing up). For example, the passive surface of the reconstructed wafer 665 is bonded to the carrier substrate 694. The carrier substrate 694 with the reconstructed wafer 665 can be referred to as a carrier reconstructed wafer assembly.

[0085] Figure 7a-7c An embodiment of a die location check (DLC) process on a reconstituted wafer is described. Figure 7a , a carrier reconstructed wafer assembly is shown. The carrier reconstructed wafer assembly includes a reconstructed wafer 765 mounted face up on a carrier substrate (not shown). The reconstructed wafer includes a die 710 having a molding compound 770. The active surface of the die 710 is visible. As shown, the die 710 of the reconstructed wafer 765 are arranged in 4 blocks 715. The blocks are arranged in a 2×2 block matrix arrangement. The die 710 of each block 715 includes an alignment die 712 and an active die 711. The alignment die 712 can be used only for alignment purposes or can be an active die for alignment purposes. Each block 715 can include 4 alignment die 712 1-4 In one embodiment, the alignment die 712 1-4 Located at the corner of block 715. Alignment die 712 may also be disposed at other locations.

[0086] refer to Figure 7b , the DLC process scans the reconstructed wafer 765. In one embodiment, the DLC uses multiple cameras to scan the reconstructed wafer 765. In one embodiment, the DLC scan uses a first and a second camera (camera A and camera B) to scan the reconstructed wafer. As shown, camera A scans the first camera area 792 of the reconstructed wafer 765 (left half); camera B scans the second camera area 794 of the reconstructed wafer 765 (right half). For example, camera A scans the first and second blocks 715 on the left half of the reconstructed wafer 765 1-2 and camera B scans the third and fourth blocks 715 on the right half of the reconstructed wafer 7653-4 of all.

[0087] The DLC scan identifies the alignment die 712 of each block to determine the zero or origin (0,0) on the Cartesian coordinate system. In one embodiment, the zero point is the alignment die 7121 located at the upper left corner of the block 715. For example, the zero point is the alignment die 7121 located at the upper left corner of each block 715. The zero point can also be set at other locations of the block 715. Preferably, the zero point of each block is located at the same location. It may also be useful to position the zero points or origins of different blocks at different locations.

[0088] In one embodiment, the zero point is based on a point on the alignment die 7121. The zero point may correspond to, for example, a center point of the alignment die 7121. For example, the scan may determine a corner of the alignment die 7121, and the center of the corner may be the zero point. It may also be useful to provide a zero point corresponding to other locations or features of the alignment die 7121.

[0089] like Figure 7c As shown, the DLC scan scans the entirety of each block 715 of the reconstructed wafer 765. For example, in this case, each camera scans the blocks 715 in its respective camera area at a speed of scanning one block 715 at a time, and the camera area includes multiple blocks 715. In each block 715, the camera images multiple dies at a time. For example, each camera images a sub-block 718 of the die 710 of the block 715 at a time. For example, the scanning pattern of the block 715 can be from left to right and from top to bottom. Other scanning patterns for scanning blocks may also be useful. The scan produces a complete image of each block.

[0090] The image size of sub-block 718 can be, for example, approximately 14×10 mm. An image showing sub-block 7181 is provided. The image shows sub-block 7181 in more detail. Illustratively, sub-block 7181 includes 12 dies 710 arranged in a 3×4 matrix. Other image sizes of sub-block 718 may also be useful. For example, the image size can be selected to accommodate other numbers of dies 710. Sub-block 7181 includes origin-aligned die 7121 located in the upper left corner of sub-block 7151. For example, sub-block 7181 is the first sub-block of the first block 7151.

[0091] As shown, the alignment die 7121 is different from the active die 711. For example, the alignment die features are different from the active die features. As shown, the alignment die 7121 includes 2 large alignment die features (large through holes), between which smaller alignment die features (smaller through holes) are arranged along a line. Other arrangements of alignment die features may also be useful. As for the active die 711, they each include 2 columns of active die features (through holes). The through holes of the active die are smaller than the through holes of the alignment die 7121. Other arrangements of die or die features may also be useful.

[0092] The origin alignment die 7121 forms the zero point of the block 7151. For example, the x and y coordinates of the zero point of the alignment die 7121 are (0,0) corresponding to the Cartesian system of the block 7151. In one embodiment, the zero point corresponds to the center point of the alignment die 7121. It is also useful to provide zero points corresponding to other locations of the alignment die 7121. For example, the zero point can be determined by using other alignment die features or offsets of alignment die features of the alignment die 7121.

[0093] Sub-block 7181 includes sub-block reference point 719. Sub-block reference point 719 can be defined using a CAD sub-block file, similar to Figure 5a , except that the CAD sub-block file includes die features of multiple dies 710 of sub-block 718. The die features of die 710 are located in the CAD die file based on green data. For example, the spacing of the die, the size of the die, and the location of the die features are all based on green data. For example, sub-block reference point 719 is a virtual sub-block reference point of sub-block 7181. The position of sub-block reference point 719 can be pre-defined in the CAD sub-block file. The position of the sub-block reference point can be based on one or more features of one or more dies of sub-block 7181. As shown in the figure, the sub-block reference point deviates from the zero point or the alignment die 7121 located at the upper left corner of sub-block 7181.

[0094] In one embodiment, the sub-block reference point 719 of the sub-block 7181 includes a first and a second reference point. As shown, the first and second reference points are arranged vertically. For example, the second reference point is offset from the first reference point. Using at least two sub-block reference points enables translation and angle alignment. Other arrangements of the first and second reference points may also be useful. Similar to the die reference point, the sub-block reference point is a virtual sub-block reference point.

[0095] In one embodiment, the coordinate point of sub-block 7121 is defined. The sub-block coordinate point can be defined arbitrarily. For example, the sub-block coordinate point can be defined by selecting a die feature of one of the dies of sub-block 7181. The sub-block coordinate point can be offset from the zero point of block 715. In some cases, the sub-block coordinate point can be one of the sub-block reference points 719 of sub-block 7181. In other cases, the sub-block coordinate point can be the zero point of sub-block 7181. In this case, the sub-block coordinate point of sub-block 7181 does not deviate from the zero point of block 765.

[0096] As discussed, the scanning generates an image of the sub-block 718 of the block 715. The coordinate points of the other sub-blocks 718 of the block 715 are generated relative to the zero point or origin. Determining the coordinate points of the other sub-blocks is similar to generating the coordinate points of the first sub-block 7181.

[0097] In one embodiment, based on the first sub-block 7181, a zero point is determined. Based on the zero point, the positions of other sub-blocks can be determined. For example, using the green data, the spacing of other sub-blocks can be determined. For example, the center of the upper left corner die of each sub-block can be the sub-block coordinate point of each sub-block of the block. It may also be useful to select other locations for the sub-block coordinate points. The sub-block coordinate points can be referred to as indexed nominal coordinate points because they are determined based on the green data about the zero point.

[0098] In one embodiment, the CAD sub-block file is an image of the best fit sub-block. A best fit is performed for each sub-block. The best fit may result in an offset relative to the indexed nominal coordinate points of each sub-block. The virtual sub-block reference points are also offset. This generates a DLC file, which is a map of the block containing the sub-block coordinate points and their virtual sub-block reference points.

[0099] In one embodiment, a DLC file is generated for each block. The data contained in the DLC file may be in a DLC format. For example, the DLC file for block 715 is used to generate an LDI file for downstream laser direct imaging (LDI) processing, such as forming traces on block 715 of a reconstructed wafer. For example, the LDI file can be read by an LDI tool, such as a laser direct imager.

[0100] Figure 7c The image of the sub-block 7181 shown is the first sub-block of the first block 7151. In particular, the first sub-block 7181 includes an alignment die 7121 as a zero point for the first block 7151. Other sub-blocks of the block may have different arrangements. For example, the alignment die 712 may be located at a different position of the sub-block or the sub-block may not include an alignment die.

[0101] Figure 7d The images show different arrangements of sub-blocks 718 of a block. As shown, each arrangement of sub-blocks 718 is a 3×4 matrix. Conventional sub-blocks 718 G The image and the first, second, third and fourth corner sub-blocks 718 1-4 . The first corner sub-block 7181 includes a first alignment die 7121 disposed at the upper left corner of the sub-block, and an active die 711 is disposed at other positions of the sub-block. The second corner sub-block 7182 includes a second alignment die 7122 disposed at the lower left corner of the sub-block matrix and an active die 711 disposed at other positions of the sub-block. The third corner sub-block 7183 includes a third alignment die 7123 disposed at the upper right corner of the sub-block matrix and an active die 711 disposed at other positions of the sub-block. The fourth corner sub-block 7184 includes a fourth alignment die 7124 disposed at the lower right corner of the sub-block matrix and an active die 711 disposed at other positions of the sub-block. As for the general sub-block 718 G , it does not include any alignment die, only the active die 711.

[0102] Select slot block 718 1-4 One of the alignment die in the block is used as the zero point of the block. For example, the first alignment die 7121 of the first corner sub-block 7181 can be selected as the zero point of the block. The coordinate points of the other sub-blocks 718 are relative to the zero point.

[0103] like Figure 7d As described in , the block includes alignment die 712 at the corners of the block. However, other arrangements of alignment die for the block may also be useful. In some cases, the arrangement of the die of the sub-block 718 can be based on the arrangement of the alignment die 712 of the block, according to Figure 7d Make the changes described in .

[0104] Figure 8a-8c An embodiment of generating a circuit file for forming conductive traces on a reconstructed wafer is shown. Figure 8a , an image of the first sub-block 8181 of the reconstructed wafer is shown. For example, the sub-block 8181 includes a 3×4 matrix of dies 810. Illustratively, the sub-block 8181 includes an origin alignment die 8121 and an active die 811. As shown, the origin alignment die 8121 is a dedicated alignment die having different features from the active die. Alternatively, the alignment die 8121 can be an active die. As described above, the coordinate points of all sub-blocks of the block are generated relative to the origin and provided in the DLC file. In addition, a virtual sub-block reference point 819 can be provided from the sub-block CAD file.

[0105] Reference Figure 8b , a circuit file 8171 corresponding to a first sub-block of a die is shown. For example, the circuit file corresponds to a first sub-block with an origin aligned die. The circuit file includes circuits for the die of the sub-block. In one embodiment, the circuit file is based on green or design data. For example, placement of the circuit is based on the designed die pitch and position and die characteristics of the sub-block.

[0106] The circuit file of the first sub-block includes the position 813 of the alignment die. As shown in the figure, no circuit pattern is provided for the alignment die. For the circuit file of the sub-block, there is no alignment die, and there will be a circuit pattern of the die at the alignment die position. In some cases, the position of the alignment die can be at other positions of the sub-block. In this case, no circuit is provided at the position of the alignment die. The circuit of the circuit file for the die of the sub-block is not adapted. For example, according to the green data, the circuit is positioned in the circuit file. The circuit file includes a sub-block circuit reference point 849. As shown in the figure, the sub-block circuit reference point 849 includes a first and a second sub-block reference point. It may also be useful to provide other numbers of sub-block circuit reference points 849. The sub-block circuit reference points correspond to the sub-block reference points on the DLC file.

[0107] exist Figure 8c , an LDI file is generated. As shown in the figure, the circuit file of the first sub-block is aligned and attached to the first sub-block 8181. For example, the sub-block circuit reference point 849 of the first circuit sub-block file 8171 is aligned to the first sub-block reference point 819 of the first sub-block 8181 of the DLC file. Alignment and attachment of the circuit files of the sub-blocks are performed on all sub-blocks of the block. For example, the corresponding circuit files are aligned and attached according to the sub-block coordinate points in the DLC file. This generates an LDI file, which is used for downstream processing, for example, generating traces on an alignment carrier. The LDI file is in a format readable by an LDI tool.

[0108] Figure 8d 817. As shown in the figure, the sub-block circuit files include a general sub-block circuit file 817. G and corner block circuit file 817 1-4 The first corner sub-block circuit file 8171 includes a first alignment die location 8131 located in the upper left corner. The second corner sub-block circuit file 8172 includes a second alignment die location 8132 located in the lower left corner. The third corner sub-block circuit file 8173 includes a third alignment die location 8133 located in the upper right corner. The fourth corner sub-block circuit file 8174 includes a fourth alignment die location 8134 located in the lower right corner. There is no sub-block circuit file 8171. 1-4 Provide circuit pattern for aligned die location. For generic sub-block circuit file 817 G , which includes the circuit patterns at all die locations.

[0109] like Figure 8d As described in the foregoing, sub-block circuit file 817 is used to include blocks of aligned die at the corners of the block. However, other arrangements of aligned die of the block may also be useful. In this case, the circuit arrangement of sub-block circuit file 817 may be different from Figure 8d , depending on the arrangement of the blocks to the die.

[0110] Figure 9a-9e A simplified cross-sectional view of a carrier reconstituted wafer assembly is shown, illustrating an embodiment of a process for forming traces on the reconstituted wafer. Figure 9a, showing a carrier reconstructed wafer assembly. The carrier reconstructed wafer assembly includes a reconstructed wafer 965 attached to a carrier substrate 994 with a carrier tape 923. The reconstructed wafer includes a die 910 encapsulated in a molding compound 970. As shown, a simplified cross-sectional view of the reconstructed wafer 965 is a row or column of a block of die 910, which includes an alignment die 912 and an active die 911. For example, the row or column may be the last or first row or column of the block. The alignment die 912 is located at the end position of the row or column of the block. The die 910 includes a feature as an opening 962 in the buffer layer 960 to expose the die bonding pad of the die 910. Illustratively, the features of the alignment die 912 are different from the features of the active die 911. In other embodiments, the alignment die 912 may be the same as the active die 911.

[0111] exist Figure 9b In the embodiment of the present invention, a conductive layer or metal layer 980 is formed. For example, the conductive layer 980 can be a copper (Cu) layer. Other types of conductive layers can also be formed. As shown in the figure, the conductive metal layer 980 fills the through hole 962 of the bare chip 910. The conductive layer can be formed, for example, by an electroplating process. Other techniques can also be used to form the conductive layer 980. The conductive layer 980 can be referred to as a conductive filling layer 980.

[0112] In one embodiment, a metal seed layer 981 is formed on the reconstituted wafer 965, and a conductive fill layer 980 fills the via 962. The seed layer may be, for example, a titanium (Ti) layer formed by sputtering. Other types of seed layers or techniques for forming seed layers may also be useful.

[0113] refer to Fig.9c , after forming the seed layer 981, after removing the excess conductive layer 980, a thin film 982 is formed over the surface of the reconstructed wafer 965. For example, the thin film 982 covers the seed layer 981. In one embodiment, the thin film is a laser imageable thin film, such as a photoresist. In one embodiment, the laser imageable thin film 982 is a thin film 982 laminated to the surface of the reconstructed wafer 965. Other types or techniques for forming the laser imageable thin film 982 may also be useful.

[0114] like Figure 9d As shown, the film is patterned to form openings 984. In one embodiment, the pattern of the patterned dry film 982 corresponds to a circuit pattern or trace to be formed on the reconstructed wafer 965. In one embodiment, the dry film 982 is patterned using laser direct imaging (LDI) by an LDI tool. For example, the LDI tool uses a laser to expose the dry film. The exposure has a desired pattern. For example, the desired pattern is based on an LDI file. For example, the LDI file is as follows Figure 8cIn one embodiment, the LDI file is used to form traces for the active die 911 of the block. The LDI file can be used to form other types of interconnects for the active die of the block, such as a redistribution layer (RDL). The exposed dry film 982 is developed to form an opening 984 therein.

[0115] Reference Fig.9e , the process continues to form a conductive trace 986 that fills the opening 984 in the dry film 982. The conductive trace includes, for example, Cu or a Cu alloy. Other types of conductive traces 986 may also be useful. In one embodiment, the conductive trace 986 is formed by electroplating. The plating process fills the opening 984 in the dry film 982. The plating process slowly stops below the height of the dry film 982. The plating process forms a conductive trace 986 in the opening 984 of the dry film 982. As shown, the dry film is patterned to expose the seed layer, for example, near the edge of the reconstructed wafer. This facilitates the electroplating process.

[0116] After forming the conductive traces 986, the dry film 982 is removed, as shown in FIG. Figure 9f As shown. The exposed portion of the seed layer is removed. For example, dry etching can be used to remove the seed layer. Other types of etching processes can also be used to remove the exposed portion of the seed layer. After removing the exposed portion of the seed layer, the process can continue. For example, the process can continue to separate the reconstructed wafer 965 into individual packages.

[0117] Alternatively, the process can continue to form additional metal layers of the RDL structure over the die. For example, the dry filing, exposure, and plating processes can be repeated until the RDL structure is complete. The reconstituted wafer 965 can be singulated into individual packages.

[0118] Figure 10a-10b Simplified cross-sectional and top views of exemplary embodiments of a package having conductive traces are shown. Fig.10a , a top view 1007a and a cross-sectional view 1007b along AA' of package 1007 are shown. As shown, package 1007 includes a single die 1011. For example, package 1007 is a single die package with one die 1011. Die 1011 is wrapped by molding compound 1070. As shown, the inactive surface (without buffer layer 1060) of die 1011 and the side surface and the side surface of buffer layer 1060 are protected by molding compound 1070. As for the active surface of die 1077, it is protected by buffer layer 1060. Other arrangements of packages may also be useful.

[0119] Buffer layer 1060 includes a through hole opening filled with a conductive filler 1080. The conductive filled through hole opening may be referred to as a through hole contact. In one embodiment, a conductive trace 1086 is disposed above the through hole contact. For example, the pattern of conductive trace 1086 is defined by an LDI file. In one embodiment, the portion of conductive trace 1086 above the conductive path forms an annular ring 1089. Annular ring 1089 surrounds the circumference of the through hole contact. In one embodiment, the width W of annular ring 1089 is formed with high precision or tolerance. For example, the width W of annular ring 1089 may be about 15um. Other widths of the annular ring may also be useful. This makes the layout of die 1011 more compact, thereby having a smaller package footprint.

[0120] Fig.10b FIG. 1007 shows a top view 1007a and a cross-sectional view 1007b along the line AA' of another embodiment of package 1007. Package 1007 is a multi-die package. As shown in the figure, multi-die package 1007 includes first and second dies 1011. 1-2 It may also be useful to provide other numbers of dies 1011 for multi-die package 1007. Die 1011 1-2 As shown in the figure, the passive surface and side surface of the die 1011 and the buffer layer 1060 are protected by the molding compound 1070. 1-2 The active surface of the PCB is protected by a buffer layer 1060. Other arrangements of packaging may also be useful.

[0121] The buffer layer 1060 includes a via opening filled with a conductive filler 1080. The conductive filled via may be referred to as a via contact. In one embodiment, a conductive trace 1086 is disposed above the via contact. For example, the pattern of the conductive trace 1086 is defined by an LDI file. The pattern of the conductive trace includes the first and second die 1011. 1-2 For example, the conductive traces can be connected through the first and second die 1011 1-2 In one embodiment, the conductive trace portion above the through-hole contact forms an annular ring 1089. The annular ring 1089 surrounds the circumference of the through-hole contact. In one embodiment, the width W of the annular ring 1089 is formed with high precision or tolerance. For example, the width W of the annular ring 1089 is about 15 um. This achieves a high degree of flexibility in the die 1011. 1-2 A more compact layout, resulting in a smaller package footprint.

[0122] Figure 11a-11b An embodiment of defining cutting or sawing lines for a reconstituted wafer is shown. Fig.11a , a grid of dicing or sawing lines 1173 is generated for the die blocks of the reconstituted wafer.

[0123] The saw wire grid 1173 is created using the average x and y values ​​of the dies for each row and column of the block. For example, the saw wire grid 1173 is created using the average x and y values ​​of the adjacent rows and columns of the dies of the block. In one embodiment, the average x and y values ​​are based on the x and y measurements of the rows and columns of the dies of the block. The x saw wire 1187 is based on the measured y values ​​of the dies of the adjacent rows of dies and the y saw wire 1188 is based on the measured x values ​​of the dies of the adjacent columns of dies. In one embodiment, the x saw wire reference points 1177 are based on the measured y values ​​of the dies of the adjacent rows of dies and the y saw wire reference points 1178 are based on the measured x values ​​of the dies of the adjacent columns of dies. The x reference points 1177 and the y reference points 1178 define the x saw wires 1187 and y saw wires 1188 of the block, forming the saw wire grid 1173. The saw wire grid 1173 may be referred to as a dynamic saw wire grid, for example, because the spacing may vary depending on the measurements of the rows and columns of dies.

[0124] In one embodiment, the saw wire grid 1173 is best fitted to the block 1115 of the die 1110. In one embodiment, the saw wire grid 1173 is best fitted to the block 1115. The x saw wire reference points 1177 and the y saw wire reference points 1178 are determined relative to the origin of the block 1115. The x and y saw wire reference points are provided in the e-map file of the block 1115. The e-map file can be merged with the circuit pattern into the LDI file to form the saw wire reference points during the trace fabrication process. The physical saw wire reference points on the reconstructed wafer may be identified by the saw tool during the singulation process of the reconstructed wafer.

[0125] In another embodiment, the wire grid may be based on measurements of sub-blocks of a block. For example, based on the sub-block coordinate points of each sub-block, the average x and y values ​​of each row and column may be extrapolated to generate the wire grid 1173. The wire grid is then best fit to the x and y wire reference points generated by block 1115, which are provided in the e-map file of block 1115.

[0126] refer to Fig.11b , is another embodiment of a saw line for determining a block 1115 of a reconstructed wafer. The block 1115 includes dies 1110 arranged in rows and columns. For example, the dies 1110 of the block 1115 are arranged in a 3×4 matrix. Matrixes of other sizes may also be useful. As shown, the die 1110 includes an alignment die 1112 disposed at a corner position of the block 1115. The remaining positions of the block 1115 include active dies 1111.

[0127] In one embodiment, the saw line is determined based on an averaging technique. For example, when a saw line is between adjacent rows or adjacent columns of a die, an averaging technique is used. The averaging technique includes generating an x-average line 1197 and a y-average line 1198 for each column and each row of the die. The average line is generated using the centers of all the die 1110. For example, the centers of the die 1110 in each row are connected in the row or x direction to form a row or x-average line 1197; the centers of the die 1110 in each column are connected in the column or y direction to form a column or y-average line 1198.

[0128] In one embodiment, the number of x saw lines is equal to the number of rows in the block plus 1, and the number of y saw lines is equal to the number of columns in the block plus 1. In one embodiment, the x saw lines are parallel to each other and the y saw lines are parallel to each other. Since the average x and y lines are based on the actual measured positions of the die 1110 of the block 1115, the x and y saw lines can have variable pitches. The x and y saw line reference points 1177 and 1178 are provided in the e-map file. The e-map file can be merged into the LDI file along with the circuit pattern to form the saw line reference points during tracking production. The physical saw line reference points on the reconstructed wafer can be identified by the cutting tool during the segmentation process of the reconstructed wafer.

[0129] In another embodiment, the saw wire grid may be based on measurements of sub-blocks of block 1115. For example, based on the sub-block coordinate points of each sub-block, the average lines 1197 and 1198 of the die may be extrapolated to generate saw wire reference points 1777 and 1178.

[0130] Without departing from its spirit or essential characteristics, the present application may be implemented in other specific forms. Therefore, the aforementioned embodiments are considered to be illustrative in all aspects, rather than limiting the present application to this description. Therefore, the scope of the present application is indicated by the appended claims rather than by the aforementioned description, and all changes within the equivalent meaning and scope of the claims are intended to be included therein.

Claims

1. A method for bonding bare dies for panel level processing, comprising: providing an alignment panel having a bonding surface, the bonding surface comprising a die bonding area for bonding a die, wherein the bonding surface comprises a local alignment mark, wherein the bonding surface comprises a panel adhesive film for facilitating bonding the die to the die bonding area; and Binds the selected die to the selected die binding area, including: aligning the selected die with the selected die bonding area using local alignment marks of the selected die bonding area, and When the selected die is aligned with the selected die bond, the selected die is bonded to the selected die bond area.

2. The method of claim 1 , wherein aligning the selected die to the selected die bonding area comprises: providing a CAD die file having die features corresponding to selected die features on a selected die surface and a defined CAD die reference point; providing a CAD panel file having panel features corresponding to local die alignment marks of the selected die bonding area and a defined CAD panel reference point; imaging a surface of the selected die using the selected die features through the camera model and fitting the CAD die file to the surface of the selected die; imaging the selected die bonding area using local alignment marks and best fitting the CAD panel file to the selected die bonding area; and The selected die is aligned with the selected die bonding area by aligning the CAD die reference points of the best fitting selected die with the CAD panel reference points of the best fitting selected die bonding area.

3. The method of claim 2, wherein: The CAD die reference points include first and second CAD die reference points; and The CAD panel reference points include first and second CAD panel reference points, wherein providing the first and second CAD die reference points and the first and second panel reference points enables translational and angular alignment of the selected die to the selected die bonding area.

4. The method of claim 1 , wherein bonding the selected die to the selected die bonding area comprises: bonding a next selected die to a next selected die bonding area of ​​the alignment panel; and Repeating the process of bonding the next selected die to the next selected die bonding area is performed until all die bonding areas of the aligned panel are bonded to dies.

5. The method according to claim 4, characterized in that The process also includes wrapping the die bonded to the die bonding area of ​​the alignment panel with a molding compound to form a reconstructed wafer.

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