Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The method includes the following steps: providing a substrate, on the top of which a first intermediate structure layer is formed, and a first metal structure penetrating the first intermediate structure layer along a first direction perpendicular to the top surface of the first intermediate structure layer; sequentially forming a first etch stop layer, a second etch stop layer, a second intermediate structure layer, and a hard mask layer on the top surface of the first intermediate structure layer; performing an integrated etching process to form an opening penetrating the second intermediate structure layer until the second etch stop layer is exposed; performing a dry etching process step by step to remove the second etch stop layer and the first etch stop layer respectively, and the dry etching process is also used to remove a part of the hard mask layer; forming a second metal structure in the opening, and the second metal structure is interconnected with the first metal structure; performing chemical mechanical polishing to completely remove the hard mask layer. The manufacturing process of the semiconductor device is optimized, and the performance and yield of the semiconductor device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the reduction of the size of semiconductor devices, in the latter-stage process of device manufacturing, it is necessary to form a damascene structure by etching trenches and holes, so as to fill copper in the trenches and holes to form wires and constitute a conductive path. At present, the all-in-one (AIO) metal damascene etching process has become a relatively common process.

[0003] However, when forming a damascene structure by all-in-one etching, on the one hand, it is easy to damage the underlying metal. For example, due to the inconsistent etching rates of different patterns, the surface of copper in the corresponding area is over-etched, forming a "U"-shaped or "V"-shaped area, which in turn affects the Rc resistance value and electron mobility of the wafer. On the other hand, the remaining metal hard mask TiN layer on the top after all-in-one etching is relatively thick. If the subsequent chemical mechanical polishing (CMP) cannot completely remove it, the TiN residue will also affect the device performance. Summary of the Invention

[0004] Based on this, in view of the problems in the above background art, it is necessary to provide a semiconductor device and a manufacturing method thereof, which can at least avoid metal damage and metal hard mask residue and improve the performance of the semiconductor device.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a manufacturing method of a semiconductor device, including the following steps:

[0006] Provide a substrate, on the top of which a first intermediate structure layer is formed, and a first metal structure penetrating the first intermediate structure layer along a first direction perpendicular to the top surface of the first intermediate structure layer;

[0007] Form a first etch stop layer, a second etch stop layer, a second intermediate structure layer and a hard mask layer on the top surface of the first intermediate structure layer in sequence;

[0008] Perform an all-in-one etching process to form an opening penetrating the second intermediate structure layer until the second etch stop layer is exposed;

[0009] Perform a dry etching process step by step to remove the second etch stop layer and the first etch stop layer respectively, and the dry etching process is also used to remove part of the hard mask layer;

[0010] Form a second metal structure in the opening, and the second metal structure is interconnected with the first metal structure;

[0011] Perform chemical mechanical polishing to completely remove the hard mask layer.

[0012] In one embodiment, the second etch stop layer includes a tantalum oxide layer or an aluminum oxide layer, the first etch stop layer includes a silicon oxide layer, and the hard mask layer includes a titanium nitride layer.

[0013] In one embodiment, the stepwise dry etching process for separately removing the second etch stop layer and the first etch stop layer includes:

[0014] Perform a first dry etching process using a chloride as an etch gas to remove the second etch stop layer and a portion of the hard mask layer;

[0015] Perform a second dry etching process using a fluoride as an etch gas to remove the first etch stop layer.

[0016] In one embodiment, the chloride includes boron chloride gas, and the fluoride includes carbon fluoride gas.

[0017] In one embodiment, the thickness range of the second etch stop layer includes 30 Å to 80 Å, and the thickness range of the first etch stop layer includes 50 Å to 150 Å.

[0018] In one embodiment, the first intermediate structure layer includes a nitrogen-doped silicon carbide layer and a silicon oxycarbide layer formed in sequence along the first direction, and the second intermediate structure layer includes a nitrogen-doped silicon carbide layer and a low-k dielectric material layer formed in sequence along the first direction.

[0019] In one embodiment, before forming the hard mask layer, a step of forming a sacrificial layer is further included. The sacrificial layer includes tetraethyl orthosilicate, and the sacrificial layer is removed while completely removing the hard mask layer.

[0020] In one embodiment, the first metal structure and the second metal structure include copper.

[0021] In one embodiment, the etch gas for the integrated etching process includes fluorinated hydrocarbon gas.

[0022] Another aspect of the present application provides a semiconductor device fabricated by using the manufacturing method of the semiconductor device described in any one of the above.

[0023] According to the semiconductor device and its manufacturing method provided by the present invention, by forming two etching stop layers, one is used to avoid damage to the underlying metal during integrated etching, and the other is used to avoid introducing new damage to the semiconductor device during the process of removing the etching stop layer. At the same time, the removal of the etching stop layer and chemical mechanical polishing are combined to control the retention or removal of the hard mask layer. This not only enables the use of the hard mask layer to control the topography of the semiconductor device but also avoids the residue of the mask layer, optimizing the manufacturing process of the semiconductor device and improving the performance and yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To better describe and illustrate the embodiments and / or examples of the applications disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the currently described embodiments and / or examples, and the currently understood best mode of these applications.

[0025] Figure 1 It is a schematic flowchart of a manufacturing method of a semiconductor device provided in an embodiment;

[0026] Figure 2 It is a schematic cross-sectional structure diagram of the obtained structure after forming the first intermediate structure layer and the first metal structure in step S101 of a manufacturing method of a semiconductor device provided in an embodiment;

[0027] Figure 3 It is a schematic cross-sectional structure diagram of the obtained structure after forming an opening penetrating the second intermediate structure layer in step S103 of a manufacturing method of a semiconductor device provided in an embodiment;

[0028] Figure 4 It is a schematic cross-sectional structure diagram of the obtained structure after performing dry etching on the second etching stop layer and the first etching stop layer in step S104 of a manufacturing method of a semiconductor device provided in an embodiment;

[0029] Figure 5 It is a schematic cross-sectional structure diagram of the obtained structure after forming the second metal structure in step S105 of a manufacturing method of a semiconductor device provided in an embodiment;

[0030] Figure 6 It is a schematic cross-sectional structure diagram of the obtained structure after performing chemical mechanical polishing in step S107 of a manufacturing method of a semiconductor device provided in an embodiment.

[0031] DESCRIPTION OF REFERENCE NUMERALS:

[0032] 210. The first intermediate structure layer; 211. The first nitrogen-doped silicon carbide layer; 212. The silicon carbon oxide layer; 220. The first metal structure; 231. The first etch stop layer; 232. The second etch stop layer; 240. The second intermediate structure layer; 241. The second nitrogen-doped silicon carbide layer; 242. The low dielectric constant material layer; 250. The sacrificial layer; 260. The hard mask layer; 270. The second metal structure. Detailed implementation manners

[0033] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant attached drawings. The preferred embodiments of this application are shown in the attached drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0035] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0036] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to encompass different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0038] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes as illustrated may be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the particular shapes of regions shown herein, but include shape deviations resulting from, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of regions of the device and are not intended to limit the scope of the present application.

[0039] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present application. Although only the components related to the present application are shown in the illustrations and are not drawn according to the number, shape and size of the components in actual implementation, the types, numbers and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0040] The present invention provides a method for manufacturing a semiconductor device, as Figure 1 shown, comprising the following steps:

[0041] Step S101: Provide a substrate, on the top of which a first intermediate structure layer is formed, and a first metal structure that penetrates the first intermediate structure layer along a first direction perpendicular to the top surface of the first intermediate structure layer;

[0042] Step S102: Sequentially form a first etch stop layer, a second etch stop layer, a second intermediate structure layer, and a hard mask layer on the top surface of the first intermediate structure layer;

[0043] Step S103: Perform an integrated etching process to form an opening that penetrates the second intermediate structure layer until the second etch stop layer is exposed;

[0044] Step S104: Perform a dry etching process step by step to remove the second etch stop layer, the first etch stop layer respectively, and the dry etching process is also used to remove a part of the hard mask layer;

[0045] Step S105: Form a second metal structure in the opening, and the second metal structure is interconnected with the first metal structure;

[0046] Step S106: Perform chemical mechanical polishing to completely remove the hard mask layer.

[0047] First, perform Step S101. Refer to Figure 2 As shown, provide a substrate, on the top of which a first intermediate structure layer 210 is formed, and a first metal structure 220 that penetrates the first intermediate structure layer along a first direction perpendicular to the top surface of the first intermediate structure layer.

[0048] In one embodiment, the substrate shown may be at least one of the materials mentioned below: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. Preferably, the substrate is a single crystal silicon substrate.

[0049] In one embodiment, the first intermediate structure layer 210 includes a first nitrogen-doped silicon carbide layer 211 (NDC) and a silicon carbon oxide layer 212 (SiCO) formed in sequence along the first direction. In one embodiment, the thickness range of the first nitrogen-doped silicon carbide layer 211 includes 300 Å to 400 Å, such as 300 Å, 350 Å, 400 Å, preferably 350 Å. The silicon carbon oxide layer 212 is formed on the top surface of the first nitrogen-doped silicon carbide layer 211, and the thickness range of the silicon carbon oxide layer 212 includes 1500 Å to 2000 Å, such as 1500 Å, 1650 Å, 2000 Å, preferably 1650 Å. The method for forming the first nitrogen-doped silicon carbide layer 211 and the silicon carbon oxide layer 212 can use chemical vapor deposition (CVD), such as one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0050] Exemplarily, the first metal structure 220 penetrates the first intermediate structure layer 210 along the first direction perpendicular to the top surface of the first intermediate structure layer 210. In one embodiment, the first metal structure 220 includes one of a contact plug (Contact, CT), a metal wiring, or a combination of a contact plug and a metal wiring. Both the contact plug and the metal wiring can use materials such as tungsten, copper, aluminum, etc., preferably copper.

[0051] Next, step S102 is executed. Referring to Figure 3 as shown, a first etch stop layer 231, a second etch stop layer 232, a second intermediate structure layer 240, and a hard mask layer 260 are sequentially formed on the top surface of the first intermediate structure layer 210.

[0052] Exemplarily, the second etch stop layer 232 includes, but is not limited to, metal oxide layers such as tantalum oxide (Ta2O5) or aluminum oxide (Al2O3), and the first etch stop layer 231 includes a silicon oxide layer (SiO2). In one embodiment, first, a process technology familiar to those skilled in the art, such as chemical vapor deposition (CVD), is used to form the first etch stop layer 231 on the top surface of the first intermediate structure layer 210 and the first metal structure 220. Specifically, using silane (SiH4) as the source gas, a gas mixture of silane diluted by nitrogen (N2) and excess oxygen (O2) is heated to 250°C to 450°C. Silane reacts with oxygen to generate silicon oxide (SiO2) and deposits on the surface of the first intermediate structure layer 210 to form the first etch stop layer 231. The thickness range of the first etch stop layer 231 includes 50 Å to 150 Å, such as 50 Å, 100 Å, 150 Å, and preferably 100 Å. Then, a second etch stop layer 232 is formed on the top surface of the first etch stop layer 231. Specifically, using a halogen compound of tantalum such as tantalum chloride (TaCl5) or an organic compound of tantalum such as Ta(OC2H5)5 as the precursor, mixed with oxygen O2, and using an inert gas (e.g., nitrogen N2, argon Ar, etc.) as the carrier gas, a tantalum oxide (Ta2O5) thin film is deposited. The thickness range of the second etch stop layer 232 includes 30 Å to 80 Å, such as 30 Å, 50 Å, 80 Å, and preferably 50 Å. The method for forming the second etch stop layer 232 can use chemical vapor deposition (CVD), such as one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer chemical vapor deposition (ALCVD).

[0053] In one embodiment, the second etch stop layer 232 uses a metal oxide layer. The second etch stop layer has a high etch selectivity with the subsequently formed second intermediate structure layer to serve as an etch stop layer for the subsequent integrated etch step. That is, when performing integrated (AIO) etching, the etch endpoint stops at the upper surface of the second etch stop layer 232. The first etch stop layer 231 uses a non-metal oxide layer. The first etch stop layer has a high etch selectivity with the second etch stop layer and the first metal structure to serve as an etch stop layer for the subsequent process of removing the second etch stop layer. That is, when performing dry etching to remove the second etch stop layer 232, the etch endpoint stops at the upper surface of the first etch stop layer 231. When further performing dry etching to remove the first etch stop layer 231, the surface of the first metal structure 220 will not be damaged.

[0054] Further, a second intermediate structure layer 240 is formed on the second etch stop layer 232. The second intermediate structure layer 240 includes a second nitrogen-doped silicon carbide layer 241 (NDC) and a low dielectric constant material layer 242 formed in sequence along a first direction. In one embodiment, the second nitrogen-doped silicon carbide layer 241 is first formed on the top surface of the second etch stop layer 232. The thickness range of the second nitrogen-doped silicon carbide layer 241 includes 300 Å to 400 Å, such as 300 Å, 350 Å, 400 Å, preferably 350 Å. Then, a low dielectric constant material layer 242 is formed on the top surface of the second nitrogen-doped silicon carbide layer 241. The low dielectric constant material layer 242 can well reduce the signal attenuation caused by the impedance and capacitive reactance delay of the circuit itself during the propagation of electrical signals. The material of the low dielectric constant material layer 242 includes but is not limited to black diamond (bd). Bd is a dielectric material composed of C, H, O, and Si elements, and the K value is 2.5 to 3.3. The thickness range of the low dielectric constant material layer 242 includes 3000 Å to 4000 Å, such as 3000 Å, 3350 Å, 4000 Å, preferably 3350 Å.

[0055] Next, a sacrificial layer 250 is formed on the top surface of the low dielectric constant material layer 242. The material of the sacrificial layer 250 includes but is not limited to tetraethyl orthosilicate (TEOS). The thickness range of the sacrificial layer 250 includes 200 Å to 400 Å, such as 200 Å, 300 Å, 400 Å, preferably 300 Å. The methods for forming the second nitrogen-doped silicon carbide layer 241, the low dielectric constant material layer 242, and the sacrificial layer 250 can employ chemical vapor deposition (CVD), such as one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0056] Further, a hard mask layer 260 is formed on the top surface of the sacrificial layer 250. The hard mask layer 260 can not only protect the morphology of the second intermediate structure layer 240 from changing during the integrated etching process, but also protect the second intermediate structure layer 240 from being damaged by bombardment and maintain its morphology unchanged during the formation of the second metal structure. The material of the hard mask layer 260 includes but is not limited to titanium nitride (TiN). The thickness range of the hard mask layer 260 includes 200 Å to 400 Å, such as 200 Å, 300 Å, 400 Å, preferably 300 Å. The method for forming the hard mask layer 260 can be completed by using process technologies familiar to those skilled in the art such as chemical vapor deposition (CVD), and will not be elaborated here.

[0057] Then, step S103 is executed, referring to Figure 3As shown, an all-in-one etching process is performed to form an opening penetrating the second intermediate structure layer 240 until the second etch stop layer 232 is exposed.

[0058] In one embodiment, an all-in-one (AIO) etching process is performed. The so-called all-in-one means that the three steps of via etching, photoresist removal, and trench etching are completed in the same process step. Using CxHyFz as the etching gas to perform the all-in-one etching process, the hard mask layer 260, the sacrificial layer 250, and the second intermediate structure layer 240 (the second nitrogen-doped silicon carbide layer 241 and the low dielectric constant material layer 242) are all etched to form openings for the damascene structure. Among them, vias are formed in a part of the second nitrogen-doped silicon carbide layer 241 and the low dielectric constant material layer 242, and trenches are formed in another part of the low dielectric constant material layer 242, the sacrificial layer 250, and the hard mask layer 260. Since the all-in-one etching has a high etching selectivity for both the second etch stop layer 232 and the second nitrogen-doped silicon carbide layer 241, the low dielectric constant material layer 242, the sacrificial layer 250, and the hard mask layer 260, the all-in-one etching stops on the surface of the second etch stop layer 232, avoiding over-etching damage to the surface of the first metal structure 220 by the all-in-one etching process.

[0059] Next, step S104 is performed. As Figure 4 shown, a dry etching process is performed step by step to remove the second etch stop layer 232 and the first etch stop layer 231 respectively. The dry etching process is also used to remove a part of the hard mask layer 260.

[0060] Exemplarily, the step-by-step dry etching process to remove the second etch stop layer 232 and the first etch stop layer 231 respectively includes: performing a first dry etching process using a chloride as the etching gas to remove the second etch stop layer 232 and a part of the hard mask layer 260; performing a second dry etching process using a fluoride as the etching gas to remove the first etch stop layer 231.

[0061] In one embodiment, to avoid undercut caused by removing the etch stop layer by wet etching, which may lead to bottom voids during subsequent metal filling, dry etching is used to remove the etch stop layer. Specifically, first, BCl3 is used as the etch gas to perform the first dry etching. Since the first dry etching has a high etch selectivity for the second etch stop layer 232 and the first etch stop layer 231, the first dry etching stops at the surface of the first etch stop layer 231. Then, a CF-based gas is used as the etch gas to perform the second dry etching. Since the second dry etching has a high etch selectivity for the first etch stop layer 231 and the first metal structure 220, the second dry etching stops at the surface of the first metal structure 220 and does not damage the first metal structure 220.

[0062] In one embodiment, to avoid incomplete removal of the hard mask layer 260 and residue generation due to the relatively thick hard mask layer 260 during subsequent chemical mechanical polishing (CMP) to remove the hard mask layer 260, a dry etching step is required to remove part of the hard mask layer 260. At the same time, to avoid bombardment damage to the sacrificial layer 250 and the second intermediate structure layer 240 during the formation of the second metal structure, part of the hard mask layer 260 needs to be retained to keep the profiles of the sacrificial layer 250 and the second intermediate structure layer 240 unchanged. In summary, in this embodiment, the first dry etching is also used to remove part of the hard mask layer 260. Specifically, the thickness of the hard mask layer 260 is thinned from about 300 Å to about 200 Å.

[0063] Next, step S105 is performed, as Figure 5 shown, to form a second metal structure 270 in the opening, and the second metal structure 270 is interconnected with the first metal structure 220.

[0064] In one embodiment, a metal material layer is formed. The metal material layer fills the opening and covers the top surface of the hard mask layer 260. The metal material filling the opening forms the second metal structure 270. The bottom surface of the second metal structure 270 is connected to the top surface of the first metal structure 220 to interconnect the second metal structure 270 with the first metal structure 220. The material of the second metal structure 270 is preferably copper, and the method for forming the second metal structure can be one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0065] Referring to Figure 5 shown, during the formation of the second metal structure, the surface of the hard mask layer 260 is bombarded and damaged, and the thickness of the hard mask layer 260 is further thinned from about 200 Å to less than 100 Å.

[0066] Next, step S106 is performed, asFigure 6 As shown, chemical mechanical polishing is performed to completely remove the hard mask layer 260.

[0067] In one embodiment, chemical mechanical polishing (CMP) is performed. First, the metal material layer on the top surface of the hard mask layer 260 is removed by chemical mechanical polishing, and then the hard mask layer 260 is removed. To avoid TiN residue in the hard mask layer 260, the sacrificial layer 250 is also removed by chemical mechanical polishing, and the process stops at the top surface of the second intermediate structure layer 240.

[0068] So far, the introduction of the related steps of the manufacturing method of the semiconductor device according to the embodiment of the present invention has been completed. It can be understood that the manufacturing method of the semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of this manufacturing method.

[0069] Refer to Figure 6 , which shows a schematic cross-sectional view of a semiconductor device provided according to the present invention. The semiconductor device is manufactured by the above method.

[0070] As Figure 6 shown, the semiconductor device includes:

[0071] A first metal structure 220, which penetrates the first intermediate structure layer 210 along a first direction perpendicular to the top surface of the first intermediate structure layer 210;

[0072] A second metal structure 270, which is interconnected with the first metal structure 220 and penetrates the second intermediate structure layer 240 along the first direction;

[0073] An etch stop layer, which is located between the first intermediate structure layer 210 and the second intermediate structure layer 240.

[0074] In one embodiment, the first intermediate structure layer 210 includes a first nitrogen-doped silicon carbide layer 211 (NDC) and a silicon carbon oxide layer 212 (SiCO) formed in sequence along the first direction. In one embodiment, the thickness range of the first nitrogen-doped silicon carbide layer 211 includes 300 Å to 400 Å, such as 300 Å, 350 Å, 400 Å, and preferably 350 Å. The silicon carbon oxide layer 212 is formed on the top surface of the first nitrogen-doped silicon carbide layer 211, and the thickness range of the silicon carbon oxide layer 212 includes 1500 Å to 2000 Å, such as 1500 Å, 1650 Å, 2000 Å, and preferably 1650 Å.

[0075] In one embodiment, the first metal structure 220 penetrates through the first intermediate structure layer 210 along a first direction perpendicular to the top surface of the first intermediate structure layer 210. In one embodiment, the first metal structure 220 includes one of a contact plug (CT), a metal wiring, or a combination of a contact plug and a metal wiring. Both the contact plug and the metal wiring can be made of materials such as tungsten, copper, aluminum, etc., and copper is preferred.

[0076] In one embodiment, the second intermediate structure layer 240 includes a second nitrogen-doped silicon carbide layer 241 (NDC) and a low dielectric constant material layer 242 formed in sequence along the first direction. The thickness range of the second nitrogen-doped silicon carbide layer 241 includes 300 Å to 400 Å, such as 300 Å, 350 Å, 400 Å, and 350 Å is preferred. The material of the low dielectric constant material layer 242 includes, but is not limited to, black diamond (bd). Bd is a dielectric material composed of elements C, H, O, and Si, and the K value is 2.5 to 3.3. The thickness range of the low dielectric constant material layer 242 includes 3000 Å to 4000 Å, such as 3000 Å, 3350 Å, 4000 Å, and 3350 Å is preferred. The low dielectric constant material layer 242 can well reduce the signal attenuation caused by the impedance and capacitive reactance delay of the circuit itself during the propagation of electrical signals.

[0077] In one embodiment, the second metal structure 270 penetrates through the second intermediate structure layer 240 along a first direction perpendicular to the top surface of the second intermediate structure layer 240. The second metal structure 270 includes, but is not limited to, a damascene structure. The damascene structure can be made of materials such as tungsten, copper, aluminum, etc., and copper is preferred. The bottom surface of the second metal structure 270 is connected to the top surface of the first metal structure 220 so that the second metal structure 270 is interconnected with the first metal structure 220.

[0078] In one embodiment, a first etch stop layer 231 is disposed on top of the first intermediate structure layer 210, a second etch stop layer 232 is disposed on top of the first etch stop layer 231, and the second intermediate structure layer 240 is disposed on top of the second etch stop layer 232. The first etch stop layer 231 includes a silicon oxide layer (SiO2). The thickness range of the first etch stop layer 231 includes 50 Å to 150 Å, such as 50 Å, 100 Å, 150 Å, and 100 Å is preferred. The second etch stop layer 232 includes, but is not limited to, a metal oxide layer such as tantalum oxide (Ta2O5) or aluminum oxide (Al2O3). The thickness range of the second etch stop layer 232 includes 30 Å to 80 Å, such as 30 Å, 50 Å, 80 Å, and 50 Å is preferred. Among them, the second etch stop layer 232 and the second intermediate structure layer 240 have a high etch selectivity, and the first etch stop layer 231 and the first metal structure 220 have a high etch selectivity.

[0079] The specific structure of the semiconductor device can be referred to the description in the corresponding part above. For the sake of brevity, it will not be elaborated here.

[0080] According to the semiconductor device and its manufacturing method provided by the present invention, by forming two etching stop layers, one for avoiding the damage to the underlying metal during the integrated etching, and the other for avoiding bringing new damage to the semiconductor device during the process of removing the etching stop layer. At the same time, the removal and retention of the hard mask layer are jointly controlled by using the two steps of removing the etching stop layer and chemical mechanical polishing. It can not only use the hard mask layer to control the topography of the semiconductor device, but also avoid the residue of the mask layer, optimize the manufacturing process of the semiconductor device, and improve the performance and yield of the semiconductor device.

[0081] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present application.

[0082] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0083] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0084] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising the following steps: Providing a substrate, on the top of which a first intermediate structure layer is formed, and a first metal structure penetrating the first intermediate structure layer along a first direction perpendicular to the top surface of the first intermediate structure layer; Sequentially forming a first etch stop layer, a second etch stop layer, a second intermediate structure layer, and a hard mask layer on the top surface of the first intermediate structure layer; Performing an integrated etching process to form an opening penetrating the second intermediate structure layer until the second etch stop layer is exposed; Performing a dry etching process step by step to remove the second etch stop layer, the first etch stop layer respectively, and the dry etching process is also used to remove part of the hard mask layer to thin the thickness of the hard mask layer and retain part of the hard mask layer; Forming a second metal structure in the opening, and the second metal structure is interconnected with the first metal structure; Performing chemical mechanical polishing to completely remove the hard mask layer.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The second etch stop layer includes a tantalum oxide layer or an aluminum oxide layer, the first etch stop layer includes a silicon oxide layer, and the hard mask layer includes a titanium nitride layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein, The step of performing a dry etching process step by step to remove the second etch stop layer, the first etch stop layer respectively includes: Performing a first dry etching process using a chloride as an etching gas to remove the second etch stop layer and part of the hard mask layer; Performing a second dry etching process using a fluoride as an etching gas to remove the first etch stop layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein, The chloride includes boron chloride gas, and the fluoride includes carbon fluoride gas.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The thickness range of the second etch stop layer includes 30 Å to 80 Å, and the thickness range of the first etch stop layer includes 50 Å to 150 Å.

6. The method for manufacturing a semiconductor device according to claim 1, wherein, The first intermediate structure layer includes a nitrogen-doped silicon carbide layer and a silicon carbon oxide layer formed sequentially along the first direction, and the second intermediate structure layer includes a nitrogen-doped silicon carbide layer and a low dielectric constant material layer formed sequentially along the first direction.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming the hard mask layer, there is also a step of forming a sacrificial layer, the sacrificial layer includes tetraethyl orthosilicate, and the sacrificial layer is removed while the hard mask layer is completely removed.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The first metal structure and the second metal structure include copper.

9. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The etching gas for the integrated etching process includes fluorinated hydrocarbon gas.

10. A semiconductor device, characterized in that, Prepared by using the preparation method of the semiconductor device according to any one of claims 1 to 9.

Images