Cutting method, semiconductor structure and chip

Abstract

The invention relates to a cutting method, a semiconductor structure and a chip. According to the cutting method, a first groove is formed in a second area of a substrate and filled with a first dielectric layer, then a second groove is formed in the first dielectric layer in the first groove, the structure, originally located in the first groove area, of the substrate is removed by forming the first groove, and the structure can be a complex structure and can comprise different materials. When the second groove is formed, only the first dielectric layer is etched in the first groove area, and compared with the mode of directly removing the structure of the second area to form the groove, the method is suitable for different cutting area materials of the substrate, the cutting difficulty can be reduced, damage and pollution to the substrate in the cutting process can be reduced, and the cutting quality is improved. The semiconductor structure and the chip can be formed by adopting the cutting method, damage and pollution to the semiconductor structure and the chip are small, and the quality of the semiconductor structure and the quality of the chip are high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a cutting method, a semiconductor structure and a chip. Background Art

[0002] After the semiconductor chip is produced through a set process, it needs to be cut to separate the chips on the substrate. The separated chips are packaged individually or further bonded to other chips and / or substrates to form a system-level package. Currently, there are mainly several cutting methods, including wheel cutting, laser cutting, plasma cutting and invisible cutting (which refers to the use of infrared laser focused into the inside of the wafer to destroy the lattice structure and separate the chips during film expansion).

[0003] With the development of technology, the cutting process is required to be less destructive and less polluting to the chip. In order to save area, it is usually necessary to set test structures (test keys), alignment marks, measurement marks and feature patterns on the cutting path. Such structures often include metal. Among the above-mentioned cutting methods, wheel cutting and laser cutting are more destructive and polluting. Although plasma cutting and invisible cutting are less polluting, they both require that there is no metal on the cutting path (i.e., the cutting path is clear). At present, there is still a lack of cutting methods that are suitable for different cutting area materials and have less destructive and less polluting cutting processes. Summary of the invention

[0004] In order to be applicable to different cutting area materials and to have a cutting process with less destructiveness and less pollution, the present invention provides a cutting method. The present invention also provides a semiconductor structure and a chip.

[0005] In one aspect, the present invention provides a cutting method, comprising:

[0006] Obtaining a substrate, the substrate comprising a first region and a second region located between adjacent first regions, the substrate comprising a front side and a back side facing each other;

[0007] forming a first groove in the second region of the substrate, wherein the first groove extends from the front surface into the substrate;

[0008] forming a first dielectric layer, wherein the first dielectric layer at least fills the first trench;

[0009] A second trench is formed in the first dielectric layer within the first trench, and the second trench extends from a surface of the first dielectric layer into the substrate.

[0010] Optionally, the substrate includes a substrate and a dielectric layer formed on the substrate, a metal layer is formed in the dielectric layer located in the second area, and a laser cutting process is performed to remove the dielectric layer and the metal layer located in the second area to form the first groove in the second area of ​​the substrate.

[0011] Optionally, before forming the first dielectric layer, slag and surface particles generated by the laser cutting process are removed.

[0012] Optionally, the first trench at least penetrates the dielectric layer.

[0013] Optionally, before forming the second groove, a second dielectric layer is formed in the first area and the second area, and a conductive pad is formed in the second dielectric layer in the first area, the second dielectric layer located in the area corresponding to the second groove does not include metal, and the second groove also extends from the surface of the second dielectric layer into the substrate.

[0014] Optionally, before forming the second groove, a third dielectric layer is formed in the first area and the second area, and the third dielectric layer covers the conductive pad; a plasma cutting process is performed from the surface of the third dielectric layer located in the first groove toward the substrate to form the second groove until the substrate is separated.

[0015] Optionally, before separating the substrate by the plasma cutting process, the substrate is thinned from the back side and the thinned back side of the substrate is placed on a carrier tape.

[0016] Optionally, the substrate is a wafer, the first area is a chip area, and the second area is a saw track area.

[0017] In another aspect, the present invention provides a semiconductor structure, comprising:

[0018] A substrate, the substrate comprising a first region and a second region located between adjacent first regions, the substrate comprising a front surface and a back surface facing each other;

[0019] A first groove is formed in the second region of the substrate and extends from the front surface into the substrate;

[0020] A first dielectric layer, filling at least the first trench;

[0021] The second groove is formed in the first dielectric layer in the first groove and extends from the surface of the first dielectric layer into the substrate.

[0022] Optionally, the substrate includes a substrate and a dielectric layer formed on the substrate, and the first groove at least penetrates the dielectric layer.

[0023] Optionally, the semiconductor structure also includes a second dielectric layer and a conductive pad, the second dielectric layer also extends from the surface of the second dielectric layer into the substrate, the conductive pad is formed in the second dielectric layer located in the first area, wherein the second dielectric layer located in the area corresponding to the second groove does not include metal.

[0024] Optionally, the semiconductor structure further includes a third dielectric layer formed in the first region and the second region and covering the conductive pad, and the second trench further extends from a surface of the third dielectric layer into the substrate.

[0025] In another aspect, the present invention provides a chip, comprising:

[0026] A first chip surface and a second chip surface facing away from each other; and

[0027] A first surface, a first groove surface formed by removing a portion of the substrate structure;

[0028] A second surface is a surface of a second groove formed by filling a first dielectric layer in the first groove and etching a region of the first dielectric layer, wherein the first surface and the second surface are located between the first chip surface and the second chip surface and intersect at an edge of the chip, and the first dielectric layer is filled between the first surface and the second surface.

[0029] In the cutting method provided by the present invention, a first groove is formed in the second area of ​​the substrate and filled with a first dielectric layer, and then a second groove is formed in the first dielectric layer in the first groove. By forming the first groove, the structure of the substrate originally located in the second groove area is removed. When forming the second groove, only the first dielectric layer is etched in the first groove area. Compared with directly removing the structure of the second area to form the groove, the method is suitable for different substrate cutting area materials, can reduce the cutting difficulty, and helps to reduce the destructiveness and pollution of the substrate during the cutting process, thereby improving the cutting quality.

[0030] The semiconductor structure provided by the present invention includes a substrate, a first groove formed in the second area of ​​the substrate, a first dielectric layer filling the first groove, and a second groove formed in the first dielectric layer in the first groove. The substrate can be separated from the second groove area, with little damage and pollution to the substrate, and the quality of the semiconductor structure is high.

[0031] The chip provided by the present invention comprises a first chip surface and a second chip surface facing each other, and also comprises a first face and a second face, wherein the first face is a first groove surface formed by removing a part of the substrate structure, and the second face is a second groove surface formed by filling a first dielectric layer in the first groove and etching the first dielectric layer region, wherein the first face and the second face are located between the first chip surface and the second chip surface and intersect at the edge of the chip. The chip can be formed by the above-mentioned cutting method, the formation of the first groove and the second groove has little destructiveness and pollution to the chip, and the quality of the chip is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic flow chart of the cutting method according to an embodiment of the present invention.

[0033] Figures 2A to 2K It is a cross-sectional schematic diagram of a cutting method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following is a further detailed description of the cutting method, semiconductor structure and chip of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in an inaccurate scale, which is only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order to perform these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the accompanying drawings is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0035] Regarding semiconductor cutting, there are still problems with the use of wheel cutting, laser cutting, plasma cutting and stealth cutting (referring to the use of infrared laser focusing on the inside of the wafer to destroy the lattice structure and separate the chip during film expansion). For example, the cutting surface of the wheel cutting is rough, which is prone to problems such as chipping, cracking, passivation and lifting of the metal layer, which can easily lead to bonding interface defects and pollution; laser cutting will produce a heat-affected zone during the cutting process, the cutting surface is rough, and slag will accumulate on the surface of the chip, and cleaning the slag will easily cause pollutants to spread; although plasma cutting and stealth cutting have less pollution, both require no metal on the cutting path (i.e., the cutting path is clear), but in order to save area, the current process usually needs to set test structures (test keys), alignment marks, measurement marks and feature patterns on the cutting path. Such structures often include metal components. If such structures are not set on the cutting path, the effective area of ​​the chip will be lost, increasing the manufacturing cost. In comparison, the cutting method of the embodiment of the present invention is suitable for different substrate cutting area materials and the cutting process is less destructive and less polluting. The specific description is as follows.

[0036] Reference Figure 1 and Figure 2A According to the cutting method of the embodiment of the present invention, a substrate 10 is obtained, the substrate 10 includes a first area A1 and a second area A2 located between adjacent first areas A1, and the substrate 10 includes a front side and a back side facing each other.

[0037] The cutting method is used, for example, to cut a wafer to form a chip. The substrate 10 is, for example, a wafer, the first area A1 is, for example, a chip area, and the second area A2 is a cutting track area. The front side of the substrate 10 is, for example, a side surface on which a device in a chip is formed. As an example, Figure 2A The upper surface of the substrate 10 shown is the front surface, and the lower surface is the back surface. It can be understood that the cutting method described in the present application is also applicable to the case where the substrate 10 is made of non-semiconductor material.

[0038] like Figure 2A As shown, the base plate 10 may include a substrate 100 and a dielectric layer 110 formed on the substrate 100, wherein a metal layer is formed in the dielectric layer 110. The substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a silicon germanium-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates for carrying semiconductor components known to those skilled in the art. In the following description, the substrate 100 is, for example, a silicon substrate.

[0039] The specific structure of the substrate 10, such as the components included and their sizes and arrangements, can be set according to specific needs. As an example, in the first area A1, a semiconductor element (not shown) may be formed in the surface area of ​​the substrate 100, such as at least one of a MOS device, a sensor device, a memory device, and a passive device, etc. A metal interconnect structure 111 is formed above the semiconductor element (the metal interconnect structure 111 in the figure is only used as an example, and may actually include multiple metal interconnect layers and conductive channels formed between the metal interconnect layers), and a pad PAD1 is formed above the metal interconnect structure 111. The semiconductor element, the metal interconnect structure 111, and the pad PAD1 are isolated by a dielectric material, and there is a conductive channel in the dielectric material to connect them. A passivation layer 112 is formed on the top of the dielectric material, and the pad PAD1 is exposed from an opening in the passivation layer 112. The dielectric material and the passivation layer 112 located on the substrate 100 around the metal interconnect structure 111 in the substrate 10 constitute a dielectric layer 110, and a metal layer composed of various metal materials is formed in the dielectric layer 110. The metal layers in the dielectric layer located in the first area A1 and the second area A2 can be the same or different.

[0040] As an example, in the second area A2, the substrate 10 is formed with a structure formed synchronously with the metal components and dielectric materials of the first area A1, for example, the second area A2 may be formed with at least one of a test key, an alignment mark, a measurement mark, and a feature pattern. Moreover, the metal material located in the second area A2 is a metal layer formed in the second area A2. The structure of the second area A2 may include more than one material.

[0041] Reference Figure 1 and Figure 2C A first trench T1 is formed in the second area A2 of the substrate 10 , and the first trench T1 extends from the front surface of the substrate 10 into the substrate 10 .

[0042] like Figure 2B As shown, optionally, before forming the first trench T1, a cover layer 120 is formed on the front surface of the substrate 10. The cover layer 120 can protect the surface of the substrate 10 in the subsequent laser cutting process. The cover layer 120, for example, includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or other suitable materials. In the following embodiments, the cover layer 120 is, for example, silicon oxide.

[0043] like Figure 2C As shown, as an example, a laser cutting process is performed to remove the dielectric layer 110 and the metal layer located in the second area A2 to form a first trench T1 in the second area A2 of the substrate 10. In other embodiments, other processes other than the laser cutting process may be used to remove the dielectric layer 110 and the metal layer located in the second area A2 to form the first trench T1 in the second area A2 of the substrate 10.

[0044] When performing the laser cutting process, a laser with a frequency of nanosecond, picosecond or femtosecond can be used to generate a suitable laser light source, so that the laser light source irradiates the second area A2 of the substrate 10. Since the laser has no selectivity for cutting materials, the material at a certain depth of the second area A2 of the substrate 10 can be removed as needed to form the first groove T1. By controlling the cutting degree of the laser cutting process, the metal layer of the second area A2 can be removed, which facilitates the subsequent further cutting of the substrate 10 in the second area A2.

[0045] Alternatively, if Figure 2C As shown, the first trench T1 at least penetrates the dielectric layer 110, that is, the depth of the first trench T1 in the substrate 10 is greater than or equal to the thickness of the dielectric layer 110, which not only facilitates the removal of the metal layer in the second area A2, but also simplifies the structure of the second area A2 and reduces the difficulty of the subsequent cutting process. In some embodiments, the first trench T1 may not penetrate the dielectric layer 110, the depth of the first trench T1 in the substrate 10 may be less than the thickness of the dielectric layer 110, and a dielectric layer 110 of a certain thickness may be retained between the bottom surface of the first trench T1 and the substrate 100 without retaining the metal layer. In the direction parallel to the front surface of the substrate 10, the cross-sectional width of the first trench T1 may be greater than, equal to, or less than the cross-sectional width of the second area A2.

[0046] Compared with the plasma cutting process, the laser cutting process has a slow cutting speed, a rough cutting surface, and is prone to slag accumulation in the cutting area. Therefore, in this embodiment, the laser cutting process is not used to completely thermally cut off the second area A2 of the substrate 10, but to form a first groove T1. On the one hand, the metal layer located in the second area A2 can be removed, and on the other hand, the speed of the entire cutting process is less affected, and the slag and surface particles generated are also less, which is convenient for cleaning and trimming the cutting surface.

[0047] Figure 2C The black dots inside and outside the first groove T1 indicate the slag and surface particles generated by the laser cutting process. In order to ensure the cleanliness of the substrate 10 and avoid contamination caused by the slag and surface particles generated by the laser cutting process, refer to Figure 1 and Figure 2D After the laser cutting process is completed and before the first dielectric layer is filled in the first trench T1, the slag and surface particles on the substrate 10 are removed. The slag refers to the melt attached to the substrate 10 due to the laser thermal effect, and the particles attached to the substrate 10 except the slag are referred to as surface particles.

[0048] Various suitable processes may be used to remove the slag and surface particles. As an example, at least one of wet cleaning and chemical mechanical polishing may be used to remove the slag and surface particles. For example, wet cleaning is first performed to remove at least part of the surface particles, and the specific cleaning solution may be selected according to the composition of the surface particles, and then chemical mechanical polishing (i.e., CMP) is performed to remove the slag and the remaining surface particles, such as Figure 2D As shown, after chemical mechanical polishing, the cover layer 120 is thinned, and then wet cleaning can be performed again to remove residual pollutants and particles. After removing the slag and surface particles, the cover layer 120 can be retained or removed as needed.

[0049] Optionally, after the process of removing the slag and surface particles generated by the laser cutting process is completed, the surface of the first groove T1 formed by the laser cutting process, that is, the first surface, can be smoothed, and the first surface of the first groove T1 is a curved surface, so that the rough surface generated by the laser cutting process can be improved. For example, the rounding process can be performed by a plasma ashing process, and the gas for generating plasma can be selected as needed. Among them, the first surface of the first groove T1 includes a first side wall and a first bottom wall, and the first side wall and the first bottom wall can be smoothly connected or non-smoothly connected. It can be understood that the morphology of the first side wall and the first bottom wall of the first groove T1 can be any shape, and the first side wall and / or the first bottom wall of the first groove T1 can be a curved surface or a plane. For example, on a cross section perpendicular to the front, the first side wall of the first groove T1 is an arc or an inclined straight line or a vertical straight line relative to the front of the substrate 10, and the first bottom wall of the first groove T1 is an arc or a straight line.

[0050] Reference Figure 1 and Figure 2E , forming a first dielectric layer 130, which at least fills the first trench T1. The first dielectric layer 130 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or other suitable materials. In the following embodiments, the first dielectric layer 130 is, for example, silicon oxide.

[0051] like Figure 2EAs shown, as an example, the first dielectric layer 130 not only fills the first trench T1, but also covers the upper surface of the dielectric layer 110 outside the first trench T1. When the cover layer 120 is retained, the first dielectric layer 130 also covers the upper surface of the cover layer 120 outside the first trench T1. In order to improve the surface flatness of the first dielectric layer 130, when forming the first dielectric layer 130, the deposition thickness of the first dielectric layer 130 is made greater than the depth of the first trench T1. After the deposition is completed, a planarization treatment (such as CMP) is performed to improve the flatness of the upper surface of the first dielectric layer 130. After planarization, the thickness of the first dielectric layer 130 can be less than, equal to or greater than the depth of the first trench T1. The first dielectric layer 130 on the substrate 10 outside the first trench T1 can be retained or removed.

[0052] Figure 2F FIG. 1 shows a cross-sectional structure of a second dielectric layer 140 formed on a substrate 10 including a first dielectric layer 130, a metal redistribution layer (RDL) formed in the second dielectric layer 140, and a conductive pad PAD2. Figure 2F As an example, the chip located in at least one chip area A1 of the substrate 10 is subsequently used for bonding and interconnection with other structures. In order to facilitate the bonding of the chip with other structures, after forming the above-mentioned first dielectric layer 130 and before forming the second trench T2, a second dielectric layer 140 is formed in the first area A1 on the front side of the substrate 10, and a conductive pad is formed in the second dielectric layer 140 in the first area A1; further, the second dielectric layer 140 can also be formed in the second area A2, and the second dielectric layer 140 located in the area corresponding to the second trench T2 does not include metal. It can be understood that when the first dielectric layer 130 only fills the first trench T1 but does not cover the front surface of the substrate 10 outside the first trench T1, the thickness of the first dielectric layer 130 can be less than, equal to, or greater than the depth of the first trench T1, and the second dielectric layer 140 can be formed only on the front surface of the substrate 10 outside the first trench T1, or the second dielectric layer 140 can be further formed on the first dielectric layer 130 in the second area A2; when the first dielectric layer 130 not only fills the first trench T1 but also covers the surface of the substrate 10 outside the first trench T1, the second dielectric layer 140 can be formed only on the first dielectric layer 130 in the first area A1, or the second dielectric layer 140 can be further formed on the first dielectric layer 130 in the second area A2. Figure 2F, exemplarily, the following process may be included: forming a second dielectric layer 140 on the surface of the first dielectric layer 130 in the first area A1 and the second area A2, and forming a metal redistribution layer RDL and a conductive pad PAD2 in the second dielectric layer 140 in the first area A1, and connecting the metal redistribution layer RDL to the pad PAD1 of each chip area A1, and connecting the conductive pad PAD2 to the metal redistribution layer RDL, or only forming the conductive pad PAD2 without forming the metal redistribution layer RDL, and the second dielectric layer 140 exposes the conductive pad PAD2 or buries the conductive pad PAD2, or only forming the metal redistribution layer RDL without forming the conductive pad PAD2, and the second dielectric layer 140 exposes the metal redistribution layer RDL or buries the metal redistribution layer RDL. The second dielectric layer 140 may be a single-layer or multi-layer structure. The present invention is not limited to the formation of the metal redistribution layer RDL and the conductive pad PAD2. For example, in another embodiment, the metal redistribution layer RDL and the conductive pad PAD2 can be formed in the substrate 10 before the first trench T1 is formed. In another embodiment, the chip located in at least one chip area A1 is connected to other structures through the pad PAD1. After the first dielectric layer 130 is formed, the second dielectric layer 140, the metal redistribution layer RDL and the conductive pad PAD2 are no longer formed.

[0053] Reference Figure 1 , Figure 2G and Figure 2H A second trench T2 is formed in the first dielectric layer 130 in the first trench T1, and the second trench T2 extends from the surface of the first dielectric layer 130 into the substrate 10. In this embodiment, a second dielectric layer 140 is formed on the first dielectric layer 130, and the second trench T2 also extends from the surface of the second dielectric layer 140 into the substrate 10.

[0054] like Figure 2G As shown, before forming the second trench T2, a third dielectric layer 150 can be formed in the first area A1 on the front side of the substrate 10, and the third dielectric layer 150 covers the conductive pad PAD2. Furthermore, the third dielectric layer 150 can also be formed in the second area A2, and the second trench T2 also extends from the surface of the third dielectric layer 150 into the substrate 10.

[0055] The third dielectric layer 150 can be used as a hard mask when forming the second trench T2. The material of the third dielectric layer 150 can be selected as needed. In this embodiment, an exposed conductive pad PAD2 is formed on the substrate 10. In order to protect the conductive pad PAD2 and prevent the diffusion of metal (such as copper), the third dielectric layer 150 can be made of a diffusion-proof material. The third dielectric layer 150 can be made of, for example, one of dielectric materials such as silicon nitride, silicon oxynitride, and NDC (Nitrogen doped Silicon Carbide) or a combination thereof.

[0056] As an example, forming the second trench T2 may include the following process:

[0057] First, if Figure 2G As shown, a third dielectric layer 150 and a patterned photoresist layer (the photoresist layer is not shown) located on the third dielectric layer 150 are formed, wherein the patterned photoresist layer has an opening located in the region of the first dielectric layer 130 in the first trench T1;

[0058] Afterwards, if Figure 2H As shown, using the patterned photoresist layer as a mask, an etching process (such as dry etching or wet etching) or a plasma cutting process is performed from the surface of the third dielectric layer 150 located in the first trench T1 toward the substrate 10 to form the second trench T2. When the third dielectric layer 150 and the second dielectric layer 140 are not formed in the first area A1 and the second area A2 of the substrate 10, the first dielectric layer 130 in the area where the second trench T2 is located is removed, and the second trench T2 extends from the surface of the first dielectric layer 130 into the substrate 10; when the second dielectric layer 140 is formed on the surface of the first area A1 and the second area A2 of the substrate 10, but the third dielectric layer 150 is not formed, the second dielectric layer 140 and the first dielectric layer 130 in the area where the second trench T2 is located are removed, and the second trench T2 extends from the surface of the first dielectric layer 130 into the substrate 10; when the second dielectric layer 140 is formed on the surface of the first area A1 and the second area A2 of the substrate 10, but the third dielectric layer 150 is not formed, the second dielectric layer 140 and the first dielectric layer 130 in the area where the second trench T2 is located are removed, and the second trench T2 The second trench T2 extends from the surface of the second dielectric layer 140 into the substrate 10; when the third dielectric layer 150 and the second dielectric layer 140 are formed on the surfaces of the first area A1 and the second area A2 of the substrate 10, the third dielectric layer 150, the second dielectric layer 140, and the first dielectric layer 130 are sequentially etched, and the substrate 100 can be further etched, and the third dielectric layer 150, the second dielectric layer 140, and the first dielectric layer 130 in the area where the second trench T2 is located are removed, and the second trench T2 extends from the surface of the third dielectric layer 150 into the substrate 10. It can be understood that those skilled in the art can also use other processes other than the etching process and the plasma cutting process to form the second trench T2.

[0059] The surface of the second trench T2 includes a second surface, and the second surface of the second trench T2 includes a second side wall and a second bottom wall. The second side wall and the second bottom wall can be smoothly connected or non-smoothly connected. It can be understood that the second side wall and the second bottom wall of the second trench T2 can be of any shape, and the second side wall and / or the second bottom wall of the second trench T2 can be a curved surface or a plane. For example, on a cross section perpendicular to the front, the second side wall of the second trench T2 is an arc or an inclined straight line or a vertical straight line relative to the front of the substrate 10, and the second bottom wall of the second trench T2 is an arc or a straight line. In this embodiment, the second bottom wall of the second trench T2 is, for example, located in the substrate 100, so that when the second area A2 is further cut by a plasma process later, only the substrate 100 needs to be cut, which can reduce the difficulty of cutting and improve efficiency. In addition, the second trench T2 can be formed by an anisotropic dry etching process, so that the second side wall of the second trench T2 can be smoother and substantially perpendicular to the front of the substrate 10, which helps to optimize the side wall morphology of the chip to be separated and helps to improve the cutting accuracy. In other embodiments, the second bottom wall of the second trench T2 is, for example, located in the first dielectric layer 130. The width of the second trench T2 is, for example, less than or equal to the width of the first trench T1, and further, the second sidewalls of the second trench T2 are, for example, located inside the first sidewalls of the first trench T1. The depth of the second trench T2 is, for example, less than or equal to or greater than the depth of the first trench T1. Preferably, the width of the second trench T2 is less than the width of the first trench T1, and the depth of the second trench T2 in the substrate 10 is greater than the depth of the first trench T1 in the substrate 10.

[0060] Reference Figure 1 and Figure 2K Further, the patterned third dielectric layer 150 is used as a mask to continue the etching process or plasma cutting process to deepen the second trench T2 until the substrate 10 is separated. The length of the second side wall of the second trench T2 and the depth of the second bottom wall in the substrate 10 gradually increase as the substrate 10 is separated.

[0061] The first dielectric layer 130 is filled between the first surface of the first trench T1 and the second surface of the second trench T2. When the second bottom wall of the second trench T2 is located in the first dielectric layer 130, the first dielectric layer 130 is filled between the first side wall of the first trench T1 and the second side wall of the second trench T2, and the first dielectric layer 130 is filled between the first bottom wall of the first trench T1 and the second bottom wall of the second trench T2; when the second bottom wall of the second trench T2 is located in the substrate 100, the first surface of the first trench T1 intersects with the second surface of the second trench T2, and the first dielectric layer 130 is filled between the first side wall of the first trench T1 and the second side wall of the second trench T2.

[0062] As an example, in Figure 2HBased on the structure shown, the following process can be further performed:

[0063] like Fig.2I As shown, first, the substrate 10 is thinned from the back side, and the back side of the substrate 10 after thinning is placed on a carrier tape 200. The carrier tape 200 is used to fix the substrate 10 and the cut chips, and helps to make the cut chips intact in the subsequent cutting process, reducing the risk of chip collapse, displacement and falling. The carrier tape 200 is, for example, a UV film. In some embodiments, the substrate 10 may not be thinned as needed.

[0064] like Figure 2J As shown, after that, the patterned third dielectric layer 150 is used as a mask to perform a plasma cutting process on the substrate 100 exposed by the second trench T2, so that the substrate 100 below the second trench T2 is removed, and the chips in each chip area are separated. In this embodiment, the plasma cutting process is compared with the wheel cutting and laser cutting processes, and the side wall formed by cutting is smooth and has good flatness, and the product can be discharged with the process gas during the cutting process, so the pollution to the chip is small;

[0065] like Figure 2K As shown, after that, according to the need of exposing the pad PAD1 (such as the case where the conductive pad PAD2 is not formed) or the conductive pad PAD2, such as before the cut chip is packaged or bonded with other structures, the third dielectric layer 150 is removed. The chip obtained by the above-mentioned cutting method can be bonded and interconnected with a bottom substrate through a bonding process. When bonding, for example, the surface of the chip formed with the conductive pad PAD2 is made the bonding surface, and the two can be bonded by a hybrid bonding process. Since the chip obtained by the above-mentioned cutting method has a high surface cleanliness, it is helpful to meet the cleanliness requirements of the hybrid bonding process and improve the yield.

[0066] In the cutting method described in the above embodiment, a first trench T1 is formed in the second area A2 of the substrate 10 and filled with the first dielectric layer 130, and then a second trench T2 is formed in the first dielectric layer 130 in the first trench T1. By forming the first trench T1, the structure of the substrate 10 originally located in the first trench T1 area is removed. When forming the second trench T2, the first dielectric layer 130 in the first trench T1 is etched. Compared with directly removing the structure of the second area A2 to form the trench, the method is suitable for materials of different cutting areas, reduces the difficulty of cutting, and helps to reduce the destructiveness and pollution of the cutting process to the substrate 10, thereby improving the cutting quality.

[0067] An embodiment of the present invention further relates to a semiconductor structure, which can be formed by using the above-mentioned cutting method.

[0068] Reference Figure 2HThe semiconductor structure includes a substrate 10, the substrate 10 includes a first area A1 and a second area A2 located between the first areas A1, and the substrate 10 includes a front side and a back side opposite to each other. As an example, the substrate 10 is a wafer, the first area A1 is a chip area, and the second area A2 is a sawing area. The front side of the substrate 10 is, for example, a side surface of a device in a chip. As an example, Figure 2H The upper surface of the substrate 10 shown is the front surface, and the lower surface is the back surface.

[0069] The semiconductor structure also includes a first dielectric layer 130 and a first trench T1 and a second trench T2 formed in a second area A2 of the substrate 10, wherein the first trench T1 extends from the front surface of the substrate 10 into the substrate 10, and the first dielectric layer 130 at least fills the first trench T1, and the second trench T2 is formed in the first dielectric layer 130 in the first trench T1, and extends from the surface of the first dielectric layer 130 into the substrate 10.

[0070] In some embodiments, the substrate 10 includes a substrate 100 and a dielectric layer 110 formed on the substrate 100 . The dielectric layer 110 is located on the front side of the substrate 10 . The first trench T1 at least penetrates the dielectric layer 110 .

[0071] like Figure 2H As shown, the semiconductor structure may further include a second dielectric layer 140 and a conductive pad PAD2, the second dielectric layer 140 is formed in the first area A1 and the second area A2 and covers the first dielectric layer 130, the second trench T2 also extends from the surface of the second dielectric layer 140 in the second area A2 into the substrate 10, the conductive pad PAD2 is formed in the second dielectric layer 140 located in the first area A1, wherein the second dielectric layer 140 located in the area corresponding to the second trench T2 does not include metal. In addition, the semiconductor structure may further include a third dielectric layer 150, the third dielectric layer 150 is formed in the first area A1 and the second area A2 and covers the second dielectric layer 140, the second trench T2 also extends from the surface of the third dielectric layer 130 in the second area A2 into the substrate 10. The relative positional relationship between the first dielectric layer 130, the second dielectric layer 140 and the third dielectric layer 150 can be referred to the above description, and will not be repeated here.

[0072] An embodiment of the present invention further relates to a chip, which can be formed by using the above-mentioned cutting method.

[0073] Reference Figure 2KAs shown, two chips are formed by cutting the substrate 10. In the embodiment of the present invention, the chip includes a first chip surface and a second chip surface opposite to each other, and also includes a first surface and a second surface. The first surface is a surface of a first groove T1 formed by removing part of the structure of the substrate 10, and the second surface is a surface of a second groove T2 formed by filling the first dielectric layer 130 in the first groove T1 and etching the first dielectric layer 130 area. The first surface and the second surface are located between the first chip surface and the second chip surface and intersect at the edge of the chip, and the first dielectric layer 130 is filled between the first surface and the second surface.

[0074] In the embodiment of the present invention, a first groove T1 and a second groove T2 are formed in the second area A2 of the substrate 10 in the semiconductor structure, and the substrate 10 can be separated from the second groove T2 area. The second groove T2 extends from the surface of the first dielectric layer 130 into the substrate 10, which has little destructiveness and pollution to the formed semiconductor structure and chip, and the semiconductor structure has high quality.

[0075] It should be noted that the embodiments in this specification are described in a progressive manner, and each part focuses on the differences from other embodiments. The relevant parts can be understood by reference.

[0076] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A cutting method, characterized in that: include: Obtaining a substrate, the substrate comprising a first region and a second region located between adjacent first regions, the substrate comprising a front side and a back side facing each other; forming a first groove in the second region of the substrate, wherein the first groove extends from the front surface into the substrate; forming a first dielectric layer, wherein the first dielectric layer at least fills the first trench; A second trench is formed in the first dielectric layer within the first trench, and the second trench extends from a surface of the first dielectric layer into the substrate.

2. The cutting method according to claim 1, characterized in that: The substrate includes a substrate and a dielectric layer formed on the substrate, a metal layer is formed in the dielectric layer located in the second area, and a laser cutting process is performed to remove the dielectric layer and the metal layer located in the second area to form the first groove in the second area of ​​the substrate.

3. The cutting method according to claim 2, characterized in that: Before forming the first dielectric layer, slag and surface particles generated by the laser cutting process are removed.

4. The cutting method according to claim 2, characterized in that: The first trench at least penetrates the dielectric layer.

5. The cutting method according to claim 1, characterized in that: Before forming the second groove, a second dielectric layer is formed in the first area and the second area, and a conductive pad is formed in the second dielectric layer in the first area. The second dielectric layer in the area corresponding to the second groove does not include metal, and the second groove also extends from the surface of the second dielectric layer into the substrate.

6. The cutting method according to claim 5, characterized in that: Before forming the second trench, forming a third dielectric layer in the first region and the second region, wherein the third dielectric layer covers the conductive pad; A plasma cutting process is performed from the surface of the third dielectric layer in the first trench toward the substrate to form the second trench until the substrate is separated.

7. The cutting method according to claim 6, characterized in that: Before the substrate is separated by the plasma cutting process, the substrate is thinned from the back side and the thinned back side of the substrate is placed on a carrier tape.

8. The cutting method according to any one of claims 1 to 7, characterized in that: The substrate is a wafer, the first area is a chip area, and the second area is a dicing area.

9. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first region and a second region located between adjacent first regions, the substrate comprising a front side and a back side facing each other; A first groove is formed in the second region of the substrate and extends from the front surface into the substrate; A first dielectric layer, filling at least the first trench; The second groove is formed in the first dielectric layer in the first groove and extends from the surface of the first dielectric layer into the substrate.

10. The semiconductor structure according to claim 9, wherein: The substrate includes a substrate and a dielectric layer formed on the substrate, and the first trench at least penetrates the dielectric layer.

11. The semiconductor structure according to claim 9, wherein: Also includes: A second dielectric layer is formed in the first region and the second region and covers the first dielectric layer, and the second groove further extends from the surface of the second dielectric layer into the substrate; A conductive pad is formed in the second dielectric layer located in the first area, wherein the second dielectric layer located in the area corresponding to the second trench does not include metal.

12. The semiconductor structure according to claim 11, wherein: Also includes: A third dielectric layer is formed in the first region and the second region and covers the conductive pad, and the second groove further extends from the surface of the third dielectric layer into the substrate.

13. A chip, characterized in that: include: A first chip surface and a second chip surface opposite to each other; as well as A first surface, a first groove surface formed by removing a portion of the substrate structure; A second surface is a surface of a second groove formed by filling a first dielectric layer in the first groove and etching a region of the first dielectric layer, wherein the first surface and the second surface are located between the first chip surface and the second chip surface and intersect at an edge of the chip, and the first dielectric layer is filled between the first surface and the second surface.

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