Partition cutting method based on wafer dark crack and chip unit

Abstract

The invention provides a wafer dark crack-based partition cutting method and a chip unit, the wafer dark crack-based partition cutting method comprises the following steps: providing a glass carrying table and a CCD (Charge Coupled Device), and setting a light source; acquiring a grayscale image of the wafer to be cut through the CCD; judging whether dark cracks exist in the to-be-cut wafer or not; a personnel instruction is obtained, and if the personnel instruction is a first instruction, a plurality of cutting channels are obtained; dividing the to-be-cut wafer into a plurality of areas based on the dark crack line segments and the plurality of cutting channels; and the interiors of the multiple areas are cut in sequence. An image is recognized through a CCD, the image is processed into a gray level image, whether dark cracks exist or not is detected through gray level difference, for the condition that the dark cracks exist, a wafer to be cut is partitioned, a plurality of areas are cut respectively, and a machine is prevented from cutting a plurality of chip units which are arranged irregularly due to dislocation caused by the dark cracks.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor production, and in particular to a partition cutting method based on wafer dark cracking and a chip unit. Background Art

[0002] Today's LED chip products are developing in the direction of miniaturization and density, and the requirements for wafer cutting in the LED chip production process are becoming increasingly higher.

[0003] Currently, the most common LED chip cutting equipment is the picosecond laser scribing machine, which uses a fixed wavelength laser to cut sapphire. Before cutting, a wide-angle CCD (Charge Coupled Device) is used to detect the wafer contour to determine the size and shape of the wafer. The picosecond laser scribing machine will cut it according to the contour identified by the wide-angle CCD.

[0004] However, dark cracks are prone to occur during the cleaning, transfer and other processing processes of the wafer, and existing technologies cannot detect dark cracks. Dark cracks cause slight misalignment of the arrangement of LED chips on the wafer. If cutting is performed according to the originally planned automatic cutting route, the misaligned LED chips will be scratched. Summary of the invention

[0005] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a zoning cutting method and a chip unit based on wafer dark cracks, aiming to solve the problem in the prior art that dark cracks are difficult to detect and easily lead to chip scratches.

[0006] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0007] A partition cutting method based on wafer dark cracking comprises the following steps:

[0008] Providing a glass stage and a CCD, and arranging a light source in the glass stage;

[0009] Placing a wafer to be cut on the glass stage, and acquiring a grayscale image of the wafer to be cut through the CCD, wherein the wafer to be cut includes a plurality of chip units;

[0010] Determining whether the wafer to be cut has dark cracks based on the grayscale image, and if so, establishing one or more dark crack line segments from the grayscale image;

[0011] Obtaining a personnel instruction, and determining an instruction type of the personnel instruction, wherein the instruction type includes a first instruction and a second instruction;

[0012] If the personnel instruction is the first instruction, based on the positions of the plurality of chip units, a plurality of cutting lanes are acquired, wherein the cutting lanes are located between adjacent chip units;

[0013] Based on the dark crack line segments and the plurality of cutting streets, establishing regional demarcation lines to divide the wafer to be cut into a plurality of regions;

[0014] The area of ​​the region is extracted, and a plurality of regions to be cut are established based on the area of ​​the region, and the plurality of regions to be cut are sorted according to the area sizes corresponding to the regions to be cut, so as to cut the interior of the plurality of regions in turn to obtain the plurality of chip units after segmentation.

[0015] Compared with the prior art, the beneficial effects of the present invention are: the image is recognized by the CCD and processed into the grayscale image, and the presence of dark cracks is detected by grayscale difference. In the case of dark cracks, the wafer to be cut is partitioned and several of the areas are cut separately to prevent the original straight cutting path for the entire wafer from passing through the inside of the chip unit, thereby preventing the machine from cutting several chip units that are misaligned and misaligned due to dark cracks.

[0016] Furthermore, the wafer to be cut includes a DBR layer.

[0017] Furthermore, before the step of placing the wafer to be cut on the glass stage and acquiring the grayscale image of the wafer to be cut by the CCD, the wafer to be cut includes a plurality of chip units, the step includes:

[0018] Providing a reference wafer with a dark crack, and acquiring a reference grayscale image of the reference wafer through the CCD;

[0019] According to the position and shape of the dark crack in the reference wafer, obtaining the grayscale value of the dark crack from the reference grayscale image;

[0020] A first maximum grayscale value is obtained from the reference grayscale image, and a grayscale difference threshold is established based on the dark crack grayscale value and the first maximum grayscale value.

[0021] Furthermore, the step of judging whether the wafer to be cut has dark cracks based on the grayscale image includes:

[0022] Obtaining a second maximum grayscale value from the grayscale image;

[0023] Based on the second maximum grayscale value and the grayscale difference threshold, it is determined whether the wafer to be cut has dark cracks.

[0024] Furthermore, after the step of judging whether the wafer to be cut has dark cracks based on the grayscale image, the method further includes:

[0025] If there is no hidden crack, the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after being divided.

[0026] Furthermore, after the step of obtaining the personnel instruction and determining the instruction type of the personnel instruction, wherein the instruction type includes the first instruction and the second instruction, the method further includes:

[0027] If the personnel instruction is the second instruction, the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after being divided.

[0028] Furthermore, the step of establishing a regional boundary line based on the dark crack line segment and the plurality of cutting paths includes:

[0029] Determine whether the dark crack line segment and a plurality of the cutting paths intersect;

[0030] If there is an intersection, a plurality of cutting paths to be connected are established from the plurality of cutting paths intersecting with the dark crack line segment;

[0031] A plurality of the to-be-connected cutting streets and the dark crack line segments are combined into a region boundary line.

[0032] Furthermore, the step of establishing a plurality of regions to be cut based on the area of ​​the region includes:

[0033] extracting a total area of ​​the wafer to determine an area threshold according to the total area;

[0034] The areas of the plurality of regions are respectively compared with the area threshold to select a region to be cut from the plurality of regions.

[0035] Furthermore, the ratio of the area threshold to the total area is 0.2:1.

[0036] An embodiment of the present invention further provides a chip unit, which is formed by cutting based on the partition cutting method based on wafer dark cracking as described in the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a flowchart of a partition cutting method based on wafer dark crack in the first embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of the structure of the glass stage and the CCD in the partition cutting method based on wafer dark crack in the first embodiment of the present invention;

[0039] Figure 3 A schematic diagram of chip arrangement of a wafer to be cut in a partition cutting method based on wafer dark cracking in the first embodiment of the present invention;

[0040] Figure 4 It is a partial schematic diagram of a wafer to be cut in a partition cutting method based on wafer dark crack in the first embodiment of the present invention;

[0041] Figure 5 It is a schematic diagram of dividing a plurality of regions in the zoning and cutting method based on wafer dark crack in the first embodiment of the present invention;

[0042] Figure 6 Another schematic diagram of dividing a plurality of regions in the zoning and cutting method based on wafer dark cracks in the first embodiment of the present invention;

[0043] Description of main component symbols:

[0044] Glass stage 100 light source 110 CCD 200 Fixed bracket 210 Wafer to be cut 300 First Area 301 Second area 302 Chip unit 310 The first sub-chip 311 The second sub-chip 312 Cutting Road 320 The first dividing line 410 The second dividing line 420 The third dividing line 430

[0045] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0046] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0047] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0049] See also Figures 1 to 6 The partition cutting method based on wafer dark crack in the embodiment of the present invention comprises the following steps:

[0050] Step S10: providing a glass stage and a CCD, and setting a light source in the glass stage;

[0051] Preferably, see Figure 2 The CCD200 is a wide-angle CCD connected to a fixing frame 210, located directly above the wafer area in the glass carrier 100, and corresponding to the position of the light source 110. The light source 110 illuminates the wafer, which can enhance the grayscale difference of the image collected by the CCD200 and make the dark crack more obvious.

[0052] Step S20: placing a wafer to be cut on the glass stage, and acquiring a grayscale image of the wafer to be cut through the CCD, wherein the wafer to be cut includes a plurality of chip units;

[0053] Preferably, see Figure 3 There are gaps between the adjacent chip units 320 on the wafer 300 to be cut, and the gaps can form cutting paths for cutting. The cutting path is planned according to the gaps, usually an S-shaped reciprocating cutting path, and is divided into horizontal and vertical S-shaped paths, that is, reciprocating from left to right and reciprocating from top to bottom, and finally the wafer 300 to be cut is divided into a plurality of rectangular chip units 320.

[0054] Specifically, the wafer to be cut includes a DBR layer.

[0055] Preferably, the DBR layer is located on the back side of the wafer 300 to be cut. When the wafer 300 to be cut is placed on the glass carrier 100, the light source 110 illuminates the wafer 300 to be cut. The DBR layer prevents light from passing through, and displays black when identifying a grayscale image. If there is a crack, light passes through, and a white line is formed in the cracked area. It can be understood that the DBR layer is beneficial for more accurate identification and detection of dark cracks on the wafer.

[0056] Before step S20, the method includes:

[0057] S210: providing a reference wafer with dark cracks, and acquiring a reference grayscale image of the reference wafer through the CCD;

[0058] Preferably, a computer with determination software is used to communicate with the CCD200 to determine the result of the CCD200 identification. Therefore, it is necessary to provide cases that conform to the actual situation to provide a basis for the software to determine whether there is a hidden crack and prevent misjudgment or missed judgment.

[0059] S220: Acquire a dark crack grayscale value from the reference grayscale image according to the position and shape of the dark crack in the reference wafer;

[0060] It is understandable that data associated with actual dark cracks are acquired and recorded.

[0061] S230: Obtain a first maximum grayscale value from the reference grayscale image, and establish a grayscale difference threshold based on the dark crack grayscale value and the first maximum grayscale value.

[0062] Preferably, due to the DBR layer, the area with the first maximum grayscale value is the black area without cracks in the reference wafer. Since the width of the dark cracks in actual situations is different, the brightness of the transmitted light is different. If the width of the dark crack to be determined is larger, larger than the dark crack in the reference wafer, the grayscale value in the formed image will be smaller than the dark crack grayscale value, and the grayscale difference with the area without dark cracks is large. Similarly, if the width of the dark crack to be determined is smaller, smaller than the dark crack in the reference wafer, it will still affect the wafer quality and cutting accuracy, and the light transmitted is less, then the grayscale value in the formed image will be larger than the dark crack grayscale value, and the grayscale difference with the area without dark cracks is small. Therefore, setting the grayscale difference threshold is helpful to identify more types of dark cracks, and the grayscale difference threshold can be manually adjusted to the optimal in actual detection.

[0063] Step S30: judging whether the wafer to be cut has dark cracks based on the grayscale image, and if so, establishing one or more dark crack line segments from the grayscale image;

[0064] By identifying the grayscale image and reading the grayscale difference of the areas with inconsistent grayscale, dark cracks can be identified, and the distribution pattern and position of the dark cracks can be specifically identified, which can be used as a basis for cutting in subsequent processes. Preferably, the computer used to identify the grayscale image can alarm to remind the operator of the existence of dark cracks.

[0065] Specifically, the step S30 includes:

[0066] S310: Obtaining a second maximum grayscale value from the grayscale image;

[0067] It can be understood that the area with the second maximum grayscale value is an area without cracks, and the second maximum grayscale value is used to provide a standard for determining whether there are dark cracks in an area with inconsistent grayscale values.

[0068] S320: judging whether the wafer to be cut has dark cracks based on the second maximum grayscale value and the grayscale difference threshold;

[0069] It is understandable that due to errors in materials and processing, the maximum grayscale value of each wafer is not completely consistent. The grayscale difference threshold is used to determine whether dark cracks exist with higher accuracy and wider versatility.

[0070] S330: If there is no hidden crack, the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after being divided.

[0071] See also Figure 3 and Figure 4 If there is no hidden crack in the wafer 300 to be cut, all the cutting paths 320 are arranged in straight lines, and the wafer 300 to be cut is cut back and forth horizontally and vertically according to the S-shaped route in the figure. The cutting path is directly determined by the specifications, parameters, arrangement of the chip array, etc. of the wafer 300 to be cut, so as to divide the wafer 300 to be cut into a plurality of rectangular chip units 310.

[0072] Step S40: obtaining a personnel instruction, and determining the instruction type of the personnel instruction, wherein the instruction type includes a first instruction and a second instruction;

[0073] Preferably, when the software indicates the presence of hidden cracks, an operation option is provided to the staff, asking whether to enable the partition cutting mode. If the partition cutting mode is enabled, the first instruction is passed; if the partition cutting mode is not enabled, the second instruction is passed.

[0074] Specifically, after step S40, the method further includes:

[0075] S410: If the personnel instruction is the second instruction, the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after being divided.

[0076] Preferably, if the staff chooses not to enable partition cutting, the wafer 300 to be cut is directly cut according to the original S-shaped route.

[0077] Step S50: if the personnel instruction is the first instruction, then based on the positions of the plurality of chip units, a plurality of cutting lanes are acquired, wherein the cutting lanes are located between adjacent chip units;

[0078] Preferably, partition cutting is enabled, and the positions and shapes of dark cracks and the cutting paths 320 around the dark cracks are extracted to partition the wafer 300 to be cut.

[0079] Step S60: establishing a region boundary line based on the dark crack line segment and the plurality of cutting streets to divide the wafer to be cut into a plurality of regions;

[0080] Preferably, see Figure 4 and Figure 5When the wafer 300 to be cut has a dark crack, the chip unit 310 with the dark crack is divided into a first sub-chip 311 and a second sub-chip 312. Since the dark crack has a certain width, the first sub-chip 311 and the second sub-chip 312 are misaligned, resulting in the chip unit 310 with the dark crack no longer presenting a complete rectangle, and the cutting road 320 around the chip unit 310 with the dark crack is also misaligned. If the wafer 300 to be cut is cut according to the original S-shaped route, refer to Figure 4 From the B end to the C end and from the D end to the E end, the inside of the second sub-chip 312 will be cut, and affected by the dark cracks, the misalignment of the cutting path 320 affects the units around the chip unit 310 with dark cracks. Cutting according to the original S-shaped route will also lead to damage of the surrounding units, resulting in a large amount of losses.

[0081] Specifically, the step S60 includes:

[0082] S610: Determine whether the dark crack line segment and a plurality of the cutting paths intersect;

[0083] S620: If there is an intersection, a plurality of cutting paths to be connected are established from the plurality of cutting paths intersecting with the dark crack line segment;

[0084] S630: Combining a plurality of the to-be-connected cutting streets and the dark crack line segments into a region boundary line.

[0085] Preferably, S610 to S630, please refer to Figure 5 When there is a dark crack in the wafer 300 to be cut, the chip unit 310 on the wafer 300 to be cut is obliquely misaligned, and the planned regional boundary divides the wafer 300 to be cut into a first area 301 and a second area 302. The regional boundary includes a first boundary 410, a second boundary 420 and a third boundary 430, wherein the first boundary 410 is the dark crack line segment, which is planned as a part of the regional boundary through the grayscale image recognition and the software, and the second boundary 420 and the third boundary 430 are respectively The third dividing lines 430 are all connected to the first dividing lines 410, and are taken from several of the cutting lanes 320 around the chip unit 310 with hidden cracks, thereby overcoming the phenomenon of misalignment of the cutting lanes. The end of the second dividing line 420 away from the first dividing line 410 and the end of the third dividing line 430 away from the first dividing line 410 are both extended according to the arrangement of the chip unit array on the wafer 300 to be cut. Specifically, they are planned according to the other cutting lanes 320 arranged in a straight line until the edge of the wafer 300 to be cut.

[0086] Step S70: extract the area of ​​the region, establish a number of regions to be cut based on the area of ​​the region, sort the regions to be cut according to the area size corresponding to the regions to be cut, and cut the inside of the regions in turn to obtain the divided chip units.

[0087] Preferably, see Figure 5 , the area of ​​the first region 301 is larger than that of the second region 302, and there are more intact chip units 310 in the first region 301. The first region 301 is cut first to ensure the cutting quality of the chips in the region. After partitioning, each region is cut separately, specifically, cutting reciprocatingly according to an S-shaped route. For example, in the first region 301, cutting is performed horizontally from left to right, and stops at the regional dividing line, and then the direction is reversed and cutting is performed from right to left. Further, when cutting to the first sub-chip 311, the cutting path stops at the connection between the first dividing line 410 and the third dividing line 430, and the direction is reversed. Starting from the connection between the first dividing line 410 and the second dividing line 420, cutting continues to the left, which can prevent the second sub-chip 312 and the units adjacent to the second sub-chip 312 from being damaged. Please refer to Figure 6 , a partitioning method is provided if there are two dark cracks. It can be understood that in the partitioning cutting method based on wafer dark cracks, several of the areas are cut separately to prevent several straight cutting paths in the S-shaped general route for the entire wafer from passing through the inside of the chip unit 310, thereby preventing the machine from cutting several chip units 310 that are misaligned and misaligned due to dark cracks.

[0088] Specifically, the step S70 includes:

[0089] S710: extracting the total area of ​​the wafer to determine an area threshold according to the total area;

[0090] S720: Compare the areas of the plurality of regions with the area threshold respectively to select a region to be cut from the plurality of regions.

[0091] S730: The ratio of the area threshold to the total area is 0.2:1.

[0092] Preferably, in S710 to S730, if there is a region whose area is smaller than 20% of the total area, it will not be cut. When the cutting of the wafer 300 to be cut is completed, the material is automatically returned and the cutting of the next wafer is continued automatically.

[0093] A second embodiment of the present invention provides a chip unit, which is formed by cutting based on the partition cutting method based on wafer dark cracking as described in the above embodiment.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A partition cutting method based on wafer dark crack, characterized in that: The steps include: Providing a glass stage and a CCD, and arranging a light source in the glass stage; Placing a wafer to be cut on the glass stage, and acquiring a grayscale image of the wafer to be cut through the CCD, wherein the wafer to be cut includes a plurality of chip units; Determining whether the wafer to be cut has dark cracks based on the grayscale image, and if so, establishing one or more dark crack line segments from the grayscale image; Obtaining a personnel instruction, and determining an instruction type of the personnel instruction, wherein the instruction type includes a first instruction and a second instruction; If the personnel instruction is the first instruction, based on the positions of the plurality of chip units, a plurality of cutting lanes are acquired, wherein the cutting lanes are located between adjacent chip units; Based on the dark crack line segments and the plurality of cutting streets, establishing regional demarcation lines to divide the wafer to be cut into a plurality of regions; The area of ​​the region is extracted, and a plurality of regions to be cut are established based on the area of ​​the region, and the plurality of regions to be cut are sorted according to the area sizes corresponding to the regions to be cut, so as to cut the interior of the plurality of regions in turn to obtain the plurality of chip units after segmentation.

2. The zoning cutting method based on wafer dark crack according to claim 1 is characterized in that: The wafer to be cut comprises a DBR layer.

3. The zoning cutting method based on wafer dark crack according to claim 1 is characterized in that: Before the step of placing the wafer to be cut on the glass stage and acquiring the grayscale image of the wafer to be cut by the CCD, wherein the wafer to be cut includes a plurality of chip units, the step includes: Providing a reference wafer with a dark crack, and acquiring a reference grayscale image of the reference wafer through the CCD; According to the position and shape of the dark crack in the reference wafer, obtaining the grayscale value of the dark crack from the reference grayscale image; A first maximum grayscale value is obtained from the reference grayscale image, and a grayscale difference threshold is established based on the dark crack grayscale value and the first maximum grayscale value.

4. The zoning cutting method based on wafer dark crack according to claim 3 is characterized in that: The step of judging whether the wafer to be cut has dark cracks based on the grayscale image comprises: Obtaining a second maximum grayscale value from the grayscale image; Based on the second maximum grayscale value and the grayscale difference threshold, it is determined whether the wafer to be cut has dark cracks.

5. The zoning cutting method based on wafer dark crack according to claim 1 is characterized in that: After the step of judging whether the wafer to be cut has dark cracks based on the grayscale image, the method further includes: If there is no hidden crack, the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after being divided.

6. The method for zoning and cutting based on wafer dark crack according to claim 1, characterized in that: After the step of obtaining the personnel instruction and determining the instruction type of the personnel instruction, wherein the instruction type includes the first instruction and the second instruction, the method further includes: If the personnel instruction is the second instruction, the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after being divided.

7. The zoning cutting method based on wafer dark crack according to claim 1 is characterized in that: The step of establishing a regional boundary line based on the dark crack line segment and the plurality of cutting paths comprises: Determine whether the dark crack line segment and a plurality of the cutting paths intersect; If there is an intersection, a plurality of cutting paths to be connected are established from the plurality of cutting paths intersecting with the dark crack line segment; A plurality of the to-be-connected cutting streets and the dark crack line segments are combined into a region boundary line.

8. The method for zoning and cutting based on wafer dark crack according to claim 1, characterized in that: The step of establishing a plurality of regions to be cut based on the area of ​​the region comprises: extracting a total area of ​​the wafer to determine an area threshold according to the total area; The areas of the plurality of regions are respectively compared with the area threshold to select a region to be cut from the plurality of regions.

9. The zoning cutting method based on wafer dark crack according to claim 8, characterized in that: The ratio of the area threshold to the total area is 0.2:

1.

10. A chip unit, characterized in that: The chip unit is formed by cutting based on the partition cutting method based on wafer dark cracking as described in any one of claims 1 to 9.

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