Semiconductor structure, semiconductor element with air interstice and preparation method thereof

Abstract

The invention provides a semiconductor element. The semiconductor element comprises a substrate, a first dielectric layer, a conductive layer and an insulating cover layer, the first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The conductive layer includes a plurality of conductive lines. The insulating cover layer is disposed on the conductive layer and is configured to enclose a plurality of first gaps between the conductive lines to form a plurality of air spacers.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 18 / 375,617 (i.e., the priority date is "October 2, 2023"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor element, and more particularly to a semiconductor structure, a semiconductor element and a method for manufacturing the same. Background Art

[0004] With the rapid development of the electronics industry, semiconductor components are getting smaller while providing more functions and more integrated circuits. However, as the size decreases, the spacing between metal wires set on the same dielectric layer also becomes smaller, resulting in more serious coupling effects between metal wires, increased electromagnetic noise and crosstalk.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0006] An embodiment of the present disclosure provides a semiconductor element, comprising a substrate, a first dielectric layer, a conductive layer, and an insulating cover layer. The first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The conductive layer includes a plurality of conductive wires. The insulating cover layer is disposed on the conductive layer and is configured to surround a plurality of first gaps between the conductive wires to form a plurality of air gaps.

[0007] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The method includes providing a semiconductor structure having a conductive layer disposed on a first upper surface of a lower portion of a first dielectric layer; etching an upper portion of the first dielectric layer to expose a plurality of conductive lines of the conductive layer; and forming an insulating cap layer on a second upper surface of the conductive layer to form a plurality of air gaps.

[0008] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first dielectric layer, a plurality of wires, and a plurality of air gaps. The first dielectric layer is disposed on the substrate. The plurality of wires are disposed on the first dielectric layer. The plurality of air gaps are disposed at a plurality of first gaps between the wires along the lateral direction of the wires.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0011] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 2 is a graph schematically illustrating various delays of different generations of technology nodes of some embodiments of the present disclosure.

[0013] Figures 3A to 3G is a schematic cross-sectional view illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure.

[0014] Figure 4 It is a schematic flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure.

[0015] Description of reference numerals:

[0016] 100: Semiconductor components

[0017] 102: Base

[0018] 102s1: Upper surface

[0019] 104: Dielectric layer

[0020] 104a: lower part

[0021] 104a1: Upper surface

[0022] 104b: upper part

[0023] 106: Conductive layer

[0024] 1061: Wire

[0025] 1061a: Wire

[0026] 1061a1: Upper surface

[0027] 1061b: Wire

[0028] 1061b1: Upper surface

[0029] 1061s1: Top surface

[0030] 106s1: Upper surface

[0031] 107: Gap

[0032] 108a: Conductive element

[0033] 108a1: Upper surface

[0034] 108b: Conductive element

[0035] 108b1: Upper surface

[0036] 109: Gap

[0037] 110: Gate Oxide

[0038] 111: Gate terminal

[0039] 112a: Insulation gap

[0040] 112b: Insulation spacer

[0041] 113: Gate structure

[0042] 120: First insulation layer

[0043] 120': Remaining first insulation layer

[0044] 122: Dielectric layer

[0045] 122': remaining second dielectric layer

[0046] 124: Second insulation layer

[0047] 124': Remaining second insulation layer

[0048] 124s1: Upper surface

[0049] 126: Insulation cover layer

[0050] 130: Gap

[0051] 132: Air gap

[0052] 202: Curve

[0053] 204: Curve

[0054] 206: Curve

[0055] 208: Curve

[0056] 210: Curve

[0057] 300a: Semiconductor Structure

[0058] 300b: Semiconductor Structure

[0059] 300c: Semiconductor structure

[0060] 300d: Semiconductor structure

[0061] 300e: Semiconductor Structure

[0062] 300g: Semiconductor structure

[0063] 400: Preparation method

[0064] 402: Steps

[0065] 404: Steps

[0066] 406: Steps

[0067] 408: Steps

[0068] 410: Steps

[0069] 412: Steps

[0070] 414: Steps

[0071] 416: Steps

[0072] d1: first thickness

[0073] d2: second thickness DETAILED DESCRIPTION

[0074] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0075] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0076] References throughout this specification to "an example" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0077] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0078] In addition, for ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatial relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0079] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0080] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, it may be formed directly or indirectly on the other element or layer. That is, for example, there may be intermediate elements or layers. In contrast, when an element or layer is referred to as being "formed directly on" another element, there are no intermediate elements or layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0081] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0082] like Figure 1 As shown, a semiconductor device 100 is provided or received. In some embodiments, the semiconductor device 100 may be or include a portion of an integrated circuit (IC) die, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other appropriate IC components, or combinations thereof.

[0083] The semiconductor device 100 may include a substrate 102, a dielectric layer 104 and a conductive layer 106. Figure 1As shown. The substrate 102 may include a semiconductor substrate such as a silicon substrate. In some embodiments, the substrate 102 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 102 may include a compound semiconductor, such as gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. In some embodiments, the substrate 102 may include an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP. Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods.

[0084] Additionally, substrate 102 may be part of an integrated circuit (IC) die that includes various passive and active microelectronic elements, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0085] Depending on the IC manufacturing stage, the substrate 102 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For example, a dielectric layer 104 may be formed over the substrate 102, such as Figure 1 In some embodiments, the dielectric layer 104 may be silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), carbon oxynitride (SiOCN), other suitable dielectric materials, or combinations thereof.

[0086] For clarity, it has been simplified Figure 1 It should be understood that additional features may be added to the substrate 102, and that some of the features described herein may be replaced, modified, or eliminated in other embodiments.

[0087] In some embodiments, the dielectric layer 104 may include an upper portion 104b and a lower portion 104a. During the manufacture of the semiconductor device 100, the lower portion 104a of the dielectric layer 104 may be formed on the substrate 102, and the conductive layer 106 may be formed on the upper surface 104a1 of the lower portion 104a of the dielectric layer 104. After forming the conductive layer 106, the upper portion 104b of the dielectric layer 104 may be formed on the conductive layer 106, so that the conductive layer 106 may be embedded in the dielectric layer 104, as shown in FIG. Figure 1 In some embodiments, the upper portion 104b and the lower portion 104a may also be referred to as an upper dielectric layer and a lower dielectric layer, respectively.

[0088] The conductive layer 106 may include a plurality of conductive lines 1061, 1061a, and 1061b, which may be signal lines, such as word lines or bit lines, of the semiconductor device 100. The conductive lines 1061, 1061a, and 1061b may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (such as titanium nitride), transition metal aluminides, or combinations thereof.

[0089] In some embodiments, the wire 1061a may electrically contact a conductive element 108a, and the wire 1061b may electrically contact a conductive element 108b. Figure 1 As shown. For example, an upper surface 108a1 of the conductive element 108a may be substantially coplanar with an upper surface 108b1 of the conductive element 108b and an upper surface 104a1 of the lower portion 104a of the dielectric layer 104. In addition, the upper surface 108a1 of the conductive element 108a, the upper surface 108b1 of the conductive element 108b, and the upper surface of the lower portion 104a of the dielectric layer 104 may have substantially the same height relative to the upper surface 102s1 of the substrate 102.

[0090] In some embodiments, the wire 1061a may partially cover the upper surface 108a1 of the conductive element 108a. In some embodiments, the wire 1061a may completely cover the upper surface 108a1 of the conductive element 108a. In some embodiments, a portion of the wire 1061b may partially cover the upper surface 108b1 of the conductive element 108b. In some embodiments, the wire 1061b may completely cover the upper surface 108b1 of the conductive element 108b.

[0091] The conductive elements 108a and 108b may be metal or metal alloys, such as aluminum, copper or alloys thereof. The conductive elements 108a and 108b may penetrate the lower portion 104a of the dielectric layer 104 , and a portion of the conductive elements 108a and 108b may protrude downward through the dielectric layer 104 .

[0092] In some embodiments, the conductive layer 106 may be the bottommost conductive layer (e.g., M0) in the integrated circuit, and one or more dielectric layers including the conductive layer may be formed on the dielectric layer 104. In addition, the conductive layer 106 may be electrically connected to the conductive layer disposed in the upper dielectric layer via one or more conductive vias (not shown).

[0093] In some embodiments, a gate oxide 110 may be formed on the upper surface 120s1 of the substrate 102. The gate oxide 110 may be a dielectric layer that connects a gate terminal (or gate electrode) 111 of a transistor to underlying source and drain terminals ( Figure 1 The gate oxide 110 is formed by thermal oxidation of silicon of the channel to form a thin silicon dioxide insulating layer with a thickness of between 5 nm and 200 nm, but the present disclosure is not limited thereto.

[0094] In some embodiments, the gate terminal 111 may also be considered as a “gate metal” or a “gate conductor”. The gate terminal 111 may be a thin electrode layer of a conductor, and the conductor may be a composite of polysilicon, silicide material, and metal, such as WN, TiN, or TaN, but the disclosure is not limited thereto. In some embodiments, the gate oxide 110 and the gate terminal 111 may have substantially the same width, and the side surfaces of the gate oxide 110 and the gate terminal 111 may be coplanar. In some embodiments, the gate oxide 110 and the gate terminal 111 may be collectively referred to as a gate structure (GS) 113.

[0095] In some embodiments, an insulating spacer 112a may be formed at a gap between a side surface of the conductive element 108a and the gate structure 113, and another insulating spacer 112a may be formed at a gap between a side surface of the conductive element 108b and the gate structure 113. In some embodiments, the insulating spacers 112a and 112b may be an insulating material, such as silicon oxide, silicon nitride, etc., but the present disclosure is not limited thereto.

[0096] In some embodiments, electromagnetic noise and / or crosstalk may exist between the wires 1061, 1061a, and 1061b. As the size of the semiconductor device 100 decreases, the size and / or pitch of the wires 1061, 1061a, and 1061b may become smaller, and the electromagnetic noise or crosstalk between them may become more serious, resulting in higher resistance capacitance (RC) delay and reduced performance of the semiconductor device 100. Higher RC delay may cause timing errors in digital circuits and cause signal distortion in analog circuits.

[0097] Figure 2 is a graph schematically illustrating various delays of different generations of technology nodes of some embodiments of the present disclosure.

[0098] In some embodiments, the delay of a given wire can be expressed by the following formula (1).

[0099]

[0100] Wherein ρ represents the resistivity of the wire; ε0 represents the absolute dielectric constant of free space, κ represents the dielectric constant of the dielectric material between the wires, L represents the length of the wire, T represents the thickness of the wire, and P represents the width of the wire. In some embodiments, ρ may also be referred to as the resistivity, and κ may also be referred to as the capacitance.

[0101] In some embodiments, the conductive layer 106 may be copper (e.g., having a lower resistivity) to reduce the resistance of the conductive lines 1061, 1061a, and 1061b. In addition, the dielectric layer 104 may be implemented using a low-K dielectric material (e.g., having a lower capacitance), where K refers to a dielectric constant. For example, the low-K dielectric material may be a material having a small dielectric constant (e.g., K is approximately equal to 2) relative to silicon dioxide (e.g., K=4.0).

[0102] like Figure 2 As shown, curve 206 shows the gate delay of different generations of technology nodes from 650nm to 100nm, and the gate delay decreases as the size of the technology node decreases. Curves 204 and 202 respectively show the interconnect delay and the total delay using aluminum as the wire and silicon oxide as the dielectric material formed at the gap between the wires. Figure 2 As shown, when the technology node size decreases, the interconnection delay increases rapidly, and when the technology node changes from 650nm to 250nm, the total delay decreases. However, when the technology node size decreases, the total delay and the interconnection delay will increase rapidly. As used herein, the term "technology node" (or "wafer node", "process node", "process technology node" or "node") refers to a parameter in a specific semiconductor manufacturing process and its design rules. For example, the technology node used here can be defined by a minimum gate width of a chip. A smaller technology node corresponds to smaller features, and smaller features correspond to smaller transistors.

[0103] Curves 210 and 208 show the interconnect delay and the total delay, respectively, using copper as the conductive lines and using a low-K material as the dielectric material formed at the gaps between the conductive lines.

[0104] Figures 3A to 3G is a cross-sectional schematic diagram illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure. Figure 1 and Figures 3A to 3G .

[0105] In one embodiment, providing Figure 1 The semiconductor device 100 is shown in FIG. 1 , and a post-etching process is performed thereon to remove the upper portion 104b of the dielectric layer 104, so that the conductive layer 106 (ie, including the conductive lines 1061, 1061a, and 1061b) and a portion of the upper surface 104a1 to 104a of the lower portion are exposed. Figure 3A As shown in the semiconductor structure 300a.

[0106] Please refer to Figure 3B , a first insulating layer 120 may be formed on Figure 3A The first insulating layer 120 is formed on the conductive lines 1061, 1061a and 1061b and the gaps 107 therebetween in the semiconductor structure 300a shown. In some embodiments, the manufacturing technology of the first insulating layer 120 may include a thermal oxidation process, a chemical or physical vapor deposition process, or other appropriate technology. In some embodiments, the thickness of the first insulating layer 120 may be substantially the same. The first insulating layer 120 may include an insulating material, such as silicon nitride, but the present disclosure is not limited thereto.

[0107] Please refer to Figure 3C , a dielectric layer 122 may be formed on Figure 3B The dielectric layer 122 is formed on the first insulating layer 120 of the semiconductor structure 300b shown. In some embodiments, the manufacturing technology of the dielectric layer 122 may include a thermal oxidation process, a chemical or physical vapor deposition process, or other appropriate technology. In some embodiments, the thickness of the dielectric layer 122 may be substantially the same. The dielectric layer 122 may include a dielectric material, such as silicon oxide or other appropriate materials.

[0108] Please refer to Figure 3D , a second insulating layer 124 may be formed on Figure 3C The second insulating layer 124 is formed on the dielectric layer 122 of the semiconductor structure 300c shown. In some embodiments, the manufacturing technology of the second insulating layer 124 may include a thermal oxidation process, a chemical or physical vapor deposition process, or other appropriate technology. In some embodiments, the second insulating layer 124 may fill the gap 109 along the lateral direction of the conductive lines 1061, 1061a and 1061b, and the upper surface 124s1 of the second insulating layer 124 may be substantially flush with and parallel to the upper surface 120s1 of the substrate 102. In addition, the second insulating layer 124 may have a first thickness d1 relative to the upper surface 104a1 of the lower portion 104a of the dielectric layer 104. The second insulating layer 124 may include an insulating material, such as silicon nitride, but the present disclosure is not limited thereto.

[0109] Please refer to Figure 3E , can be ground Figure 3DThe second insulating layer 124 of the semiconductor structure 300d is polished to expose the conductive lines 1061, 1061a, and 1061b. In some embodiments, the second insulating layer 124 can be polished using chemical mechanical polishing (CMP) to expose the upper surfaces 1061s1, 1061a1, and 1601b1 of the conductive lines 1061, 1061a, and 1061b. In addition, the upper ends of the first insulating layer 120 and the dielectric layer 122 are also exposed. The polished second insulating layer 124 can have a second thickness d2 relative to the upper surface 104a1 of the lower portion 104a of the dielectric layer 104. The second thickness d2 is less than the first thickness d1.

[0110] Please refer to Figure 3F , Etching Figure 3E The dielectric layer 122 of the semiconductor structure 300e shown in FIG. 1 forms a plurality of gaps 130 between the conductive lines 1061, 1061a, and 1061b. In some embodiments, the gaps 130 may also be referred to as sidewall gaps along the lateral direction of the conductive lines 1061, 1061a, and 1061b. In some embodiments, the dielectric layer 122 may be etched using a vapor etching process. In some other embodiments, the dielectric layer 122 may be etched using a dry etching process or a wet etching process, but the present disclosure is not limited thereto.

[0111] refer to Figure 3G , an insulating cap layer 126 can be formed on the upper surface 106s1 of the conductive layer 106 to surround the gap 130, thereby forming a plurality of air gaps 132. In some embodiments, the air gaps 132 can also be referred to as sidewall gaps of the conductive lines 1061, 1061a, and 1061b. For example, each air gap 132 can be surrounded by the insulating cap layer 132, the remaining first insulating layer 120', the remaining second dielectric layer 122', and the remaining second insulating layer 124'.

[0112] In some embodiments, air has the lowest dielectric constant, which is approximately equal to 1. The air gaps 132 formed along the lateral direction (i.e., the sidewalls) of the conductive lines can significantly reduce electromagnetic noise and crosstalk between the conductive lines 1061, 1061a, and 1061b. In some embodiments, the semiconductor structure 300g can be regarded as a semiconductor element including a plurality of sidewall gaps disposed between the conductive lines.

[0113] Figure 4 is a flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure. Figure 1 , Figures 3A-3G and Figure 4 .

[0114] In step 402, a semiconductor structure (eg, Figure 1The semiconductor device 100 shown in FIG. 1 includes a conductive layer (e.g., a conductor layer 106) disposed on an upper surface (e.g., an upper surface 104a1) of a lower portion (e.g., a lower portion 104a) of a first dielectric layer (e.g., a dielectric layer 104). In some embodiments, the first dielectric layer 104 of the semiconductor device 100 may include an upper portion 104b and a lower portion 104a, and the conductive layer 106 may be buried between the upper portion 104b and the lower portion 104a. In some other embodiments, the semiconductor device 100 may not include the upper portion 104b of the dielectric layer 104, and the conductive layer 106 may be formed on the upper surface 104a1 of the lower portion 104a of the dielectric layer 104.

[0115] In step 404, an upper portion of the first dielectric layer (e.g., upper portion 104b) is removed to expose the conductive wires (e.g., conductive wires 1061, 1061a, and 1061b) of the conductive layer. In some embodiments, the upper portion of the first dielectric layer may be removed by performing a dry etching, wet etching, or vapor etching process, but the present disclosure is not limited thereto. In addition, after removing the upper portion, the conductive layer 106 (i.e., including conductive wires 1061, 1061a, and 1061b) and a portion of the upper surface 104a1 of the lower portion 104a are exposed, as shown in FIG. Figure 3A As shown in the semiconductor structure 300a.

[0116] In step 406, a first insulating layer (eg Figure 3B The first insulating layer 120 in the embodiment of the present invention is formed on the conductive lines and the first gaps therebetween (e.g., gaps 107). In some embodiments, the manufacturing technology of the first insulating layer 120 may include a thermal oxidation process, a chemical or physical vapor deposition process, or other appropriate technology. The first insulating layer 120 may include an insulating material, such as silicon nitride, but the present disclosure is not limited thereto.

[0117] In step 408, a second dielectric layer (eg, Figure 3C The dielectric layer 120 shown is formed on the first insulating layer. In some embodiments, the manufacturing technology of the dielectric layer 122 may include a thermal oxidation process, a chemical or physical vapor deposition process, or other suitable technology. The dielectric layer 122 may include a dielectric material, such as silicon oxide or other suitable materials.

[0118] In step 410, a second insulating layer (eg, Figure 3DThe second insulating layer 124 shown is formed on the second dielectric layer. In some embodiments, the manufacturing technology of the second insulating layer 124 may include a thermal oxidation process, a chemical or physical vapor deposition process, or other appropriate technology. In some embodiments, the gap 109 may refer to a gap in the dielectric layer 122 along the lateral direction. The second insulating layer 124 may fill the gap 109 in the lateral direction. The upper surface 124s1 of the second insulating layer 124 may be substantially flush and parallel to the upper surface 120s1 of the substrate 102. In addition, the second insulating layer 124 may have a first thickness d1 relative to the upper surface 104a1 of the lower portion 104a of the dielectric layer 104. The second insulating layer 124 may include an insulating material, such as silicon nitride, but the present disclosure is not limited thereto.

[0119] In step 412, the second insulating layer (eg Figure 3D The second insulating layer 124 shown in the figure is polished to expose the wire, the first insulating layer and the second dielectric layer. In some embodiments, a chemical mechanical polishing (CMP) process can be used to polish the second insulating layer 124 so as to expose the upper surfaces 1061s1, 1061a1, 1601b1 of the wires 1061, 1061a and 1061b. In addition, the upper ends of the first insulating layer 120 and the dielectric layer 122 are also exposed. The polished second insulating layer 124 can have a second thickness d2 relative to the upper surface 104a1 of the lower portion 104a of the dielectric layer 104. The second thickness d2 is less than the first thickness d1.

[0120] In step 414, the second dielectric layer (eg, Figure 3E , to obtain a plurality of second gaps between the conductive lines (eg, Figure 3F In some embodiments, the gap 130 may also be referred to as a sidewall gap along the lateral direction of the conductive lines 1061, 1061a, and 1061b. In some embodiments, a vapor phase etching process may be used to etch the dielectric layer 122. In some other embodiments, a dry etching process or a wet etching process may be used to etch the dielectric layer 122, but the present disclosure is not limited thereto.

[0121] In step 416, an insulating cover layer (e.g., Figure 3G The insulating cap layer 126 shown in FIG. 1 is formed on a second upper surface of the conductive layer (eg, Figure 3G The upper surface 106s1 shown in FIG. 1 is formed to surround the second gap, thereby forming a plurality of air gaps (eg, Figure 3G In some embodiments, air has the lowest dielectric constant, which is approximately equal to 1. Electromagnetic noise and crosstalk between the wires 1061, 1061a, and 1061b can be significantly reduced by the air gaps 132 along the lateral directions (ie, sidewalls) of the wires.

[0122] An embodiment of the present disclosure provides a semiconductor element, comprising a substrate, a first dielectric layer, a conductive layer, and an insulating cover layer. The first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The conductive layer includes a plurality of conductive wires. The insulating cover layer is disposed on the conductive layer and is configured to surround a plurality of first gaps between the conductive wires to form a plurality of air gaps.

[0123] In some embodiments, the semiconductor device further includes a first insulating layer disposed on the conductive lines.

[0124] In some embodiments, the semiconductor device further includes a second dielectric layer disposed on the first insulating layer.

[0125] In some embodiments, the semiconductor device further includes a second insulating layer disposed on the second dielectric layer and filling a plurality of second gaps of the second dielectric layer in a lateral direction.

[0126] In some embodiments, the second insulating layer, the first insulating layer, and the second dielectric layer above each first upper surface of the conductive layers are polished so that a remaining first insulating layer and a remaining second dielectric layer are exposed.

[0127] In some embodiments, the first upper surface of the conductive layer is coplanar with a second upper surface of the remaining second insulating layer, a third upper surface of the remaining first insulating layer, and a fourth upper surface of the remaining second dielectric layer.

[0128] In some embodiments, the second insulating layer, the first insulating layer, and the second dielectric layer are polished using a chemical mechanical polishing process.

[0129] In some embodiments, the remaining second dielectric layer is etched to form the plurality of first gaps.

[0130] In some embodiments, a vapor phase etching process is used to etch the remaining second dielectric layer.

[0131] In some embodiments, the second dielectric layer comprises silicon oxide

[0132] In some embodiments, the insulating cap layer, the first insulating layer, and the second insulating layer include a first insulating material.

[0133] In some embodiments, the first insulating material includes silicon nitride

[0134] In some embodiments, each air gap is surrounded by the insulating cap layer, the remaining first insulating layer, the remaining second dielectric layer, and the remaining second insulating layer.

[0135] In some embodiments, the semiconductor device further comprises a gate structure, a first conductive element, a second conductive element, a first spacer and a second spacer. The gate structure is disposed on an upper surface of the substrate. The first conductive element contacts a first conductive element among the conductive elements. The second conductive element contacts a second conductive element among the conductive elements. The first spacer is disposed between the first conductive element and the gate structure. The second spacer is disposed between the second conductive element and the gate structure.

[0136] In some embodiments, the first spacer and the second spacer include an insulating material.

[0137] In some embodiments, the gate structure includes a gate oxide and a gate terminal. The gate oxide is disposed on the upper surface of the substrate. The gate terminal is disposed on the gate oxide.

[0138] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The method includes the following steps: providing a semiconductor structure having a conductive layer disposed on a first upper surface of a lower portion of a first dielectric layer; etching an upper portion of the first dielectric layer to expose a plurality of conductive wires of the conductive layer; and forming an insulating cap layer on a second upper surface of the conductive layer to form a plurality of air gaps.

[0139] In some embodiments, after etching an upper portion of the first dielectric layer to expose the conductive lines of the conductive layer, the preparation method further includes the following steps: forming a first insulating layer on the conductive lines and a plurality of first gaps therebetween.

[0140] In some embodiments, after forming the first insulating layer on the conductive lines and the first gaps therebetween, the manufacturing method further includes the following steps: forming a second dielectric layer on the first insulating layer.

[0141] In some embodiments, after forming the second dielectric layer on the first insulating layer, the preparation method further includes the following steps: forming a second insulating layer on the second dielectric layer, wherein the second insulating layer fills multiple second gaps of the second dielectric layer along the lateral direction of the second dielectric layer.

[0142] In some embodiments, after forming the second insulating layer on the second dielectric layer, the preparation method further comprises the following steps: grinding the second insulating layer to expose the conductive lines, the first insulating layer, and the second dielectric layer.

[0143] In some embodiments, the second upper surface of the conductive layer is coplanar with a third upper surface of a remaining second insulating layer, a fourth upper surface of a remaining first insulating layer, and a fifth upper surface of a remaining second dielectric layer.

[0144] In some embodiments, after grinding the second insulating layer to expose the conductive lines, the first insulating layer, and the second dielectric layer, the preparation method further includes: etching the second dielectric layer to obtain a plurality of second gaps between the conductive lines.

[0145] In some embodiments, the manufacturing method further includes the following steps: forming the insulating cap layer on the second upper surface of the conductive layer to surround the second gaps to form the air gaps.

[0146] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first dielectric layer, a plurality of wires, and a plurality of air gaps. The first dielectric layer is disposed on the substrate. The plurality of wires are disposed on the first dielectric layer. The plurality of air gaps are disposed at a plurality of first gaps between the wires along the lateral direction of the wires.

[0147] In some embodiments, the semiconductor structure further includes a first insulating layer disposed on the conductive lines.

[0148] In some embodiments, the semiconductor structure further includes a second dielectric layer disposed on the first insulating layer.

[0149] In some embodiments, the semiconductor structure further includes a second insulating layer disposed on the second dielectric layer and filling a plurality of second gaps of the second dielectric layer in a lateral direction.

[0150] In some embodiments, the second insulating layer, the first insulating layer, and the second dielectric layer above each of the first upper surfaces of the conductive lines are polished to expose a remaining first insulating layer and a remaining second dielectric layer.

[0151] In some embodiments, the remaining second dielectric layer is etched to form a plurality of second gaps.

[0152] In some embodiments, the semiconductor structure further includes an insulating cap layer disposed on each of the first upper surfaces of the conductive lines and surrounding the second gaps to form the air gaps.

[0153] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0154] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a base; a first dielectric layer disposed on the substrate; a conductive layer disposed on the first dielectric layer, wherein the conductive layer comprises a plurality of conductive lines; as well as An insulating cover layer is disposed on the conductive layer and is configured to surround a plurality of first gaps between the plurality of conductive lines to form a plurality of air gaps. 2 . The semiconductor device as claimed in claim 1 , further comprising a first insulating layer disposed on the plurality of conductive lines. 3 . The semiconductor device as claimed in claim 2 , further comprising a second dielectric layer disposed on the first insulating layer. 4 . The semiconductor device as claimed in claim 3 , further comprising a second insulating layer disposed on the second dielectric layer and filling the second gaps of the second dielectric layer in a lateral direction. 5 . The semiconductor device as claimed in claim 4 , wherein the second insulating layer, the first insulating layer and the second dielectric layer above each first upper surface of the plurality of conductive layers are ground so as to expose a remaining first insulating layer and a remaining second dielectric layer. 6 . The semiconductor device as claimed in claim 5 , wherein the first upper surface of the conductive layer is coplanar with a second upper surface of the remaining second insulating layer, a third upper surface of the remaining first insulating layer, and a fourth upper surface of the remaining second dielectric layer. 7 . The semiconductor device as claimed in claim 6 , wherein the second insulating layer, the first insulating layer and the second dielectric layer are polished using a chemical mechanical polishing process. 8 . The semiconductor device as claimed in claim 6 , wherein the remaining second dielectric layer is etched to form the plurality of first gaps.

9. The semiconductor device as claimed in claim 8, wherein a vapor phase etching process is used to etch the remaining second dielectric layer.

10. The semiconductor device as claimed in claim 3, wherein the second dielectric layer comprises silicon oxide. 11 . The semiconductor device as claimed in claim 4 , wherein the insulating cap layer, the first insulating layer and the second insulating layer comprise a first insulating material. 12 . The semiconductor device as claimed in claim 11 , wherein the first insulating material comprises silicon nitride. 13 . The semiconductor device as claimed in claim 8 , wherein each air gap is surrounded by the insulating cap layer, the remaining first insulating layer, the remaining second dielectric layer and the remaining second insulating layer.

14. A semiconductor structure comprising: a base; a first dielectric layer disposed on the substrate; A plurality of conductive lines are disposed on the first dielectric layer; as well as A plurality of air gaps are set at a plurality of first gaps between the plurality of conductive lines along a lateral direction of the plurality of conductive lines. 15 . The semiconductor structure as claimed in claim 14 , further comprising a first insulating layer disposed on the plurality of conductive lines. 16 . The semiconductor structure as claimed in claim 15 , further comprising a second dielectric layer disposed on the first insulating layer. 17 . The semiconductor structure as claimed in claim 16 , further comprising a second insulating layer disposed on the second dielectric layer and filling the second gaps of the second dielectric layer in a lateral direction. 18 . The semiconductor structure of claim 17 , wherein the second insulating layer, the first insulating layer and the second dielectric layer above each first upper surface of the plurality of conductive lines are polished to expose a remaining first insulating layer and a remaining second dielectric layer.

19. The semiconductor structure of claim 18, wherein the remaining second dielectric layer is etched to form a plurality of second gaps. 20 . The semiconductor structure of claim 19 , further comprising an insulating cap layer disposed on each of the first upper surfaces of the plurality of conductive lines to surround the plurality of second gaps to form the plurality of air gaps.

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