A vertical structure Micro LED chip and its preparation method

Abstract

The present invention relates to the technical field of LED packaging. The present invention discloses a vertical structure Micro LED chip and a preparation method thereof. The vertical structure Micro LED chip comprises a first Micro LED chip and a second Micro LED chip. The first Micro LED chip comprises a first substrate, a first epitaxial layer, and a first electrode. A first bonding layer is arranged on the first epitaxial layer, and the first electrode is exposed; the first electrode comprises a first N-type electrode and a first P-type electrode; the second Micro LED chip comprises a second epitaxial layer and a second electrode. A second bonding layer is arranged on the second epitaxial layer, and the second electrode is exposed; the second electrode comprises a second N-type electrode; the first Micro LED chip and the second Micro LED chip are bonded together through the first bonding layer and the second bonding layer, and the first N-type electrode and the second N-type electrode are arranged in alignment. The implementation of the present invention effectively improves the light output power of the Micro LED chip per unit area, and also reduces the image distortion phenomenon caused by the wavelength difference of adjacent chips.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and in particular to a vertical structure Micro LED chip and a preparation method thereof. Background Art

[0002] Micro LED chips have excellent brightness and color saturation in common screen displays. At the same time, Micro LED chips have good stability and high conversion efficiency, which gives them many advantages over OLED and LCD displays in display technology.

[0003] Existing Micro LED chips have good display effects in both indoor and outdoor displays, but the display effect on high-transmittance glass planes is poor. This is because in order to ensure the transparent display effect of the glass, the gap between the light-emitting chips must be large enough to reduce light blocking, which often causes the gap area to be larger than the chip area, and the total area of ​​the gap exceeds 50%-80% of the chip area. At the same resolution, the reduction in chip area leads to a decrease in brightness, and thus the display effect will be reduced under strong outdoor light.

[0004] In addition, the human eye is sensitive to the chip's light wavelength at around 1nm-2nm. If the wavelength difference between adjacent Micro LED chips exceeds this value, the human eye will see serious color distortion. The light wavelength of the Micro LED chip is easily affected by the uniformity of epitaxial growth, and at the current stage, it is extremely difficult to make the difference in the light wavelength within a single epitaxial wafer less than 2nm. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a vertically structured Micro LED chip and a preparation method thereof, so as to increase the light output power of the Micro LED chip per unit area without changing the gap between the light-emitting chips and reduce the image distortion caused by the wavelength difference between adjacent chips.

[0006] In order to solve the above technical problems, the first aspect of the present invention provides a vertical structure Micro LED chip, including: a first Micro LED chip and a second Micro LED chip;

[0007] The first Micro LED chip includes a first substrate and a first epitaxial layer disposed on the first substrate, a first electrode and a first bonding layer are disposed on the first epitaxial layer, and the first electrode is exposed outside the first bonding layer; the first electrode includes a first N-type electrode and a first P-type electrode;

[0008] The second Micro LED chip includes a second epitaxial layer, a second electrode and a second bonding layer are disposed on the second epitaxial layer, and the second electrode is exposed outside the second bonding layer; the second electrode includes a second N-type electrode;

[0009] The first Micro LED chip and the second Micro LED chip are bonded together through the first bonding layer and the second bonding layer, and the first N-type electrode and the second N-type electrode are arranged in alignment;

[0010] The vertical structure Micro LED chip also includes an insulating protection layer arranged on the second epitaxial layer and a solder pad arranged on the insulating protection layer, and the solder pad penetrates the insulating protection layer and is electrically connected to at least two of the first electrode, the second electrode, and the second epitaxial layer.

[0011] As an improvement of the above solution, the average value of the emission wavelength of the first Micro LED chip and the emission wavelength of the second Micro LED chip is the preset emission wavelength of the vertical structure Micro LED chip;

[0012] The light emission wavelength of the first Micro LED chip differs from the light emission wavelength of the second Micro LED chip by 5nm to 10nm.

[0013] As an improvement of the above solution, the second epitaxial layer includes a second N-type semiconductor layer, a second multi-quantum well layer and a second P-type semiconductor layer which are arranged in sequence.

[0014] As an improvement of the above solution, the second electrode is a second N-type electrode, and the second bonding layer is arranged on the surface of the second N-type semiconductor layer;

[0015] The pads include a first pad, a second pad and a third pad. The first pad, the second pad and the third pad penetrate the insulating protection layer and are electrically connected to the second N-type electrode, the first P-type electrode and the second P-type semiconductor layer respectively.

[0016] As an improvement of the above solution, the second electrode further includes a second P-type electrode, and the second bonding layer is arranged on the surface of the second P-type semiconductor layer;

[0017] The pads include a first pad, a second pad and a third pad, and the first pad, the second pad and the third pad penetrate the insulating protection layer and are electrically connected to the first P-type electrode, the second P-type electrode and the second N-type electrode respectively;

[0018] The thickness of the second N-type semiconductor layer is 0.5 μm to 1.1 μm, and the total thickness of the second N-type semiconductor layer, the second multi-quantum well layer and the second P-type semiconductor layer is less than 1.5 μm.

[0019] As an improvement of the above solution, the first epitaxial layer includes a first N-type semiconductor layer, a first multi-quantum well layer and a first P-type semiconductor layer arranged in sequence, and the first bonding layer is arranged on the surface of the first P-type semiconductor layer.

[0020] As an improvement of the above solution, the first bonding layer is one or more of a silicon oxide layer, an aluminum oxide layer, and an Au-Sn alloy, and the thickness of the first bonding layer is 0.1 μm to 0.3 μm;

[0021] The second bonding layer is one or more of a silicon oxide layer, an aluminum oxide layer, and an Au-Sn alloy, and the thickness of the second bonding layer is 0.1 μm to 0.3 μm.

[0022] The second aspect of the present invention further provides a method for preparing the vertical structure Micro LED chip, comprising:

[0023] Preparing a first epitaxial layer on a first substrate, and preparing a first electrode on the first epitaxial layer, wherein the first electrode includes a first N-type electrode and a first P-type electrode;

[0024] Preparing a first bonding layer on the first epitaxial layer and exposing the first electrode to obtain a first Micro LED chip;

[0025] Preparing a second epitaxial layer on a second substrate, and preparing a second electrode on the second epitaxial layer, wherein the second electrode comprises a second N-type electrode;

[0026] Preparing a second bonding layer on the second epitaxial layer and exposing the second electrode to obtain a second Micro LED chip;

[0027] Bonding the first bonding layer and the second bonding layer to align and bond the first N-type electrode and the second N-type electrode;

[0028] The substrate on the second Micro LED chip is peeled off, and the exposed surface is etched downward to expose the electrode to form a first through hole and a second through hole;

[0029] preparing an insulating protective layer on the second epitaxial layer;

[0030] The insulating protective layer is etched downward to expose the electrode or the epitaxial layer to form a third through hole, and the insulating protective layer at the first through hole and the second through hole is removed to expose the first through hole and the second through hole;

[0031] A first pad, a second pad, and a third pad are prepared at the first through hole, the second through hole, and the third through hole.

[0032] As an improvement of the above solution, the step of preparing a second epitaxial layer on the second substrate and forming a second electrode on the second epitaxial layer includes:

[0033] The step of preparing a second epitaxial layer on the second substrate and preparing a second electrode on the second epitaxial layer comprises:

[0034] Preparing a second epitaxial layer on a second substrate, wherein the second epitaxial layer includes a second N-type semiconductor layer, a second multi-quantum well layer, and a second P-type semiconductor layer which are sequentially arranged;

[0035] A second electrode is prepared on the second P-type semiconductor layer, wherein the second electrode includes a second N-type electrode and a second P-type electrode.

[0036] As an improvement of the above solution, the step of preparing a second epitaxial layer on the second substrate and preparing a second electrode on the second epitaxial layer includes:

[0037] Preparing a second epitaxial layer on a second substrate, wherein the second epitaxial layer includes a second N-type semiconductor layer, a second multi-quantum well layer, and a second P-type semiconductor layer which are sequentially arranged;

[0038] preparing a temporary bonding layer on the second P-type semiconductor layer;

[0039] Providing a temporary substrate, and bonding the temporary substrate and the temporary bonding layer together;

[0040] peeling off the second substrate to expose the second N-type semiconductor layer;

[0041] A second electrode is prepared on the second N-type semiconductor layer, where the second electrode is a second N-type electrode.

[0042] The implementation of the present invention has the following beneficial effects:

[0043] In the present invention, the vertical structure Micro LED chip includes a first Micro LED chip and a second Micro LED chip; the first Micro LED chip includes a first substrate, a first epitaxial layer, and a first bonding layer; the second Micro LED chip includes a second epitaxial layer and a second bonding layer, the first Micro LED chip and the second Micro LED chip are bonded together through the first bonding layer and the second bonding layer, and the first N-type electrode and the second N-type electrode are arranged in alignment; the superposition of the first Micro LED chip and the second Micro LED chip effectively improves the light output power of the Micro LED chip per unit area, so that it has a good display effect on a high-transmittance glass plane, and can meet the good display requirements in outdoor strong light environments. In addition, by controlling the different currents of the two Micro LED chips, the light power output by the chips at different wavelengths of the two chips is changed, so that the main wavelength output by the two chips can be adjusted, reducing the image distortion caused by the wavelength difference of adjacent chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 : A schematic diagram of the structure of a vertically structured Micro LED chip provided in the first embodiment of the present invention;

[0045] Figure 2 : A schematic diagram of the structure of a vertical Micro LED chip provided in the second embodiment of the present invention;

[0046] Figure 3 : A schematic diagram of the structure after step (1-1) of the first embodiment or the second embodiment of the present invention is completed;

[0047] Figure 4 : A schematic diagram of the structure after the step (1-2) of the first embodiment or the second embodiment of the present invention is completed;

[0048] Figure 5 : A schematic diagram of the structure after step (2) of the first embodiment or the second embodiment of the present invention is completed;

[0049] Figure 6 : A schematic diagram of the structure after the step (3-1) of the first embodiment or the second embodiment of the present invention is completed;

[0050] Figure 7 : A schematic diagram of the structure after step (3-2) of the first embodiment of the present invention is completed;

[0051] Figure 8 : A schematic diagram of the structure after step (4) of the first embodiment of the present invention is completed;

[0052] Fig. 9: A schematic diagram of the structure after step (5) of the first embodiment of the present invention is completed;

[0053] Fig.10 : A schematic diagram of the structure after the substrate is peeled off in step (6) of the first embodiment of the present invention;

[0054] Fig.11 : A schematic diagram of the structure of the second N-type semiconductor layer after the thickness of the second N-type semiconductor layer is reduced in step (6) of the first embodiment of the present invention;

[0055] Fig.12 : A schematic diagram of the structure after the first through hole and the second through hole are formed in step (6) of the first embodiment of the present invention;

[0056] Fig.13 : A schematic diagram of the structure after step (7) of the first embodiment of the present invention is completed;

[0057] Fig.14 : A schematic diagram of the structure after S1 is completed in step (3) of the second embodiment of the present invention;

[0058] Fig.15 : A schematic diagram of the structure after S2 is completed in step (3) of the second embodiment of the present invention;

[0059] Fig.16 : A schematic diagram of the structure after S3 in step (3) of the second embodiment of the present invention is completed;

[0060] Fig.17 : A schematic diagram of the structure after S4 is completed in step (3) of the second embodiment of the present invention;

[0061] Fig.18 : A schematic diagram of the structure after step (4) of the second embodiment of the present invention is completed;

[0062] Fig.19 : A schematic diagram of the structure after step (5) of the second embodiment of the present invention is completed;

[0063] Fig. 20 : A schematic diagram of the structure after peeling off the temporary substrate in step (6) of the second embodiment of the present invention;

[0064] Fig.21 : A schematic diagram of the structure after the first through hole and the second through hole are formed in step (6) of the second embodiment of the present invention;

[0065] Fig. 22 : A schematic diagram of the structure after step (7) of the second embodiment of the present invention is completed.

[0066] Figure numerals: 100-first substrate; 110-first N-type semiconductor layer; 120-first multi-quantum well layer; 130-first P-type semiconductor layer; 141-first N-type electrode; 142-first P-type electrode; 150-first bonding layer; 200-second substrate; 210-second N-type semiconductor layer; 220-second multi-quantum well layer; 230-second P-type semiconductor layer; 231-temporary bonding layer; 232-temporary substrate; 241-second N-type electrode; 242-second P-type electrode; 250-second bonding layer; 310-first through hole; 320-second through hole; 330-third through hole; 400-insulating protection layer; 510-first pad; 520-second pad; 530-third pad. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail with specific embodiments below.

[0068] To solve the above problems, the first aspect of the present invention provides a vertical structure Micro LED chip, including: a first Micro LED chip and a second Micro LED chip. The average value of the light-emitting wavelength of the first Micro LED chip and the light-emitting wavelength of the second Micro LED chip is the preset light-emitting wavelength of the vertical structure Micro LED chip. In the present invention, the superposition of the first Micro LED chip and the second Micro LED chip effectively improves the light output power of the Micro LED chip per unit area, so that it has a good display effect on a high-transmittance glass plane, and can meet the good display requirements in outdoor strong light environments. It should be noted that the average value here refers to the average value calculated by measuring the measured value of the light-emitting wavelength of the first Micro LED chip and the measured value of the light-emitting wavelength of the second Micro LED chip.

[0069] Furthermore, the light-emitting wavelength of the first Micro LED chip and the light-emitting wavelength of the second Micro LED chip differ by 1nm to 20nm, preferably 5nm to 10nm. By controlling different currents of the two Micro LED chips, the light power output by the chips at different wavelengths is changed, thereby achieving adjustable main wavelength output by the two chips, reducing image distortion caused by wavelength differences between adjacent chips, and lowering growth performance requirements for epitaxial wafers.

[0070] Among them, the first Micro LED chip and the second Micro LED chip are bonded together through a bonding layer, and the electrodes of the first Micro LED chip and the electrodes of the second Micro LED chip are arranged in alignment, which can make the current more evenly distributed in the two Micro LED chips, improve the luminous efficiency of the Micro LED chips, and also help to reduce the parallel resistance, thereby reducing the forward conduction voltage.

[0071] Specifically, the first Micro LED chip includes a first substrate 100 and a first epitaxial layer arranged on the first substrate 100. Optionally, the first epitaxial layer includes a first N-type semiconductor layer 110, a first multi-quantum well layer 120 and a first P-type semiconductor layer 130 arranged in sequence. A first electrode and a first bonding layer 150 are arranged on the first epitaxial layer. The first electrode is exposed outside the first bonding layer 150. The first electrode includes a first N-type electrode 141 and a first P-type electrode 142, that is, the first bonding layer 150 is arranged on the surface of the first P-type semiconductor layer 130, and the first N-type electrode 141 and the first P-type electrode 142 are exposed.

[0072] It can be understood that the first N-type semiconductor layer 110 can be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, etc., but not limited thereto; the first multi-quantum well layer 120 can be an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an AlGaN / AlGaN multi-quantum well layer, etc., but not limited thereto; the first P-type semiconductor layer 130 can be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, etc., but not limited thereto. The material composition of the first N-type electrode 141 and the first P-type electrode 142 can be the same or different. The first bonding layer 150 serves to bond the first epitaxial layer and the second epitaxial layer, and is preferably made of silicon oxide, aluminum oxide, Au-Sn alloy, etc.

[0073] The second Micro LED chip includes a second epitaxial layer, the second epitaxial layer includes a second N-type semiconductor layer 210, a second multi-quantum well layer 220 and a second P-type semiconductor layer 230 arranged in sequence, a second electrode and a second bonding layer 250 are arranged on the second epitaxial layer, the second electrode is exposed outside the second bonding layer 250, and the second electrode includes a second N-type electrode 241. Through the bonding action of the second bonding layer 250 and the first bonding layer 150, the first epitaxial layer and the second epitaxial layer can be bonded together to form a vertical structure Micro LED chip in which two Micro LED chips are stacked.

[0074] It can be understood that the second N-type semiconductor layer 210 can be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, etc., but not limited thereto; the second multi-quantum well layer 220 can be an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an AlGaN / AlGaN multi-quantum well layer, etc., but not limited thereto; the second P-type semiconductor layer 230 can be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, etc., but not limited thereto. The composition of the second N-type semiconductor layer 210 can be the same as or different from that of the first N-type semiconductor layer 110, the composition of the second multi-quantum well layer 220 can be the same as or different from that of the first multi-quantum well layer 120, and the composition of the second P-type semiconductor layer 230 can be the same as or different from that of the first P-type semiconductor layer 130. The second bonding layer 250 is preferably made of silicon oxide, aluminum oxide, Au—Sn alloy, etc. The composition of the second bonding layer 250 may be the same as or different from that of the first bonding layer 150 .

[0075] Furthermore, the vertical structure Micro LED chip also includes an insulating protection layer 400 arranged on the second epitaxial layer and a pad arranged on the insulating protection layer 400, and the pad penetrates the insulating protection layer 400 and is electrically connected to at least two of the first electrode, the second electrode, and the second epitaxial layer.

[0076] In some specific and preferred embodiments, the second electrode is a second N-type electrode 241, the second bonding layer 250 is arranged on the surface of the second N-type semiconductor layer 210, and the pads include a first pad 510, a second pad 520 and a third pad 530, and the first pad 510, the second pad 520 and the third pad 530 penetrate the insulating protection layer 400 and are electrically connected to the second N-type electrode 241, the first P-type electrode 142 and the second P-type semiconductor layer 230 respectively. In this embodiment, the first Micro LED chip and the second Micro LED chip are arranged in parallel, and the first N-type electrode 141 and the second N-type electrode 241 are aligned to form an N electrode of the vertical structure Micro LED chip. The first P-type electrode 142 in the first Micro LED chip serves as the P electrode of the vertical structure Micro LED chip. The current is injected from the only first P-type electrode 142 and flows through the PN junctions of the two Micro LED chips in sequence. The recombination rate of electrons and holes in the first Micro LED chip and the second Micro LED chip is regulated by adjusting the injected voltage or current, and then the light emission wavelength is regulated, thereby reducing the image distortion caused by the wavelength difference between adjacent chips.

[0077] In some other specific and preferred embodiments, the second electrode further includes a second P-type electrode 242, that is, the second electrode includes a second N-type electrode 241 and a second P-type electrode 242, the second bonding layer 250 is disposed on the surface of the second P-type semiconductor layer 230, and the pad includes a first pad 510, a second pad 520 and a third pad 530, and the first pad 510, the second pad 520 and the third pad 530 penetrate the insulating protective layer 400 and are electrically connected to the first P-type electrode 142, the second P-type electrode 242 and the second N-type electrode 241 respectively. In this embodiment, the first Micro LED chip and the second Micro LED chip can be regarded as being arranged in parallel, and the P electrode and the N electrode of each chip are independently connected. By applying voltage and controlling current to the first Micro LED chip and the second Micro LED chip respectively, the ratio of their luminous intensity can be accurately set, and the luminous wavelength can be mixed as required, and the luminous wavelength can be precisely regulated to meet the display requirements of high resolution and high precision pixels.

[0078] It can be understood that the first N-type electrode 141 and the second N-type electrode 241 are arranged in alignment, and the first P-type electrode 142 and the second P-type electrode 242 are arranged in alignment or non-aligned. Of course, the first P-type electrode 142 and the second P-type electrode 242 can also be arranged in alignment, and the first N-type electrode 141 and the second N-type electrode 241 can be arranged in alignment or non-aligned, which can be flexibly adjusted according to actual conditions. The material composition of the first pad 510, the second pad 520 and the third pad 530 can be the same or different.

[0079] Regarding the arrangement of the second electrode and the second bonding layer 250 in the second Micro LED chip, there are many implementations, such as Figure 1 In the first embodiment provided, the second electrode is a second N-type electrode 241 and a second P-type electrode 242, and the second bonding layer 250 is disposed on the surface of the second P-type semiconductor layer 230; Figure 2 In the second embodiment provided, the second electrode is a second N-type electrode 241 , and the second bonding layer 250 is disposed on a surface of the second N-type semiconductor layer 210 .

[0080] The present invention will be further described below with specific embodiments:

[0081] First embodiment

[0082] This embodiment provides a vertical structure Micro LED chip, such as Figure 1As shown, it includes a first Micro LED chip and a second Micro LED chip; the average of the emission wavelengths of the first Micro LED chip and the second Micro LED chip is the preset emission wavelength of the vertical structure Micro LED chip; the emission wavelength of the first Micro LED chip and the emission wavelength of the second Micro LED chip differ by 5nm to 10nm.

[0083] Specifically, the first Micro LED chip includes a first substrate 100 and a first epitaxial layer arranged on the first substrate 100, the first epitaxial layer includes a first N-type semiconductor layer 110, a first multi-quantum well layer 120 and a first P-type semiconductor layer 130 arranged in sequence, a first electrode and a first bonding layer 150 are arranged on the first P-type semiconductor layer 130, the first bonding layer 150 is arranged on the surface of the first P-type semiconductor layer 130, the first electrode includes a first N-type electrode 141 and a first P-type electrode 142, and the first N-type electrode 141 and the first P-type electrode 142 are exposed outside the first bonding layer 150.

[0084] The second Micro LED chip includes a second epitaxial layer, which includes a second N-type semiconductor layer 210, a second multi-quantum well layer 220 and a second P-type semiconductor layer 230 arranged in sequence, a second electrode and a second bonding layer 250 are arranged on the second P-type semiconductor layer 230, and the second bonding layer 250 is arranged on the surface of the second P-type semiconductor layer 230. The second electrode includes a second N-type electrode 241 and a second P-type electrode 242, and the second N-type electrode 241 and the second P-type electrode 242 are exposed outside the second bonding layer 250.

[0085] The first Micro LED chip and the second Micro LED chip are bonded together through the first bonding layer 150 and the second bonding layer 250 , and the first N-type electrode 141 and the second N-type electrode 241 are arranged in alignment.

[0086] The vertical structure Micro LED chip further includes an insulating protection layer 400 disposed on the second N-type semiconductor layer 210; a first pad 510, a second pad 520 and a third pad 530 are disposed on the insulating protection layer 400, and the first pad 510, the second pad 520 and the third pad 530 penetrate the insulating protection layer 400 and are electrically connected to the first P-type electrode 142, the second P-type electrode 242 and the second N-type electrode 241 respectively;

[0087] Accordingly, the method for preparing the vertical structure Micro LED chip includes:

[0088] (1) preparing a first epitaxial layer on a first substrate 100, and preparing a first electrode on the first epitaxial layer, wherein the first electrode includes a first N-type electrode 141 and a first P-type electrode 142;

[0089] Specifically include:

[0090] (1-1) A first epitaxial layer is prepared on a first substrate 100, such as Figure 3 As shown;

[0091] Specifically, the first epitaxial layer includes a first N-type semiconductor layer 110, a first multi-quantum well layer 120, and a first P-type semiconductor layer 130 arranged in sequence. Optionally, the first substrate 100 may be a sapphire substrate, a GaAs substrate, a silicon substrate, or a SiC substrate, but is not limited thereto; more preferably, the first substrate 100 is a sapphire substrate, sapphire has a high light transmittance, and the relative yield of the first epitaxial layer after the first epitaxial layer is peeled off is higher.

[0092] (1-2) preparing a first electrode on the first epitaxial layer, wherein the first electrode includes a first N-type electrode 141 and a first P-type electrode 142;

[0093] Specifically, the first P-type semiconductor layer 130 is patterned and etched to expose the first N-type semiconductor layer 110 to form a first N-type step, a first N-type electrode 141 in contact with the first N-type semiconductor layer 110 is prepared on the first N-type step, and a first P-type electrode 142 is prepared on the first P-type semiconductor layer 130. Figure 4 shown.

[0094] Preferably, the first P-type semiconductor layer 130 is patterned and etched by a photolithography process and an etching process, wherein the etching process can be dry etching or wet etching. More preferably, the etching process is dry etching, which can better ensure the inclination angle of the first N-type step. Exemplary dry etching is inductively coupled plasma (ICP) etching and reactive ion etching (RIE) etching.

[0095] The first N-type electrode 141 and the first P-type electrode 142 can be prepared by a physical vapor deposition (PVD) process or an evaporation process. The first N-type electrode 141 and the first P-type electrode 142 can be formed by the same process or by two processes in two steps. The present invention is not limited thereto, and any corresponding structural implementation form is within the protection scope of the present invention.

[0096] (2) Preparing a first bonding layer 150 on the first epitaxial layer and exposing the first electrode to obtain a first MicroLED chip;

[0097] Specifically, a first bonding layer 150 is prepared on the first P-type semiconductor layer 130, and then the surface of the first bonding layer 150 is processed to expose the first N-type electrode 141 and the first P-type electrode 142, so as to obtain a first Micro LED chip. Figure 5 As shown. The length and width of the Micro LED chip are between 10μm and 50μm, and its thickness design needs to be smaller than the width. Generally, the total thickness of the Micro LED chip should be as less as possible than 10μm. Therefore, the thickness of the first bonding layer 150 is controlled to be 0.1μm to 0.3μm, and the bonding effect is good. The first bonding layer 150 has a light-absorbing property and will absorb light. The thicker the first bonding layer 150 is, the more likely it is to cause the brightness of the Micro LED chip to decrease. Optionally, the process for preparing the first bonding layer 150 can be plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), etc., but is not limited to this.

[0098] Further, the surface of the first bonding layer 150 is polished to expose the first N-type electrode 141 and the first P-type electrode 142. At the same time, the polishing process can make the surface of the first bonding layer 150 a smooth plane, which is beneficial to the enhancement of the bonding strength between the first bonding layer 150 and the second bonding layer 250. An exemplary polishing process is a mechanical chemical polishing (CMP) process, but is not limited thereto.

[0099] (3) preparing a second epitaxial layer on the second substrate 200, and preparing a second electrode on the second epitaxial layer, wherein the second electrode includes a second N-type electrode 241 and a second P-type electrode 242;

[0100] Specifically include:

[0101] (3-1) A second epitaxial layer is prepared on the second substrate 200, such as Figure 6 As shown;

[0102] The second epitaxial layer includes a second N-type semiconductor layer 210, a second multi-quantum well layer 220, and a second P-type semiconductor layer 230, which are sequentially arranged on the second substrate 200. Optionally, the second substrate 200 may be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto; more preferably, the second substrate 200 is a sapphire substrate, which has a high light transmittance, and the relative yield of the second epitaxial layer after the second epitaxial layer is peeled off is higher.

[0103] (3-2) preparing a second electrode on the second epitaxial layer, wherein the second electrode includes a second N-type electrode 241 and a second P-type electrode 242;

[0104] Specifically, the second P-type semiconductor layer 230 is patterned and etched to expose the second N-type semiconductor layer 210 to form a second N-type step, a second N-type electrode 241 in contact with the second N-type semiconductor layer 210 is prepared on the second N-type step, and a second P-type electrode 242 is prepared on the second P-type semiconductor layer 230. Figure 7 Optionally, the second P-type semiconductor layer 230 is patterned and etched by photolithography and etching, wherein the etching process may be dry etching or wet etching, and more preferably, the etching process is dry etching, which can better ensure the inclination angle of the second N-type step, and exemplary dry etching is ICP etching and RIE etching.

[0105] The second N-type electrode 241 and the second P-type electrode 242 can be prepared by a PVD process or an evaporation process. The second N-type electrode 241 and the second P-type electrode 242 can be formed by the same process or by two processes in two steps. The present invention is not limited thereto, and any corresponding structural implementation form is within the protection scope of the present invention.

[0106] (4) Preparing a second bonding layer 250 on the second epitaxial layer and exposing the second electrode to obtain a second MicroLED chip;

[0107] Specifically, a second bonding layer 250 is prepared on the second P-type semiconductor layer 230, and then the surface of the second bonding layer 250 is processed to expose the second N-type electrode 241 and the second P-type electrode 242, so as to obtain a second Micro LED chip. Figure 8 As shown, the thickness of the second bonding layer 250 is 0.1 μm to 0.3 μm, and the bonding yield with the first bonding layer 150 is high. In addition, the second bonding layer 250 has a light absorption property and absorbs light. The thicker the second bonding layer 250 is, the easier it is to reduce the brightness of the Micro LED chip. Optionally, the process for preparing the second bonding layer 250 can be PECVD, ALD, PEALD, etc., but is not limited thereto.

[0108] Furthermore, the surface of the second bonding layer 250 is polished to expose the second N-type electrode 241 and the second P-type electrode 242. At the same time, the polishing process makes the surface of the second bonding layer 250 a smooth plane, which is beneficial to the enhancement of the bonding strength between the second bonding layer 250 and the first bonding layer 150. An exemplary polishing process is a CMP process, but it is not limited thereto.

[0109] (5) Bonding the first bonding layer 150 and the second bonding layer 250 so that the first N-type electrode 141 and the second N-type electrode 241 are aligned and bonded, as shown in FIG. Fig. 9 As shown;

[0110] In this step, the bonding temperature during the bonding is 145°C to 450°C, the bonding pressure is between 700N and 15000N, the bonding environment pressure is less than 0.001torr, and the bonding time is 30min to 180min, so that the first epitaxial layer and the second epitaxial layer are tightly combined through the bonding action between the first bonding layer 150 and the second bonding layer 250, and the reliability is high when used in LED devices.

[0111] (6) Peeling off the second substrate 200 to expose the second N-type semiconductor layer 210, as shown in FIG. Fig.10 As shown;

[0112] Then, the exposed second N-type semiconductor layer 210 is thinned. Fig.11 As shown;

[0113] Finally, the second N-type semiconductor layer 210 is etched downward to expose the first P-type electrode 142 to form a first through hole 310, and the second N-type semiconductor layer 210 is etched downward to expose the second P-type electrode 242 to form a second through hole 320. Fig.12 As shown;

[0114] Preferably, the second N-type semiconductor layer 210 can be thinned by etching. The thickness of the second N-type semiconductor layer 210 after thinning is preferably about 1 μm. The second N-type semiconductor layer 210 has relatively more defects on the side close to the second substrate 200, which will cause the resistance to increase. After thinning, the contact resistance at the interface of the second multi-quantum well layer 220 is low. After applying voltage, the distribution and movement of carriers inside the semiconductor can be more accurately controlled, so as to achieve precise control of the emission wavelength of the second MincroLED chip. More preferably, the thickness of the second N-type semiconductor layer 210 is 0.5 μm to 1.1 μm, and the total thickness of the second N-type semiconductor layer 210, the second multi-quantum well layer 220 and the second P-type semiconductor layer 230 is less than 1.5 μm.

[0115] It can be understood that the radius of the first through hole 310 and the second through hole 320 are respectively smaller than the radius of the corresponding first P-type electrode 142 and the second P-type electrode 242, which can not only reduce the contact resistance, more accurately control the distribution of current in the N-type semiconductor layer, improve conductivity, but also reduce the shading area. Optionally, a photolithography process and an etching process are used to etch downward to the exposed surface, wherein the etching process can be dry etching or wet etching, and more preferably, the etching process is dry etching, which can better ensure the inclination angle and etching depth of the N-type step, and exemplary dry etching is ICP etching and RIE etching.

[0116] (7) An insulating protective layer 400 is formed on the second N-type semiconductor layer 210, and the insulating protective layer 400 is etched downward to the second N-type electrode 241 to form a third through hole 330, and the insulating protective layer 400 at the first through hole 310 and the second through hole 320 is removed to expose the first through hole 310 and the second through hole 320, as shown in FIG. Fig.13 As shown;

[0117] In this step, the insulating protective layer 400 is an aluminum oxide layer, and the thickness of the insulating protective layer 400 is The process for preparing the insulating protection layer 400 includes but is not limited to ALD, PVD, CVD, etc.

[0118] Furthermore, a photolithography process and an etching process are used to etch downward to the exposed surface, wherein the etching process can be dry etching or wet etching. More preferably, the etching process is dry etching, which can better ensure the inclination angle and etching depth of the first N-type step and the second N-type step. Exemplary dry etching is ICP etching and RIE etching.

[0119] (8) Prepare the first pad 510, the second pad 520 and the third pad 530 at the first through hole 310, the second through hole 320 and the third through hole 330, and obtain Figure 1 The vertical structure Micro LED chip shown;

[0120] In this step, the process of preparing the first pad 510, the second pad 520 and the third pad 530 by PVD process and evaporation process can also be other preparation processes, and the present invention does not specifically limit this. The first pad 510, the second pad 520 and the third pad 530 can be formed by the same process or by different processes in steps, and the present invention is not limited to this, and any corresponding structural implementation form is within the protection scope of the present invention.

[0121] Second embodiment

[0122] This embodiment provides a vertical structure Micro LED chip, such as Figure 2 As shown, it includes a first Micro LED chip and a second Micro LED chip; the average of the emission wavelengths of the first Micro LED chip and the second Micro LED chip is the preset emission wavelength of the vertical structure Micro LED chip; the emission wavelength of the first Micro LED chip and the emission wavelength of the second Micro LED chip differ by 5nm to 10nm.

[0123] Specifically, the first Micro LED chip includes a first substrate 100 and a first epitaxial layer arranged on the first substrate 100, the first epitaxial layer includes a first N-type semiconductor layer 110, a first multi-quantum well layer 120 and a first P-type semiconductor layer 130 arranged in sequence, a first electrode and a first bonding layer 150 are arranged on the first P-type semiconductor layer 130, the first bonding layer 150 is arranged on the surface of the first P-type semiconductor layer 130, the first electrode includes a first N-type electrode 141 and a first P-type electrode 142, and the first N-type electrode 141 and the first P-type electrode 142 are exposed outside the first bonding layer 150.

[0124] The second Micro LED chip includes a second epitaxial layer, which includes a second N-type semiconductor layer 210, a second multi-quantum well layer 220, and a second P-type semiconductor layer 230 arranged in sequence, a second electrode and a second bonding layer 250 are arranged on the second N-type semiconductor layer 210, and the second bonding layer 250 is arranged on the second N-type semiconductor layer 210. The second electrode is a second N-type electrode 241, and the second N-type electrode 241 is exposed outside the second bonding layer 250.

[0125] The first Micro LED chip and the second Micro LED chip are bonded together through the first bonding layer 150 and the second bonding layer 250 , and the first N-type electrode 141 and the second N-type electrode 241 are arranged in alignment.

[0126] The vertical structure Micro LED chip also includes an insulating protection layer 400 arranged on the second P-type semiconductor layer 230; a first solder pad 510, a second solder pad 520 and a third solder pad 530 are arranged on the insulating protection layer 400, and the first solder pad 510, the second solder pad 520 and the third solder pad 530 penetrate the insulating protection layer 400 and are electrically connected to the second N-type electrode 241, the first P-type electrode 142 and the second P-type semiconductor layer 230 respectively.

[0127] Accordingly, the method for preparing the vertical structure Micro LED chip includes:

[0128] (1) preparing a first epitaxial layer on a first substrate 100, and preparing a first electrode on the first epitaxial layer, wherein the first electrode includes a first N-type electrode 141 and a first P-type electrode 142;

[0129] Specifically include:

[0130] (1-1) A first epitaxial layer is prepared on a first substrate 100, such as Figure 3 As shown;

[0131] Specifically, the first epitaxial layer includes a first N-type semiconductor layer 110, a first multi-quantum well layer 120, and a first P-type semiconductor layer 130 arranged in sequence. Optionally, the first substrate 100 may be a sapphire substrate, a GaAs substrate, a silicon substrate, or a SiC substrate, but is not limited thereto; more preferably, the first substrate 100 is a sapphire substrate, sapphire has a high light transmittance, and the relative yield of the first epitaxial layer after the first epitaxial layer is peeled off is higher.

[0132] (1-2) preparing a first electrode on the first epitaxial layer, wherein the first electrode includes a first N-type electrode 141 and a first P-type electrode 142;

[0133] Specifically, the first P-type semiconductor layer 130 is patterned and etched to expose the first N-type semiconductor layer 110 to form a first N-type step, a first N-type electrode 141 in contact with the first N-type semiconductor layer 110 is prepared on the first N-type step, and a first P-type electrode 142 is prepared on the first P-type semiconductor layer 130. Figure 4 shown.

[0134] Preferably, the first P-type semiconductor layer 130 is patterned and etched by photolithography and etching processes, wherein the etching process can be dry etching or wet etching. More preferably, the etching process is dry etching, which can better ensure the inclination angle of the first N-type step. Exemplary dry etching is ICP etching and RIE etching.

[0135] The first N-type electrode 141 and the first P-type electrode 142 can be prepared by PVD process or evaporation process. The first N-type electrode 141 and the first P-type electrode 142 can be formed by the same process or by two processes in two steps. The present invention is not limited to this, and any corresponding structural implementation form is within the protection scope of the present invention.

[0136] (2) Preparing a first bonding layer 150 on the first epitaxial layer and exposing the first electrode to obtain a first MicroLED chip;

[0137] Specifically, a first bonding layer 150 is prepared on the first P-type semiconductor layer 130, and then the surface of the first bonding layer 150 is processed to expose the first N-type electrode 141 and the first P-type electrode 142, so as to obtain a first Micro LED chip. Figure 5 As shown. The thickness of the first bonding layer 150 is 0.1 μm to 0.3 μm. Optionally, the process for preparing the first bonding layer 150 may be PECVD, ALD, PEALD, etc., but is not limited thereto.

[0138] Furthermore, the surface of the first bonding layer 150 is polished to expose the first N-type electrode 141 and the first P-type electrode 142. At the same time, the polishing process can make the surface of the first bonding layer 150 a smooth plane, which is conducive to enhancing the bonding strength between the first bonding layer 150 and the second bonding layer 250. An exemplary polishing process is a CMP process, but it is not limited thereto.

[0139] (3) preparing a second epitaxial layer on the second substrate 200, and preparing a second electrode on the second epitaxial layer, wherein the second electrode is a second N-type electrode 241;

[0140] Specifically include:

[0141] (3-1) A second epitaxial layer is prepared on the second substrate 200, such as Figure 6 As shown;

[0142] The second epitaxial layer includes a second N-type semiconductor layer 210, a second multi-quantum well layer 220, and a second P-type semiconductor layer 230, which are sequentially arranged on the second substrate 200. Optionally, the second substrate 200 may be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto; more preferably, the second substrate 200 is a sapphire substrate, which has a high light transmittance, and the relative yield of the second epitaxial layer after the second epitaxial layer is peeled off is higher.

[0143] (3-2) preparing a second electrode on the second epitaxial layer, wherein the second electrode is a second N-type electrode 241;

[0144] In this embodiment, a temporary substrate 232 may be formed on the second P-type semiconductor layer 230 to replace the second substrate 200, and then the second substrate 200 may be peeled off to expose the second N-type semiconductor layer 210, and finally a second electrode may be prepared on the second N-type semiconductor layer 210. Specifically, the process includes:

[0145] S1, preparing a temporary bonding layer 231 on the second P-type semiconductor layer 230, such as Fig.14 As shown;

[0146] The temporary bonding layer 231 can be directly bonded to the second P-type semiconductor layer 230, so the material of the temporary bonding layer 231 is selected from a polymer with a certain bonding strength, but it also needs to be easy to peel off and remove, and the residue on the second P-type semiconductor layer 230 is easy to clean to avoid affecting the performance of the vertical structure Micro LED chip formed after bonding. Preferably, the temporary bonding layer 231 includes benzocyclobutene resin (BCB), epoxy resin, polyimide (PI) and the like.

[0147] S2, providing a temporary substrate 232, bonding the temporary substrate 232 and the temporary bonding layer 231 together, such as Fig.15 As shown;

[0148] The temporary substrate 232 shown has a certain supporting effect on the epitaxial layer. More preferably, the temporary substrate 232 is a double-sided polished and light-transmitting material. Optionally, the temporary substrate 232 shown is highly light-transmitting quartz, glass, sapphire, etc., but not limited to this. The thickness of the temporary substrate 232 is 0.35mm~1mm.

[0149] Furthermore, the bonding temperature during the bonding is 70° C. to 250° C., the bonding pressure is 30N to 1500N, the bonding environment pressure is less than 0.001 torr, and the bonding time is 60 min to 130 min.

[0150] S3, peeling off the second substrate 200 to expose the second N-type semiconductor layer 210, such as Fig.16 As shown;

[0151] S4, preparing a second N-type electrode 241 on the second N-type semiconductor layer 210, such as Fig.17 As shown;

[0152] In this step, the second N-type electrode 241 can be prepared on the second N-type semiconductor layer 210 by using a PVD process or an evaporation process.

[0153] (4) forming a second bonding layer 250 on the second epitaxial layer and exposing the second electrode to obtain a second MicroLED chip;

[0154] Specifically, a second bonding layer 250 is prepared on the second N-type semiconductor layer 210, and then the second bonding layer 250 is processed to expose the second N-type electrode 241 on the surface thereof, thereby obtaining a second Micro LED chip. Fig.18 As shown, the thickness of the second bonding layer 250 is 0.1 μm to 0.3 μm. Optionally, the process for preparing the second bonding layer 250 may be PECVD, ALD, PEALD, etc., but is not limited thereto.

[0155] Furthermore, the surface of the second bonding layer 250 is polished to expose the second N-type electrode 241. At the same time, the polishing process makes the surface of the second bonding layer 250 a smooth plane, which is beneficial to enhance the bonding strength between the second bonding layer 250 and the first bonding layer 150. An exemplary polishing process is a CMP process, but is not limited thereto.

[0156] (5) Bonding the first bonding layer 150 and the second bonding layer 250 so that the first N-type electrode 141 and the second N-type electrode 241 are aligned and bonded, as shown in FIG. Fig.19 As shown;

[0157] In this step, the bonding temperature during the bonding is 145°C to 450°C, the bonding pressure is between 700N and 15000N, the bonding environment pressure is less than 0.001torr, and the bonding time is 30min to 180min, so that the first epitaxial layer and the second epitaxial layer are tightly combined through the bonding action between the first bonding layer 150 and the second bonding layer 250, and the reliability is high when used in LED devices.

[0158] (6) peeling off the temporary substrate 232 and the temporary bonding layer 231 to expose the second P-type semiconductor layer 230, as shown in FIG. Fig. 20 As shown; after the temporary substrate 232 and the temporary bonding layer 231 are peeled off, it is also necessary to remove the residue of the temporary bonding layer 231 on the second P-type semiconductor layer 230.

[0159] Subsequently, the second P-type semiconductor layer 230 is etched downward until the second N-type electrode 241 is exposed to form a first through hole 310, and the second P-type semiconductor layer 230 is etched downward until the first P-type electrode 142 is exposed to form a second through hole 320. Fig.21 As shown;

[0160] Preferably, the thickness of the second P-type semiconductor layer 230 is 0.7 μm to 1.5 μm, and the total thickness of the second N-type semiconductor layer 210, the second multi-quantum well layer 220 and the second P-type semiconductor layer 230 is 2 μm to 3 μm, wherein the second N-type semiconductor layer 210 serves as a bonding surface, and its thickness is controlled at 0.5 μm to 1 μm, which is beneficial to improving the bonding yield.

[0161] It can be understood that the radius of the first through hole 310 and the second through hole 320 are respectively smaller than the radius of the corresponding second N-type electrode 241 and the first P-type electrode 142, which can not only reduce the contact resistance, more accurately control the distribution of current in the N-type semiconductor layer, improve conductivity, but also reduce the shading area.

[0162] (7) An insulating protection layer 400 is formed on the second N-type semiconductor layer 210, and the insulating protection layer 400 is etched down to the second P-type semiconductor layer 230 to form a third through hole 330, and the insulating protection layer 400 at the first through hole 310 and the second through hole 320 is removed to expose the first through hole 310 and the second through hole 320, as shown in FIG. Fig. 22 As shown;

[0163] In this step, the insulating protective layer 400 is an aluminum oxide layer, and the thickness of the insulating protective layer 400 is The process for preparing the insulating protection layer 400 includes but is not limited to ALD, PVD, CVD, etc.

[0164] Furthermore, a photolithography process and an etching process are used to etch downward to the exposed surface, wherein the etching process can be dry etching or wet etching. More preferably, the etching process is dry etching, which can better ensure the inclination angle and etching depth of the first N-type step and the second N-type step. Exemplary dry etching is ICP etching and RIE etching.

[0165] (8) Prepare the first pad 510, the second pad 520 and the third pad 530 at the first through hole 310, the second through hole 320 and the third through hole 330, and obtain Figure 2 The vertical structure Micro LED chip shown;

[0166] In this step, the process of preparing the first pad 510, the second pad 520 and the third pad 530 by PVD process and evaporation process can also be other preparation processes, and the present invention does not specifically limit this. The first pad 510, the second pad 520 and the third pad 530 can be formed by the same process or by different processes in steps, and the present invention is not limited to this, and any corresponding structural implementation form is within the protection scope of the present invention.

[0167] The first comparison

[0168] This comparative example provides a vertical structure Micro LED chip, which includes only one Micro LED chip, specifically:

[0169] The Micro LED chip includes a substrate and an epitaxial layer arranged on the substrate, the epitaxial layer includes an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer arranged in sequence on the substrate, an N-type electrode and a P-type electrode are arranged on the P-type semiconductor layer, wherein the N-type electrode contacts the N-type semiconductor layer through a through hole, and the P-type electrode contacts the P-type semiconductor layer, the Micro LED chip also includes an insulating protection layer arranged on the P-type semiconductor layer and a pad arranged on the insulating protection layer, the pad includes a first pad and a second pad, and the first pad and the second pad are electrically connected to the N-type electrode and the P-type electrode after penetrating the insulating protection layer.

[0170] The second comparison

[0171] This comparative example provides a vertical structure Micro LED chip, which includes only one Micro LED chip, specifically:

[0172] The Micro LED chip includes a substrate, a temporary bonding layer and an epitaxial layer arranged on the temporary bonding layer, the epitaxial layer includes a P-type semiconductor layer, a multi-quantum well layer and an N-type semiconductor layer arranged in sequence on the temporary bonding layer, an N-type electrode and a P-type electrode are arranged on the N-type semiconductor layer, wherein the N-type electrode is in contact with the N-type semiconductor layer, and the P-type electrode is in contact with the P-type semiconductor layer through a through hole, the Micro LED chip also includes an insulating protective layer arranged on the N-type semiconductor layer and a pad arranged on the insulating protective layer, the pad includes a first pad and a second pad, and the first pad and the second pad are electrically connected to the N-type electrode and the P-type electrode after penetrating the insulating protective layer.

[0173] Performance Testing

[0174] The fluorescent adhesive film obtained in the embodiment and the comparative example is prepared into an LED chip according to the application method of the present invention, wherein the luminous peak of the LED chip is in the range of 450nm to 460nm, and its optical power density (optical power per unit area) is tested, wherein the input potential is a relative value based on the first comparative example, and the optical power density is calculated based on the first comparative example. The test results are shown in Table 1 below.

[0175] Table 1 Performance test results of embodiments and comparative examples

[0176] Input potential Optical power density First embodiment 100％ 193％ Second embodiment 100％ 189％ The first comparison 100％ 100％ The second comparison 100％ 98％

[0177] From the above results, it can be seen that the superposition of the first Micro LED chip and the second Micro LED chip in the present invention effectively improves the light output power of the Micro LED chip per unit area, thereby increasing the light power per unit area of ​​the obtained vertical structure Micro LED chip, so that it has a good display effect on the high-transmittance glass plane and can meet the good display requirements in outdoor strong light environments.

[0178] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A vertical structure Micro LED chip, characterized in that: include: A first Micro LED chip and a second Micro LED chip; The first Micro LED chip includes a first substrate and a first epitaxial layer disposed on the first substrate, a first electrode and a first bonding layer are disposed on the first epitaxial layer, and the first electrode is exposed outside the first bonding layer; the first electrode includes a first N-type electrode and a first P-type electrode; The second Micro LED chip includes a second epitaxial layer, a second electrode and a second bonding layer are disposed on the second epitaxial layer, and the second electrode is exposed outside the second bonding layer; the second electrode includes a second N-type electrode; The first Micro LED chip and the second Micro LED chip are bonded together through the first bonding layer and the second bonding layer, and the first N-type electrode and the second N-type electrode are arranged in alignment; The vertical structure Micro LED chip also includes an insulating protection layer arranged on the second epitaxial layer and a solder pad arranged on the insulating protection layer, and the solder pad penetrates the insulating protection layer and is electrically connected to at least two of the first electrode, the second electrode, and the second epitaxial layer.

2. The vertical structure Micro LED chip according to claim 1, wherein: The average of the emission wavelength of the first Micro LED chip and the emission wavelength of the second Micro LED chip is the preset emission wavelength of the vertical structure Micro LED chip; The light emission wavelength of the first Micro LED chip differs from the light emission wavelength of the second Micro LED chip by 5nm to 10nm.

3. The vertical structure Micro LED chip according to claim 1, wherein: The second epitaxial layer includes a second N-type semiconductor layer, a second multi-quantum well layer, and a second P-type semiconductor layer which are sequentially arranged.

4. The vertical structure Micro LED chip according to claim 3, wherein: The second electrode is a second N-type electrode, and the second bonding layer is arranged on the surface of the second N-type semiconductor layer; The pads include a first pad, a second pad and a third pad. The first pad, the second pad and the third pad penetrate the insulating protection layer and are electrically connected to the second N-type electrode, the first P-type electrode and the second P-type semiconductor layer respectively.

5. The vertical structure Micro LED chip according to claim 3, wherein: The second electrode further includes a second P-type electrode, and the second bonding layer is arranged on the surface of the second P-type semiconductor layer; The pads include a first pad, a second pad and a third pad, and the first pad, the second pad and the third pad penetrate the insulating protection layer and are electrically connected to the first P-type electrode, the second P-type electrode and the second N-type electrode respectively; The thickness of the second N-type semiconductor layer is 0.5 μm to 1.1 μm, and the total thickness of the second N-type semiconductor layer, the second multi-quantum well layer and the second P-type semiconductor layer is less than 1.5 μm.

6. The vertical structure Micro LED chip according to claim 1, wherein: The first epitaxial layer includes a first N-type semiconductor layer, a first multi-quantum well layer and a first P-type semiconductor layer which are arranged in sequence, and the first bonding layer is arranged on the surface of the first P-type semiconductor layer.

7. The vertical structure Micro LED chip according to claim 1, wherein: The first bonding layer is one or more of a silicon oxide layer, an aluminum oxide layer, and an Au-Sn alloy, and the thickness of the first bonding layer is 0.1 μm to 0.3 μm; The second bonding layer is one or more of a silicon oxide layer, an aluminum oxide layer, and an Au-Sn alloy, and the thickness of the second bonding layer is 0.1 μm to 0.3 μm.

8. A method for preparing a vertical structure Micro LED chip as claimed in claims 1 to 7, characterized in that: include: Preparing a first epitaxial layer on a first substrate, and preparing a first electrode on the first epitaxial layer, wherein the first electrode includes a first N-type electrode and a first P-type electrode; Preparing a first bonding layer on the first epitaxial layer and exposing the first electrode to obtain a first Micro LED chip; Preparing a second epitaxial layer on a second substrate, and preparing a second electrode on the second epitaxial layer, wherein the second electrode comprises a second N-type electrode; Preparing a second bonding layer on the second epitaxial layer and exposing the second electrode to obtain a second Micro LED chip; Bonding the first bonding layer and the second bonding layer to align and bond the first N-type electrode and the second N-type electrode; The substrate on the second Micro LED chip is peeled off, and the exposed surface is etched downward to expose the electrode to form a first through hole and a second through hole; preparing an insulating protective layer on the second epitaxial layer; The insulating protective layer is etched downward to expose the electrode or the epitaxial layer to form a third through hole, and the insulating protective layer at the first through hole and the second through hole is removed to expose the first through hole and the second through hole; A first pad, a second pad, and a third pad are prepared at the first through hole, the second through hole, and the third through hole.

9. The method for preparing a vertical structure Micro LED chip according to claim 8, wherein: The step of preparing a second epitaxial layer on the second substrate and preparing a second electrode on the second epitaxial layer comprises: Preparing a second epitaxial layer on a second substrate, wherein the second epitaxial layer includes a second N-type semiconductor layer, a second multi-quantum well layer, and a second P-type semiconductor layer which are sequentially arranged; A second electrode is prepared on the second P-type semiconductor layer, wherein the second electrode includes a second N-type electrode and a second P-type electrode.

10. The method for preparing a vertical structure Micro LED chip according to claim 8, wherein: The step of preparing a second epitaxial layer on the second substrate and preparing a second electrode on the second epitaxial layer comprises: Preparing a second epitaxial layer on a second substrate, wherein the second epitaxial layer includes a second N-type semiconductor layer, a second multi-quantum well layer, and a second P-type semiconductor layer which are sequentially arranged; preparing a temporary bonding layer on the second P-type semiconductor layer; Providing a temporary substrate, and bonding the temporary substrate and the temporary bonding layer together; peeling off the second substrate to expose the second N-type semiconductor layer; A second electrode is prepared on the second N-type semiconductor layer, where the second electrode is a second N-type electrode.

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