Isolation power supply chip based on multi-core architecture and control method

Abstract

The invention provides an isolated power supply chip based on a multi-core architecture and a control method. The isolated power supply chip comprises a plurality of power core branches arranged in parallel and a feedback branch. Each power core branch is used for inverting an input DC voltage into a high-frequency oscillation power signal, and then the high-frequency oscillation power signal is rectified into a DC output voltage acting on a load after being subjected to power transmission through a transformer. Each path of power core branch circuit works alternately under the action of different PWM (Pulse Width Modulation) control signals; and the feedback branch is used for sampling the DC output voltage and adjusting different PWM control signals in real time according to a sampling result.

Description

Technical Field

[0001] The present disclosure relates to the technical field of isolated power supplies, and in particular to an isolated power supply chip and a control method based on a multi-core architecture. Background Art

[0002] Isolated power supplies usually modulate the output voltage through a PWM signal with a frequency of several hundred kHz to several MHz. However, due to the switching characteristics of the PWM signal, the input current is discontinuous, resulting in severe conducted electromagnetic interference (EMI) in the frequency range of 150kHz to 30MHz, and causing output voltage fluctuations. Although this can be alleviated by adding EMI filters at the input and capacitors at the output, this will significantly increase the cost and PCB board area.

[0003] At the same time, although the isolated power chip with on-chip transformer integration has significantly reduced its size, it is limited by the inductance of the transformer and the oscillation frequency of the power signal on the chip (tens to hundreds of MHz). The parasitic capacitance of the on-chip transformer induces a common-mode current of 30MHz to 1GHz, making the chip a source of radiated EMI. Therefore, the current isolated power chip has the problem of output voltage ripple, conducted EMI and radiated EMI being difficult to meet the requirements. Summary of the invention

[0004] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides an isolated power supply chip and a control method based on a multi-core architecture.

[0005] In order to achieve the above purpose, the technical solution of the present disclosure is as follows:

[0006] According to an embodiment of one aspect of the present disclosure, an isolated power chip based on a multi-core architecture is provided, comprising a plurality of power core branches arranged in parallel, and a feedback branch. Each power core branch is used to invert the input DC voltage into a high-frequency oscillation power signal, and then rectify it into a DC output voltage acting on the load after power transmission through a transformer; each power core branch works alternately under the action of different PWM control signals; the feedback branch is used to sample the DC output voltage, and adjust different PWM control signals in real time according to the sampling results.

[0007] According to an embodiment of the present disclosure, the isolated power supply chip includes N power core branches arranged in parallel, N is greater than 1, and the phases of the PWM control signals corresponding to adjacent power core branches are staggered by 360° / N, so that the power core branches work alternately to achieve mutual cancellation of DC output voltage ripples.

[0008] According to the embodiment of the present disclosure, each power core branch includes a transmitter inverter circuit, a transformer, and a receiver rectifier circuit. The transmitter inverter circuit is used to invert the input DC voltage into a differential high-frequency oscillation power signal; the transformer includes a primary coil and a secondary coil, and is configured to couple and transmit the high-frequency oscillation power signal received by the primary coil to the secondary coil; the receiver rectifier circuit is used to receive the high-frequency oscillation power signal transmitted by the transformer and rectify it into a DC output voltage acting on the load.

[0009] According to an embodiment of the present disclosure, the transmitter inverter circuit adopts a cross-coupled LC oscillator topology, or a switch full-bridge driver topology, or a switch full-bridge LLC driver topology.

[0010] According to the embodiment of the present disclosure, the receiver rectifier circuit adopts a passive diode rectification topology structure or a MOS tube rectification topology structure.

[0011] According to an embodiment of the present disclosure, the feedback branch includes a feedback control circuit and a multi-phase generator circuit. The feedback control circuit is used to sample the DC output voltage and obtain a PWM reference signal based on the sampling result. The multi-phase generator circuit is connected to the feedback control circuit and is configured to perform phase shift adjustment on the PWM reference signal to generate a PWM control signal for controlling each power core branch.

[0012] According to an embodiment of the present disclosure, a multi-phase generator circuit includes a voltage-controlled delay line, a phase detector, a charge pump, and a capacitor; wherein the voltage-controlled delay line includes a plurality of delay units, which are used to sequentially delay an input PWM reference signal to obtain a plurality of PWM control signals with phase deviations; the phase detector is used to detect the phase deviation between the PWM reference signal and the PWM control signal and convert it into a switching signal for controlling the charge pump, so as to control the charge pump to inject current into the capacitor to generate a voltage signal, and the voltage signal is used to feed back to the delay unit to adjust the delay time of each delay unit.

[0013] According to an embodiment of the present disclosure, the isolated power supply chip includes four power core branches arranged in parallel, and the phases of the PWM control signals corresponding to adjacent power core branches are staggered by 90°, so that the power core branches work alternately.

[0014] According to the embodiment of the present disclosure, the transformer of each power core branch constitutes a transformer group based on a grid array multi-layer packaging substrate.

[0015] According to an embodiment of another aspect of the present disclosure, a control method for an isolated power supply chip based on a multi-core architecture is provided, including: making each power core branch arranged in parallel work alternately under the action of different PWM control signals to invert the input DC voltage into a high-frequency oscillation power signal; performing power transmission based on the high-frequency oscillation power signal; rectifying the high-frequency oscillation power signal after power transmission to obtain a DC output voltage; and sampling the DC output voltage, and adjusting different PWM control signals in real time according to the sampling results. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a schematic diagram of an isolated power chip with a classic single-core architecture;

[0018] Figure 2 A schematic diagram of an isolated power chip of a multi-core architecture according to an embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of the working waveform of the isolated power chip of the multi-core architecture according to an embodiment of the present disclosure;

[0020] Figure 4 is a schematic diagram of normalized output voltage ripple according to an embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram comparing the waveform of the input current of the embodiment of the present disclosure and the waveform of the traditional single-core working current;

[0022] Figure 6 It is a schematic diagram comparing the conducted EMI noise on the spectrum of the isolated power chip of the multi-core architecture of the embodiment of the present disclosure and the conducted EMI noise of the traditional isolated power chip.

[0023] Figure 7 It is a schematic diagram comparing the radiated EMI noise on the spectrum of the isolated power chip of the multi-core architecture of the embodiment of the present disclosure and the radiated EMI noise of the traditional isolated power chip.

[0024] Figure 8 A schematic diagram of operating waveforms of an isolated power chip of a multi-core architecture according to another embodiment of the present disclosure;

[0025] Fig. 9 is a schematic diagram of a multi-phase generator according to an embodiment of the present disclosure;

[0026] Fig.10 A schematic diagram of a PWM control signal of a multi-phase generator circuit and PWM control signals of four branches according to an embodiment of the present disclosure;

[0027] Fig.11 is a schematic diagram of a phase detector according to an embodiment of the present disclosure;

[0028] Fig.12 is a schematic diagram of a charge pump according to an embodiment of the present disclosure;

[0029] Fig.13 is a schematic diagram of the three-dimensional structure of a transformer group according to an embodiment of the present disclosure;

[0030] Fig.14 is a schematic diagram of a transformer group from another angle according to an embodiment of the present disclosure;

[0031] Fig.15 A schematic diagram of electromagnetic simulation results of the inductance and coupling coefficient of the transformer according to an embodiment of the present disclosure;

[0032] Fig.16 A schematic diagram of electromagnetic simulation results of the quality factor of the transformer according to an embodiment of the present disclosure;

[0033] Fig.17 This is a flow chart of a control method for an isolated power chip based on a multi-core architecture according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The present invention provides an isolated power supply chip and control method based on a multi-core architecture. Through multi-phase PWM control, the continuity of input and output currents is achieved, and the conducted EMI and output voltage ripple are effectively reduced. At the same time, the transformer size is reduced to reduce parasitic capacitance and common-mode current, and the cores work alternately at different oscillation frequencies to reduce radiated EMI. The multi-core architecture isolated power supply chip and control method disclosed in the present invention not only reduce conducted and radiated EMI, but also effectively reduce output voltage ripple, significantly improving the stability and safety of the system.

[0035] In the fields of new energy, automotive electronics, industrial control, and biomedicine, systems often need to transmit power and data across power domains, but at the same time they face interference issues such as surge current, electrical noise, and common-mode noise. For example, interference in the high-voltage domain may affect noise-sensitive modules in the low-voltage domain, and even threaten the safety of humans and equipment in severe cases. Isolated power supplies can effectively block noise such as interference and surge current by introducing isolation barriers between different voltage domains, protecting sensitive equipment and related circuits, thereby ensuring the safety of humans and equipment and improving system reliability.

[0036] like Figure 1The isolated power chip of the classic single-core architecture shown generally includes four key parts: an inverter 100 at the transmitting end, which is responsible for converting direct current (DC) to alternating current (AC); a transformer 200, which acts as an isolation barrier to isolate and transmit AC power signals; a rectifier 300 at the receiving end, which converts the AC signal back to DC; and a feedback control circuit 400, which is used to feed back the DC voltage signal to the oscillator circuit at the transmitting end, thereby regulating and stabilizing the output DC voltage.

[0037] The above-mentioned isolated power supply chip usually adopts PWM control to achieve high efficiency in a wide load range. The output voltage ripple size can be described by formula (1):

[0038] ;

[0039] C L Indicates load capacitance, ripple size and PWM signal frequency f PWM In order to reduce the ripple, the PWM frequency needs to be increased, but this will increase the switching loss of the inverter, thereby reducing the system efficiency. In addition, the output current usually depends on the load condition. Although increasing the capacitance can reduce the ripple, it may also limit the application scenarios of the isolated power supply. Therefore, there is still no perfect solution to optimize the balance between ripple and efficiency.

[0040] When the high-frequency voltage and current generated by the isolated power supply chip are conducted through the power line and signal line and interfere with other devices, this interference propagated through the conductor is called "conducted electromagnetic interference." In the isolated power supply, in order to modulate the output voltage, the PWM control signal generated by the feedback control circuit 400 is used to control the start and stop of the inverter 100, which causes the input current to be discontinuous, thereby generating conducted EMI. To reduce this interference, an EMI filter is usually added to the input end of the chip, such as the technical solution in [Texas Instruments' PMP22845 design example: "Isolated 5-V Bias Supply for Automotive CISPR25, Class 5 Emissions, Reference Design," Accessed on April. 20, 2021]. However, this also increases costs and limits the application scenarios of isolated power supply chips.

[0041] The main radiation source of the isolated power supply is dipole radiation. This radiation is generated by the current on the isolation barrier 200, which cannot form a loop and is generated through an equivalent dipole antenna. Since there is no actual physical loop between the reference grounds on both sides, the current can only be radiated in the form of electromagnetic waves, so it is difficult to eliminate this radiation source. When the common-mode voltage generated by the oscillator at the transmitting end passes through the isolation barrier, a common-mode current I is generated due to the distributed parasitic capacitance between the primary and secondary coils of the transformer. CM , resulting in dipole radiation from input to output. At this time, the transformer can be regarded as a dipole antenna, and its dipole radiation power can be expressed as:

[0042] ;

[0043] Where L ant 、f CM and I CM are the length of the dipole antenna, the common-mode current frequency and amplitude respectively. CM The calculation formula for the primary and secondary common mode voltage is:

[0044] ;

[0045] ;

[0046] Among them C ISO is the parasitic capacitance between the primary and secondary coils of the transformer, V pri_CM and V sec_CM are the common-mode voltages of the primary and secondary, V P1 is the voltage at one end of the primary coil of the transformer, V P2 is the voltage at the other end of the transformer primary coil, V S1 is the voltage at one end of the transformer secondary coil, V S2 is the voltage at the other end of the transformer secondary coil. According to formula (3), the common-mode current I can be reduced by reducing the change rate of the common-mode voltage between the primary and secondary. CM EMI radiation is evaluated by measuring the electric field strength of the radiation source received by a spectrum analyzer or EMI receiver. The electric field strength quantifies the magnitude of the interference voltage of the radiation source. As mentioned above, the dipole radiation source is determined by the magnitude of the common-mode current. Therefore, the spectrum of the common-mode current is used to characterize the intensity of EMI radiation within a frequency range. The spectrum of the common-mode current can be obtained through circuit analysis and simulation, which is an effective method for designing and optimizing EMI.

[0047] Application-level solution to EMI radiation: Traditional isolated power chips need to be designed and adjusted through the PCB layout at the application level to pass the Class A or Class B limits of CISPR32. For example, adding an external shielding layer will make the system more bulky and cause problems such as heat dissipation difficulties; adding a safe high-voltage capacitor between the two ground planes will effectively reduce the EMI radiation caused by common-mode current, but the cost is very high; using the stitching capacitor formed by the middle layer of at least four layers of PCB boards to form a low-resistance path between the two ground planes, and using the two middle layers of the PCB to form a large-area parallel plate capacitor to suppress dipole radiation EMI radiation [Reference Analog Devices, AN-0971, “Recommendations for Control of Radiated Emissions with isoPower Devices,” Rev. C, Accessed on Nov. 27, 2021]. Application-level PCB design will always add some additional costs to the system and is not conducive to fundamentally passing the EMI standard test.

[0048] Solutions to EMI radiation at the chip level: Currently, there are several methods to optimize EMI through topology or circuit design within the chip, such as frequency hopping modulation and symmetrical inverter structure, which are analyzed and described below.

[0049] 1. A frequency hopping modulation connects 32 cross-coupled LC oscillators in parallel in the transmitter, and controls the number of oscillators connected to the power transmission through a 5-bit random number generator, thereby controlling the capacitance value of the capacitor that resonates with the transformer, changing the oscillation frequency of the power signal, and making the power signal have multiple peaks within a period of time, which is equivalent to the energy of a certain frequency being dispersed to several frequencies, reducing the highest peak value detected by the EMI receiver, and thus effectively alleviating the radiated EMI of the isolated power chip. However, this method has great defects. First, at least the frequency needs to be dispersed into many parts, which means that many LC oscillators are needed, which increases the circuit complexity and occupies a large chip area; secondly, in order to ensure that the frequency dispersion range is wide enough, the capacitance value of the capacitor cannot be too small, otherwise the dispersion effect is not obvious enough, which further increases the chip area. Finally, modulating power by frequency hopping will cause the input current to fluctuate continuously, further worsening the conducted EMI. References [W. Qin etal., "An 800mW Fully Integrated Galvanic Isolated Power Transfer SystemMeeting CISPR 22 Class-B Emission Levels with 6dB Margin," 2019 IEEEInternational Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019].

[0050] 2. A symmetrical inverter structure uses a pair of NMOS and PMOS to form a complementary D-type oscillator. Since the two groups of NMOS and PMOS alternately charge and discharge the primary coil of the transformer 200, a 0~V voltage is formed at both ends of the transformer 200. DD The swing signal forms a stable V DD / 2 common mode voltage V PRI_CM, it can be seen from formulas (2) and (3) that the symmetrical topology can greatly compress the common-mode current and thus reduce EMI radiation. However, the problem with this structure is that the efficiency of using the symmetrical topology is low, and a dead zone control circuit is required to prevent the four power tubes from being turned on at the same time and causing the chip to burn out. References [D. Pan et al.,"A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-CoupledShoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMIStandard," IEEE International Solid- State Circuits Conference - (ISSCC), SanFrancisco, CA, USA, 2022].

[0051] As can be seen from the above, traditional isolated power supply technology has the following problems or shortcomings:

[0052] 1. Ripple control: Ripple can be reduced by increasing PWM frequency and increasing output capacitance, but this method limits the application scenarios of isolated power supplies;

[0053] 2. Conducted EMI control: Usually rely on off-chip EMI filters and other devices to reduce conducted EMI, which significantly increases costs;

[0054] 3. Radiated EMI control: To reduce radiated EMI, external devices such as magnetic beads, shielding layers and splicing capacitors are required, which increases costs and limits the application of chips. At the same time, the use of frequency hopping technology and symmetrical structure on the chip will increase circuit complexity and chip area, affecting performance such as conducted EMI, ripple and efficiency.

[0055] In order to solve the above problems in the prior art, the main purpose of the present invention is to:

[0056] 1. Reduce output voltage ripple: A control method for an isolated power chip based on a multi-core architecture is proposed. By controlling the phase stagger of the PWM control signal of the inverter, each core is turned on alternately to achieve mutual cancellation of the output voltage ripple, thereby effectively reducing the ripple;

[0057] 2. Reduce conducted EMI: Based on the above multi-core multi-phase control method, each core works alternately, making the input current more continuous, significantly reducing conducted EMI;

[0058] 3. Optimize radiated EMI: Design an isolated power chip based on a multi-core architecture, reduce the parasitic capacitance by reducing the size of the transformer, reduce the common-mode current, and reduce radiated EMI; at the same time, stagger the operating frequencies of multiple power cores to reduce the radiation peak and optimize the radiated EMI.

[0059] In summary, relying on off-chip components to reduce EMI (including conducted and radiated EMI) and output ripple will significantly increase costs, while frequency hopping and symmetrical topology design increase circuit complexity and affect other performance of isolated power supplies. Therefore, there is an urgent need for an isolated power chip that can control EMI and ripple at a low cost at the chip level.

[0060] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0061] In an embodiment of the present disclosure, an isolated power supply chip based on a multi-core architecture is provided. Figure 2 and Figure 8 As shown, the isolated power supply chip includes multiple power core branches arranged in parallel, and a feedback branch.

[0062] Each power core branch is used to invert the input DC voltage into a high-frequency oscillating power signal, and then rectify it into a DC output voltage acting on the load after power transmission through a transformer;

[0063] Each power core branch works alternately under the action of different PWM control signals; the feedback branch is used to sample the DC output voltage and adjust different PWM control signals in real time according to the sampling results.

[0064] According to an embodiment of the present disclosure, the isolated power supply chip includes N power core branches arranged in parallel, N is greater than 1, and the phases of the PWM control signals corresponding to adjacent power core branches are staggered by 360° / N, so that the power core branches work alternately to achieve mutual cancellation of DC output voltage ripples.

[0065] According to the embodiment of the present disclosure, each power core branch includes a transmitter inverter circuit, a transformer, and a receiver rectifier circuit. The transmitter inverter circuit is used to invert the input DC voltage into a differential high-frequency oscillation power signal; the transformer includes a primary coil and a secondary coil, and is configured to couple and transmit the high-frequency oscillation power signal received by the primary coil to the secondary coil; the receiver rectifier circuit is used to receive the high-frequency oscillation power signal transmitted by the transformer and rectify it into a DC output voltage acting on the load. Figure 2As shown, the isolated power chip includes N power core circuits from 0 to N-1, and each power core branch mainly includes a transmitter inverter circuit, a transformer, and a receiver rectifier circuit. Correspondingly, the N transmitter inverter circuits (0 to N-1) in each power core branch constitute the transmitter 100, and the N transformers (TF0-TF N-1 ) form a transformer group 200, and N receiver rectifier circuits (0 to N-1) form a receiver 300. Each power core branch forms a power transmission stage, which is called a core in a multi-core power core, and multiple cores are connected in parallel.

[0066] According to the embodiment of the present disclosure, the feedback branch includes a feedback control circuit and a multi-phase generator circuit. The feedback control circuit is used to sample the DC output voltage and obtain a PWM reference signal according to the sampling result. The multi-phase generator circuit is connected to the feedback control circuit and is configured to perform phase shift adjustment on the PWM reference signal to generate a PWM control signal for controlling each power core branch. Figure 2 and Figure 8 As shown, the feedback branch includes a feedback control circuit 400 and a multi-phase generator 500. The feedback control circuit 400 and the multi-phase generator 500 control the core working sequence to modulate the output voltage to supply power to the load.

[0067] The following describes the composition and function of each circuit module:

[0068] The transmitter 100 is used to convert the input DC voltage V DD Inverted into a differential high-frequency oscillation power signal and output to the N primary coils of the transformer group 200;

[0069] Transformer group 200, an isolation device for transmitting AC power, is composed of N transformers TF 0~ T N-1 Composition, each transformer consists of a primary coil and a secondary coil;

[0070] The receiver 300 is used to rectify the high-frequency oscillation power signal received by the secondary coil of the transformer group 200 into a direct current, and provide a stable direct current voltage to the load;

[0071] Feedback control circuit 400, for sampling the output voltage signal and feeding it back to the receiver, providing a control signal for modulating the output voltage;

[0072] The multi-phase generator circuit 500 generates a PWM control signal for accurately controlling each power core branch according to the control signal generated by the feedback control circuit.

[0073] Taking a single power core branch as an example, the transmitter inverter circuit 0 generates a high-frequency oscillation power signal, which is transmitted through node V P1 、V P2Connect the two ends of the primary coil of transformer TF0. The transformer couples the power signal from the primary to the secondary through electromagnetic induction. S1 、V S2 Connect the receiver rectifier 0, the rectifier converts the AC quantity into DC quantity to supply the load, completing the power transmission.

[0074] The transmitter inverter circuit can adopt a cross-coupled LC oscillator topology, a switch full-bridge driver topology, a switch full-bridge LLC driver topology, or a combination thereof; the receiver rectifier circuit can adopt a passive diode rectifier topology, a MOS tube rectifier topology, or a combination thereof; the transformer group 200 requires N transformers to be connected in parallel to connect each inverter and rectifier.

[0075] The feedback control circuit 400 and the multi-phase generator circuit 500 generate control signals for the power core (or power core branch), such as Figure 3 As shown, the input current I IN and ripple V ISO When PWM is high, the power core works normally and transmits power; when PWM is low, the power core stops working. N power cores correspond to N PWM control signals (or called PWM control signals), and the phase of each PWM control signal is staggered by 360° / N (Δφ=360° / N), so that the power cores work alternately.

[0076] Ideally, when the PWM control signal duty cycle is k / N (k=1,2,3…N-1), V ISO The fluctuation is 0, and there is no ripple at this time, which is the best case. Even in the worst case, such as Figure 4 As shown in the figure, since the isolated power supply is divided into N small power cores, the power of each small power core is 1 / N of the total power, making the output voltage Ripple is reduced to 1 / N of the traditional single-core single PWM control signal control structure 2 , f PWM Indicates the PWM control signal frequency, C L represents the load capacitance, as shown in formulas (5) and (1):

[0077] .

[0078] like Figure 4 The normalized output voltage ripple is shown, and the effects of traditional single-core single-phase PWM control and multi-core multi-phase control are intuitively compared. Figure 5 As shown, compared with the traditional single-core architecture, the single-core input current I INThe input current of the multi-core architecture is evenly distributed in the entire cycle, which achieves a more continuous and stable current waveform. This uniform distribution significantly optimizes the conducted EMI performance, such as Figure 6 The spectrum characteristics of the isolated power supply from 150kHz to 30MHz are shown in the figure. Compared with the traditional solution, the isolated power supply using multi-phase PWM control has a higher PWM frequency (1f PWM、 2f PWM、 3f PWM The conducted EMI noise peak of the MOSFET is significantly reduced, effectively suppressing the high-frequency noise peak.

[0079] Furthermore, since the transformer group is divided into N transformers, the size of each transformer is reduced to 1 / N of the original size. The parasitic capacitance of the transformer refers to the capacitance between the primary and secondary. The reduction in size reduces the value of the parasitic capacitance, thereby reducing the common-mode current I CM As can be seen from formula (2), the radiated EMI is reduced. Since the operating frequencies of multiple cores are different, the single noise peak is dispersed into N peaks, reducing the highest peak value. Figure 7 The frequency spectrum characteristics of the isolated power supply from 30MHz to 1GHz are shown in the figure. It can be seen that at the oscillation frequency f OSC There are multiple peaks (f0, f1, ... f n ), which disperses the noise energy into N parts and reduces the highest peak value that the spectrum receiver can detect.

[0080] From the above description, it can be seen that the isolated power chip with a multi-core architecture will effectively reduce the isolated power ripple and improve the conducted and radiated EMI performance.

[0081] In a 10x10mm package, for example, considering the efficiency and output power, it is preferred to set 4 power core branches. Figure 8 As shown, an isolated power chip including a four-way power core branch architecture is also provided, which mainly includes: a transmitter stage 100, a transformer group 200, a receiver 300, a feedback control circuit 400 and a multi-phase generator circuit 500, which includes a total of 4 power core branches, each power core branch includes a set of inverters, rectifiers, and transformers.

[0082] The following describes the composition and function of each circuit:

[0083] The transmitter is used to convert the input DC voltage V DD Inverted into a differential high-frequency oscillation power signal and output to the N primary coils of the transformer group 200;

[0084] The transformer group 200 is an isolation device for transmitting AC power, and is composed of N transformers TF 0~N-1Composition, each transformer consists of a primary coil and a secondary coil;

[0085] The receiver 300 is used to rectify the high-frequency oscillation power signal received by the secondary coil of the transformer group 200 into a direct current, and provide a stable direct current voltage to the load;

[0086] A feedback control circuit 400 is used to sample the output voltage signal and feed it back to the receiver to provide a control signal for modulating the output voltage;

[0087] The multi-phase generator circuit 500 generates a PWM control signal for accurately controlling each power core branch according to the control signal generated by the feedback control circuit.

[0088] The transmitter inverter circuit can adopt a cross-coupled LC oscillator topology, a switch full-bridge driver topology, a switch full-bridge LLC driver topology, etc., but the full-bridge topology requires 4 drive circuits to drive the power tube switch, and superimposing multiple power cores requires more area; the receiver rectifier circuit can adopt MOS tube rectification or diode rectification.

[0089] According to an embodiment of the present disclosure, a multi-phase generator circuit includes a voltage-controlled delay line, a phase detector, a charge pump, and a capacitor; wherein the voltage-controlled delay line includes a plurality of delay units, which are used to sequentially delay an input PWM reference signal to obtain a plurality of PWM control signals with phase deviations; the phase detector is used to detect the phase deviation between the PWM reference signal and the PWM control signal and convert it into a switching signal for controlling the charge pump, so as to control the charge pump to inject current into the capacitor to generate a voltage signal, and the voltage signal is used to feed back to the delay unit to adjust the delay time of each delay unit.

[0090] Furthermore, the multi-phase generator circuit 500 generates control signals of four power core branches (four cores) according to the control signal of the previous feedback control circuit 400, such as Fig. 9As shown in the figure: the multi-phase generator circuit includes: a phase detector, a charge pump and a voltage-controlled delay line. The input signal PWM_TX enters the voltage-controlled delay line, passes through 4 identical delay units (the delay time of each unit is consistent), and enters the phase detector together with the PWM_TX signal without delay. There is a certain phase deviation between the delayed signal and the original signal. The phase detector can convert the detected specific phase deviation into a switching signal to control the charge pump, and then control the charge pump to inject current into the capacitor to generate a voltage signal, and use this voltage signal to adjust the delay time of each delay unit. When there is a phase deviation between PWM_TX and the signal passing through the voltage-controlled delay line, the phase detector and the charge pump work together to increase the delay time of the delay unit until PWM_TX is completely aligned with the delayed signal, that is, after PWM_TX passes through four delay units (D0-D3), the signal phase is shifted by 360°, and each delay unit is delayed by 90° (φ=90°). The four delay units output four PWM control signals (PWM <0> - PWM <3> ), as the control signal for controlling each power core. The waveforms of the four PWM control signals and the control signal PWM_TX input to the multi-phase generator circuit 500 are as follows: Fig.10 As shown, PWM_TX is used as the reference signal, PWM <0> to PWM <3> Delay 90° phase in sequence until PWM <3> Aligned with PWM_TX.

[0091] Furthermore, the present disclosure provides a specific phase detector circuit (reference Fig.11 shown) and the charge pump circuit (reference Fig.12 shown), combined with Fig.11 and Fig.12 As shown, the phase detector includes two D flip-flops (5011 and 5012) and a logic gate 5013: U1 and U2 are two signals that need phase detection. Every time a rising edge arrives, V P &V N Flipping to high level, when V P &V N When both are high, the D flip-flop is set to 0, V P &V N At the same time, they are low level; due to the phase difference between U1 and U2, V P &V N They will not flip at the same time, thus outputting two voltage signals containing phase difference information. Charge pump circuit: Assuming that U1 is in the first sequence, V P Flip, control the switch 5021 of the charge pump to turn on, charge the capacitor, and then U2 rising edge arrives, triggering V NFlip, switch 5022 that controls the charge pump is turned on, and the charge pump stops charging the capacitor; at this time, the voltage on the capacitor controls the delay unit to increase the delay of U1, reduce the phase difference between U1 and U2, and the phase difference of the next round of rising edges is reduced. Until U1 and U2 are aligned, there is no phase difference, the capacitor maintains the voltage, and the system reaches stability.

[0092] According to the embodiment of the present disclosure, the transformer of each power core branch constitutes a transformer group based on a grid array multi-layer packaging substrate. The present disclosure also provides a specific transformer group 200 implementation method, which can be manufactured on a 4-layer packaging substrate, with a total of 4 layers of metal, two of which are transformer coils, and the other two layers are interconnected metal wires. The primary and secondary coils of the two-layer transformer can be any two layers, but considering the condition that the transformer dielectric withstand voltage allows, the two primary and secondary coils select the two adjacent layers with the smallest spacing to achieve the maximum coupling coefficient. The transmission efficiency of the transformer is proportional to the Q value and the coupling coefficient. Under the condition of size constraints, by optimizing the transformer coil length X, width Y, number of turns N, line spacing s, line width w and line thickness t parameters, the spacing h between the primary and secondary coils of the transformer is determined according to the withstand voltage characteristics of the dielectric material used; within the resonant frequency range of the isolated power supply, the best transmission efficiency is achieved.

[0093] In this specific embodiment, a micro transformer group based on a land grid array (LGA) substrate is prepared in an area of ​​9.5 mm×8.2 mm. Fig.13 The figure shows the three-dimensional structure diagram of the transformer. Fig.14 The top view of the transformer is shown. There are 4 coils in total. The 8 ports on the left are the input ports of the 4 transformer primary coils, and the 8 ports on the right are the output ports of the transformer secondary. The port of the primary coil of the first transformer is marked in the figure (V PP0 、V PN0 ) and the secondary coil port (V SP0 、V SN0 ), combined with Figure 8 As shown, the power signal is from V P1 and V P2 Input, coupled from V S1 and V S2 Output to the secondary. The specific parameters of a single transformer coil are set to X=1700μm, Y=2200μm, N=3, w=70, s=50μm, t=30μm and h=60μm. The results are calculated using electromagnetic simulation software. Fig.15 and Fig.16 As shown, the Q value (Q P , Q S ) is 35 in the range of 90~100MHz, the inductance of the primary and secondary coils (LP , L S ) are 96nH respectively, and the coupling coefficient k is 0.72.

[0094] The present disclosure also provides a control method for the isolated power supply chip based on the multi-core architecture as described above. Fig.17 As shown, the control method includes operations S1-S4:

[0095] Operation S1: enabling each power core branch arranged in parallel to work alternately under the action of different PWM control signals to invert the input DC voltage into a high-frequency oscillation power signal;

[0096] Operation S2: performing power transmission based on the high-frequency oscillation power signal;

[0097] Operation S3: rectifying the high frequency oscillation power signal after power transmission to obtain a DC output voltage; and

[0098] Operation S4: sampling the DC output voltage, and adjusting different PWM control signals in real time according to the sampling result.

[0099] In summary, the isolated power supply chip and control method based on multi-core architecture disclosed in the present invention have the following beneficial effects or one of them:

[0100] 1. Phase interleaving control method of multi-core architecture: The phase of the PWM control signal of the inverter is interleaved through the multi-core architecture, and each core is turned on alternately to achieve mutual cancellation of output voltage ripples, thereby significantly reducing the output ripple.

[0101] 2. Multi-core alternating operation achieves continuous input current: The alternating operation mechanism of the multi-core architecture makes the input current more continuous and effectively reduces conducted EMI.

[0102] 3. Transformer miniaturization design based on multi-core architecture: By reducing the size of the transformer to reduce parasitic capacitance and common-mode current, radiated EMI can be reduced.

[0103] 4. Staggered operating frequencies of power cores: In a multi-core architecture, the operating frequencies of multiple power cores are staggered to reduce the radiation peak and optimize radiated EMI.

[0104] 5. Integrated on-chip EMI control solution: No need to rely on external EMI filters, magnetic beads, shielding layers and other off-chip devices, low-cost EMI and ripple control can be achieved through multi-core control and transformer design inside the chip.

[0105] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0106] In summary, the present disclosure provides an isolated power supply chip and control method based on a multi-core architecture. The isolated power supply control method based on a multi-core architecture significantly optimizes the ripple and EMI problems in the traditional isolated power supply through phase interleaving and multi-core alternating working mechanisms. In order to reduce output voltage ripple and conducted EMI, traditional methods often require increasing the PWM frequency or relying on external EMI filters and other off-chip devices, which not only increases costs but also limits the application scope of the chip. The present disclosure achieves lower ripple and better EMI performance without adding external devices through on-chip optimization of multi-core control.

[0107] At the same time, by reducing the size of the transformer and staggering the operation of each power core, the common mode current and radiation peak are effectively reduced, so that the radiated EMI is significantly improved. In summary, the present disclosure not only reduces the overall cost of the isolated power supply, but also achieves higher system stability and wider application adaptability, with significant economic and technical advantages.

[0108] It should be noted that, in this document, unless otherwise specified, “a” element is not limited to a single element, but may include one or more elements.

[0109] In addition, in this document, unless otherwise specified, ordinal numbers such as "first" and "second" are only used to distinguish multiple components with the same name, and do not indicate that there is a hierarchy, level, execution order, or process order between them. A "first" component and a "second" component may appear together in the same component, or appear in different components. The presence of a component with a larger ordinal number does not necessarily indicate the presence of another component with a smaller ordinal number.

[0110] In this document, unless otherwise specified, the so-called feature A "or" or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist at the same time; the so-called "include", "comprise", "have" and "contain" mean including but not limited to these.

[0111] In addition, in this document, the terms "upper", "lower", "left", "right", "front", "back", or "between" are only used to describe the relative positions between multiple elements, and can be extended to include translation, rotation, or mirroring. In addition, in this document, unless otherwise specified, "an element is on another element" or similar descriptions do not necessarily mean that the element contacts the other element.

[0112] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0113] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An isolated power chip based on a multi-core architecture, comprising: Multiple power core branches are arranged in parallel, each power core branch is used to invert the input DC voltage into a high-frequency oscillation power signal, and then rectify it into a DC output voltage acting on the load after power transmission through a transformer; each power core branch works alternately under the action of different PWM control signals; as well as The feedback branch is used to sample the DC output voltage and adjust different PWM control signals in real time according to the sampling result.

2. The isolated power supply chip according to claim 1 comprises N power core branches arranged in parallel, N is greater than 1, and the phases of the PWM control signals corresponding to adjacent power core branches are staggered by 360° / N, so that the power core branches work alternately to achieve mutual cancellation of DC output voltage ripples.

3. According to the isolated power chip of claim 1, each power core branch comprises: A transmitter inverter circuit is used to invert the input DC voltage into a differential high-frequency oscillating power signal; A transformer, comprising a primary coil and a secondary coil, and configured to couple and transmit the high-frequency oscillation power signal received by the primary coil to the secondary coil; as well as The receiver rectifier circuit is used to receive the high-frequency oscillation power signal transmitted by the transformer and rectify it into a DC output voltage acting on the load.

4. The isolated power chip according to claim 3, wherein the transmitter inverter circuit adopts a cross-coupled LC oscillator topology, a switch full-bridge driver topology, or a switch full-bridge LLC driver topology. 5 . The isolated power chip according to claim 4 , wherein the receiver rectifier circuit adopts a passive diode rectifier topology structure or a MOS tube rectifier topology structure.

6. The isolated power chip according to claim 1, wherein the feedback branch comprises: A feedback control circuit is used to sample the DC output voltage and obtain a PWM reference signal according to the sampling result; The multi-phase generator circuit is connected to the feedback control circuit and is configured to perform phase shift adjustment on the PWM reference signal to generate a PWM control signal for controlling each power core branch.

7. The isolated power chip according to claim 6, wherein the multi-phase generator circuit comprises a voltage-controlled delay line, a phase detector, a charge pump, and a capacitor; wherein: The voltage-controlled delay line includes a plurality of delay units, which are used to sequentially delay the input PWM reference signal to obtain a plurality of PWM control signals with phase deviations; The phase detector is used to detect the phase deviation between the PWM reference signal and the PWM control signal and convert it into a switching signal for controlling the charge pump, so as to control the charge pump to inject current into the capacitor to generate a voltage signal, and the voltage signal is used to feed back to the delay unit to adjust the delay time of each delay unit.

8. The isolated power chip according to claim 1 comprises four power core branches arranged in parallel, and the phases of the PWM control signals corresponding to adjacent power core branches are staggered by 90°, so that the power core branches work alternately. 9 . The isolated power chip according to claim 1 , wherein the transformer of each power core branch constitutes a transformer group based on a grid array multi-layer packaging substrate.

10. A control method for an isolated power chip based on a multi-core architecture according to any one of claims 1 to 9, comprising: Each power core branch connected in parallel works alternately under the action of different PWM control signals, and inverts the input DC voltage into a high-frequency oscillation power signal; Performing power transmission based on the high frequency oscillation power signal; Rectifying the high frequency oscillation power signal after power transmission to obtain a DC output voltage; and The DC output voltage is sampled, and different PWM control signals are adjusted in real time according to the sampling result.

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