A sampling current correction method, system and device

Abstract

The present application discloses a sampling current correction method, system and device, which are applied in the field of power electronics technology, including: determining the current working mode of the DC converter; including the boost mode and the buck mode; determining the deviation state and deviation duration of the sampling current of the specified phase of the DC converter; including sampling advance and sampling lag; based on the working mode and the deviation duration, determining the first compensation amount used to reflect the deviation between the sampling current and the theoretical current in the current rising stage, and / or the second compensation amount used to reflect the deviation between the sampling current and the theoretical current in the current falling stage; based on the deviation state, the sampling current of the corresponding stage is compensated by the first compensation amount and / or the second compensation amount. Applying the scheme of the present application, the sampling current is compensated by the compensation amount, which effectively eliminates the sampling error, and does not need to adjust the sampling time, which is conducive to ensuring the accuracy and reliability of the current sharing control.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a sampling current correction method, system and device. Background Art

[0002] A DC converter, also known as a DC-DC converter, can convert a certain voltage level of DC power into another voltage level of DC power. Figure 1 , which is a schematic diagram of the structure of a multi-phase interleaved parallel DC converter. Currently, high-power DC converters usually use Figure 1 This topology, combined with phase shift control, can reduce the output current ripple. Figure 2 , which is a schematic diagram of the waveform of each phase current after phase shift control. This method can reduce the current stress of the switching device and extend the service life of the power electronic device.

[0003] Multi-phase interleaved parallel DC converters have high requirements for current sharing control between phases. If there is uneven current sharing between phases, the current ripple will increase, reducing the service life of the switching device. In severe cases, it will cause phase circulation and damage the machine. When performing current sharing control, it is necessary to sample the current of each phase, that is, to sample the inductor current at the inductor position of each phase. If the sampling value is inaccurate, it is not conducive to ensuring the reliability of current sharing control.

[0004] The reasons for inaccurate sampling values ​​can be divided into two categories: drive delay and sampling circuit delay. IGBT turn-on time, dead time, narrow pulse suppression time, etc. will all cause drive delay. One current approach is to assume that drive delay has a greater impact than sampling circuit delay, and adjust the sampling time according to the drive delay to reduce the sampling error. However, for many machines with different powers, the impact of drive delay and sampling circuit delay varies. It is necessary to adjust the sampling time accordingly according to the actual situation to effectively ensure the accuracy of the sampled value. In addition, the adjustment of the sampling time poses certain risks to the system. In the case of misjudgment of conditions, it is easy to sample abnormal position currents, affecting the reliability of the control algorithm.

[0005] In summary, how to effectively improve the accuracy of the sampling current of the DC converter is a technical problem that those skilled in the art urgently need to solve. Summary of the invention

[0006] The object of the present invention is to provide a sampling current correction method, system and device to effectively improve the accuracy of the sampling current of a DC converter.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] In a first aspect, the present invention provides a sampling current correction method, comprising:

[0009] Determine the current working mode of the DC converter; wherein the working mode includes a boost mode and a buck mode;

[0010] Determine the deviation state and deviation duration of the sampling current; wherein the deviation state includes sampling advance and sampling lag;

[0011] Based on the working mode and the deviation duration, determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase;

[0012] Based on the deviation state, the sampling current of the corresponding stage is compensated by the first compensation amount and / or the second compensation amount.

[0013] In one implementation, determining the deviation state of the sampled current of the specified phase of the DC converter includes:

[0014] Determining a current variation curve at a sampling position of a specified phase of the DC converter;

[0015] Based on the current variation curve, determining a theoretical current in a current rising phase and a theoretical current in a current falling phase;

[0016] When it is determined that the sampled current in the current rising stage is lower than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is higher than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling ahead;

[0017] When it is determined that the sampled current in the current rising stage is higher than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is lower than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling hysteresis.

[0018] In one implementation, determining the deviation duration of the sampled current includes:

[0019] Determining a current variation curve at a sampling position of a specified phase of the DC converter;

[0020] Based on the current variation curve, determining a theoretical current in a current rising phase and a theoretical current in a current falling phase;

[0021] Determine the difference between the time corresponding to the theoretical current in the current rising stage on the current change curve and the time corresponding to the sampled current in the current rising stage on the current change curve within a single carrier cycle, and use it as the deviation duration of the sampled current;

[0022] Alternatively, the difference between the time corresponding to the theoretical current in the current decreasing phase on the current variation curve and the time corresponding to the sampled current in the current decreasing phase on the current variation curve within a single carrier cycle is determined and used as the deviation duration of the sampled current.

[0023] In one embodiment, based on the working mode and the deviation duration, determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase, includes:

[0024] Based on the working mode, determining the forward duty cycle D and the inductor current ripple ΔI in the working mode;

[0025] Based on the forward duty cycle D, the inductor current ripple ΔI, the carrier period T and the deviation duration Δt, determine a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase;

[0026] The forward duty cycle D represents the duty cycle corresponding to the increase of the absolute value of the current in the working mode.

[0027] In one embodiment, based on the forward duty cycle D, the inductor current ripple ΔI, the carrier period T and the deviation time Δt, determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase, includes:

[0028] Based on the forward duty cycle D and the carrier cycle T, the duration of the current rising phase in a single carrier cycle is determined as the rising duration t1;

[0029] Determine the proportion of the deviation duration in the rising duration t1, and determine a first compensation amount according to the proportion of the deviation duration in the rising duration t1 and the inductor current ripple ΔI;

[0030] Based on the forward duty cycle D and the carrier cycle T, the duration of the current falling phase in a single carrier cycle is determined as the falling duration t2;

[0031] The proportion of the deviation duration in the rising duration t2 is determined, and the second compensation amount is determined according to the proportion of the deviation duration in the rising duration t2 and the inductor current ripple ΔI.

[0032] In one implementation, based on the working mode, determining the forward duty cycle D and the inductor current ripple ΔI in the working mode includes:

[0033] When the working mode is the step-down mode, according to the low-voltage side voltage U L With high voltage side voltage U H , determine the forward duty cycle D in buck mode;

[0034] Determine the low voltage side voltage U L , the carrier period T, and the product of 1-D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the buck mode is obtained;

[0035] When the working mode is the boost mode, according to the low voltage side voltage U L With high voltage side voltage U H , determine the forward duty cycle D in buck mode;

[0036] Determine the low voltage side voltage U L , the product of the carrier period T, and the forward duty cycle D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the boost mode is obtained.

[0037] In one embodiment, the DC converter is a multi-phase interleaved parallel DC converter, and the sampling current correction method further includes:

[0038] Based on the compensated current values, current sharing control of the multi-phase interleaved parallel DC converter is performed;

[0039] Wherein, for each phase of the multi-phase interleaved parallel DC converter, the update of the phase sampling current adopts a double sampling and double updating method, or a double sampling and single updating method, or a single sampling and single updating method;

[0040] The double sampling and double updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage and the current value of the phase compensated in the current falling stage are obtained by the sampling current correction method as two sampling points obtained in the carrier cycle;

[0041] The single sampling and single updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage, or the current value of the phase compensated in the current falling stage is obtained by the sampling current correction method as one sampling point obtained in the carrier cycle;

[0042] The double sampling and single updating method means that in each carrier cycle, the average value of the current value of the phase compensated in the current rising stage and the average value of the current value of the phase compensated in the current falling stage obtained by the sampling current correction method are used as one sampling point obtained in the carrier cycle.

[0043] In one implementation, based on the deviation state, compensating the sampling current of the corresponding stage by using the first compensation amount and / or the second compensation amount includes:

[0044] When the deviation state is sampling advance, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the current value after compensation in the current rising stage, and the sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the current value after compensation in the current falling stage;

[0045] When the deviation state is sampling lag, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the compensated current value in the current rising stage; the sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the compensated current value in the current falling stage.

[0046] In a second aspect, the present invention provides a sampling current correction system, comprising:

[0047] A working mode determination module, used to determine the current working mode of the DC converter; wherein the working mode includes a boost mode and a buck mode;

[0048] The deviation condition determination module is used to determine the deviation state and deviation duration of the sampled current; wherein the deviation state includes sampling advance and sampling lag;

[0049] A compensation amount determination module, for determining, based on the working mode and the deviation duration, a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase;

[0050] A compensation execution module is used to compensate the sampling current of the corresponding stage through the first compensation amount and / or the second compensation amount based on the deviation state.

[0051] In a third aspect, the present invention provides a sampling current correction device, comprising:

[0052] Memory for storing computer programs;

[0053] A processor is used to execute the computer program to implement the steps of the sampling current correction method as described above.

[0054] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the sampling current correction method as described above are implemented.

[0055] By applying the technical solution provided in the embodiment of the present invention, considering that adjusting the sampling moment is prone to errors and thus affecting the reliability of the control algorithm, the sampling moment is not adjusted. Instead, the sampling current is compensated by the compensation amount, so that the value after compensation is a more accurate sampling value, thereby ensuring the reliability of the current sharing control.

[0056] Specifically, different working modes and different deviation durations of the sampling current will affect the calculation of the compensation amount, and the sampling moment may be the current rising stage or the current falling stage. Therefore, in the present application scheme, based on the working mode and the deviation duration, a first compensation amount for reflecting the deviation between the sampling current in the current rising stage and the theoretical current and / or a second compensation amount for reflecting the deviation between the sampling current in the current falling stage and the theoretical current will be determined to ensure the flexibility of the scheme. After obtaining the first compensation amount and / or the second compensation amount, it is necessary to combine the deviation state of the sampling current, that is, whether the sampling is advanced or delayed, to realize compensation for the sampling current in the corresponding stage, so that the current value after compensation is a more accurate value, effectively eliminating the sampling error, which is also conducive to ensuring the reliability of the current sharing control.

[0057] In summary, the present application scheme compensates the sampled current through the compensation amount, effectively eliminates the sampling error, and does not need to adjust the sampling time, which is conducive to ensuring the accuracy and reliability of current sharing control. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 It is a structural schematic diagram of a multi-phase interleaved parallel DC converter;

[0060] Figure 2 Schematic diagram of the waveform of each phase current after phase shift control;

[0061] Figure 3 A flowchart of a sampling current correction method provided in a specific embodiment of the present invention;

[0062] Figure 4 It is a schematic diagram of the principle of sampling ahead of time;

[0063] Figure 5 It is the principle diagram of sampling hysteresis;

[0064] Figure 6 A schematic diagram of the structure of a sampling current correction system provided by a specific embodiment of the present invention;

[0065] Figure 7 A schematic diagram of the structure of a sampling current correction device provided in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0066] The core of the present invention is to provide a sampling current correction method, system and device, which can compensate the sampling current by the compensation amount, effectively eliminate the sampling error, and do not need to adjust the sampling time, which is conducive to ensuring the accuracy and reliability of current sharing control. It is applicable to both unidirectional DC-DC converters and bidirectional DC-DC converters.

[0067] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0068] Please refer to Figure 3 , Figure 3 The present invention provides a flow chart of a sampling current correction method according to a specific embodiment of the present invention. The sampling current correction method may include the following steps:

[0069] Step S301: determining the current working mode of the DC converter; wherein the working mode includes a boost mode and a buck mode.

[0070] The DC converter of the present application can usually be a multi-phase staggered parallel DC converter, which has high requirements for current sharing, so the current sampling value is required to be relatively accurate. The multi-phase staggered parallel DC converter has two working modes: boost mode (BOOST boost) and buck mode (BUCK buck). Of course, in other specific implementations, the DC converter used can be other types of DC converters.

[0071] by Figure 1 Taking the DC converter as an example, the boost mode and the buck mode are explained. Figure 1 The left side is the low voltage side, and the voltage on the low voltage side is denoted as U L, the right side is the high voltage side, the voltage on the high voltage side is denoted as U H For a multi-phase interleaved parallel DC converter, the specific number of parallel phases can be set according to actual needs, for example Figure 1 The figure shows three phases, each phase consists of an inductor and a bridge arm, and the two switch tubes in the bridge arm can usually be IGBTs. Figure 1 S1 to S5 shown are IGBTs including anti-parallel diodes.

[0072] In boost mode, current flows from the low voltage side to the high voltage side, that is, Figure 1 The current flows from the left side to the right side of the voltage source. Usually, the current flowing from the high voltage side to the low voltage side can be regarded as the positive direction of the current. Therefore, the current direction is negative when working in the boost mode. Figure 1 The DC converter shown is a multi-phase staggered parallel boost DC converter, each phase of which includes two IGBTs, which can work in a complementary wave-generating working state or an independent wave-generating working state. . Taking one of the phases as an example, for example, during the conduction of S5, the current flowing through the inductor L2 increases linearly at a certain rate, and some energy is stored in the inductor L2. During the off period of S5, the current flows to the right through the switch S2, and the current on the inductor L2 gradually decreases. Here, the inductor L2 phase is taken as an example, and the control logic of the other phases is the same, and phase shift control is performed at the same time. If it is three-phase, the phase difference is 120°.

[0073] In buck mode, current flows from the high voltage side to the low voltage side, that is, Figure 1 The current flows from the right side to the left side. Usually, the current flows from the high voltage side to the low voltage side as the positive direction of the current. Therefore, the current direction is positive when working in the buck mode. Figure 1 The DC converter shown is a multi-phase staggered parallel step-down DC converter, each phase of which includes two IGBTs, which can work in a complementary wave-generating working state or an independent wave-generating working state. Still taking the inductor L2 phase as an example, for example, during the conduction period of S2, the current flowing through the inductor L2 increases linearly at a certain rate, and some energy is stored in the inductor L2. During the off period of S2, the inductor L2 forms a freewheeling loop through the switch S5, and the current on the inductor L2 gradually decreases. Here, the inductor L2 phase is taken as an example, and the control logic of the other phases is the same.

[0074] In addition, the DC converter of the present application may be a DC converter having both a boost mode and a buck mode, or a DC converter having only a single working mode, that is, the present application is applicable to both unidirectional DC-DC converters and bidirectional DC-DC converters. If the DC converter has only a single working mode, it can be understood that when executing step S301, the working mode of the DC converter determined is fixed and will not change due to different scenarios. In the following text of the present application, Figure 1 Such a multi-phase interleaved parallel DC converter is used as an example for explanation, that is, it can support both the boost mode and the buck mode.

[0075] In addition, there are many specific ways to determine the current working mode of the DC converter. For example, when the current is sampled by the Hall sensor, the current working mode of the DC converter can be determined based on the current flow direction. Figure 1 If the current flows from the low voltage side to the high voltage side, it means that the current working mode of the DC converter is the boost mode. Figure 1 The high-voltage side of the DC converter flows to the low-voltage side, which means that the current working mode of the DC converter is the buck mode. Of course, in other implementations, there can be other determination methods. For example, in one case, when using the DC converter, after the user connects the DC converter to the battery and the load respectively, the user operates in the host computer so that the DC converter starts working. At this time, the battery can supply power to the load through the DC converter, and at this time, it can be determined based on the instructions from the host computer that it is currently in the boost mode, and then the on-off control of the corresponding switch will be performed according to the boost mode. On the contrary, after the user connects the DC converter to the battery and the power supply respectively, the user operates in the host computer so that the DC converter starts working. At this time, the power supply can charge the battery through the DC converter, and at this time, it can be determined based on the instructions from the host computer that it is currently in the buck mode, and then the on-off control of the corresponding switch will be performed according to the buck mode. For another example, in one case, although a DC converter supporting two working modes is used, the user locks the mode based on its actual needs, such as locking it to the buck mode, and then it can be directly determined that the current working mode of the DC converter is the buck mode.

[0076] Step S302: Determine the deviation state and deviation duration of the sampled current of the specified phase of the DC converter; wherein the deviation state includes sampling advance and sampling lag.

[0077] The DC converter can be a single-phase or multi-phase DC converter in parallel. The specified phase in the DC converter described in this application can be any phase in the DC converter. That is to say, the scheme of this application takes any phase in the DC converter as an example to illustrate the calibration of the sampled current. For other phases, the principle of the scheme of this application can be referred to to improve the current accuracy. Ideally, the value of the sampled current should be equal to the theoretical value, but as described above, the drive delay and the sampling circuit delay will affect the sampling, causing the sampling current to appear ahead or behind. Therefore, in order to effectively realize compensation later, it is necessary to determine the deviation state and deviation duration of the sampled current. The deviation state includes the two states of sampling ahead and sampling behind, and the deviation duration reflects the difference between the moment of current sampling and the theoretical moment.

[0078] There may be many specific implementations for determining the deviation state and deviation duration of the sampled current. For example, the determination may be based on a current variation curve.

[0079] Specifically, in a specific implementation of the present invention, determining the deviation state of the sampled current of the specified phase of the DC converter may specifically include:

[0080] Determine a current variation curve at a sampling position of a specified phase of the DC converter;

[0081] Based on the current variation curve, the theoretical current in the current rising stage and the theoretical current in the current falling stage are determined;

[0082] When it is determined that the sampled current in the current rising stage is lower than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is higher than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling ahead;

[0083] When it is determined that the sampled current in the current rising stage is higher than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is lower than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling hysteresis.

[0084] For easier understanding, please refer to Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of the principle of sampling ahead of time. Figure 5 For ease of description, in this application, the theoretical current in the current rising stage, that is, the theoretical current sampling value when the IGBT is turned on, is recorded as I up , and the sampling current in the current rising stage obtained by the sampling circuit is recorded as I up_real Accordingly, the theoretical current in the current drop phase, that is, the theoretical current sampling value when the IGBT is turned off, is recorded as Idown , and the sampling current in the current falling stage obtained by the sampling circuit is recorded as I down_real In addition, as described above, usually, the current direction is negative in boost mode and positive in buck mode. Figure 4 and Figure 5 For ease of description and understanding, the currents are all positive, that is, the currents in the figure can be regarded as the absolute values ​​of the currents.

[0085] As described above, if the DC converter is a multi-phase staggered parallel DC converter, current sampling will be performed on each phase, and the sampled current of each phase can be compensated according to the principle of the present application. The present application is to explain the compensation principle of one phase. The sampling position of the DC converter's specified phase is also the inductance position of the phase, so the sampled current is also the inductance current of the phase. The current change curve at the sampling position can be obtained, for example, by an oscilloscope device, such as Figure 4 and Figure 5 All of them take the V phase among the three phases as an example. Figure 4 and Figure 5 The current change curve in is the current change curve at the sampling position of the V phase, that is, the current change curve of the V phase inductor current. The oscilloscope device can be an oscilloscope. By connecting the oscilloscope device to the sampling position, the real-time current change at the sampling position can be displayed, that is, the current change curve at the sampling position is obtained.

[0086] In a switching cycle, after the IGBT is turned on, the inductor current will increase, and after the IGBT is turned off, the inductor current will decrease. Figure 4 and Figure 5 It can be seen that the current change curve at the sampling position changes accordingly with the on and off of the IGBT. In the current rising stage, the theoretical current sampling value I up It should be at the midpoint of the IGBT conduction (high level) period. Similarly, in the current drop phase, the theoretical current sampling value I down It should be the midpoint of the IGBT turn-off (low level) period. Therefore, after the current change curve at the sampling position is determined by the oscilloscope device, the current at the midpoint of the current rising stage can be used as the theoretical current I in the current rising stage. up , and the current at the midpoint of the current drop phase is taken as the theoretical current I down .

[0087] The sampling current in the current rising stage and the sampling current in the current falling stage can be obtained by sampling the sampling circuit, see Figure 4 and Figure 5Specifically, current sampling is triggered at the rising edge and falling edge of the synchronization signal. As described above, due to the influence of drive delay and sampling circuit delay, sampling advance or sampling lag may occur.

[0088] If the sampling is ahead, see Figure 4 , it can be seen that the sampling current I up_real Will be lower than the theoretical current I during the current rise phase up , and the sampling current I in the current falling phase down_real It will be higher than the theoretical current I during the current rise phase. down , that is, the sampling current I in the current rising stage up_real The sampling time of the current drop phase and the sampling current I down_real The sampling time of is always before the theoretical sampling time. If the sampling is delayed, refer to Figure 5 , it can be seen that the sampling current I up_real It will be higher than the theoretical current I during the current rise phase. up , and the sampling current I in the current falling phase down_real Will be lower than the theoretical current I during the current rise phase down , that is, the sampling current I in the current rising stage up_real The sampling time of the current drop phase and the sampling current I down_real The sampling time of the theoretical sampling point is after the sampling time of the theoretical sampling point.

[0089] Therefore, in this embodiment, when it is determined that the sampled current in the current rising stage is lower than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is higher than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling advance, and accordingly, when it is determined that the sampled current in the current rising stage is higher than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is lower than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling lag.

[0090] It can be seen that this implementation method can determine the deviation state of the sampling current by numerical comparison, which is easy to implement. In addition, it can be understood that in this implementation method, when performing the above comparison, only I up and I up_real , or we can just compare I down and I down_real , or we can compare I up and I up_real Compare I down and I down_real, is to take into account that in some cases, when setting the sampling, for example, only the sampling of the current rising stage is set, that is, there is no need to sample the current falling stage. For such a situation, it is only necessary to compare I up and I up_real The deviation state of the sampled current can be determined. On the contrary, if only the sampling of the current falling stage is set, that is, there is no need to sample the current rising stage, in such a case, only the comparison of I down and I down_real The deviation state of the sampled current can be determined. If current sampling is performed in both the current rising stage and the current falling stage, then only I up and I up_real , or just compare I down and I down_real , or both compare I up and I up_real Compare I down and I down_real , it can be set according to actual needs, which ensures the flexibility of this application solution.

[0091] In addition, it should be noted that for a specific device, that is, when both the software and hardware are determined, the deviation state of the sampling current is determined and will not change with the carrier cycle. Therefore, in practical applications, the deviation state of the sampling current can be determined in advance and written into the storage device, so that when the sampling current correction system executes the scheme of the present application, the deviation state of the sampling current can be determined by reading the data in the storage device. Similarly, the deviation duration of the sampling current can also be determined in advance and written into the storage device, so that when the sampling current correction system executes the scheme of the present application, the deviation duration of the sampling current can be determined by reading the data in the storage device.

[0092] In a specific implementation of the present invention, determining the deviation duration of the sampled current of a specified phase of the DC converter may specifically include:

[0093] Determine a current variation curve at a sampling position of a specified phase of the DC converter;

[0094] Based on the current variation curve, the theoretical current in the current rising stage and the theoretical current in the current falling stage are determined;

[0095] Determine the difference between the time corresponding to the theoretical current in the current rising stage on the current change curve and the time corresponding to the sampled current in the current rising stage on the current change curve within a single carrier cycle, and use it as the deviation duration of the sampled current;

[0096] Alternatively, the difference between the time corresponding to the theoretical current in the current decreasing phase on the current variation curve and the time corresponding to the sampled current in the current decreasing phase on the current variation curve in a single carrier cycle is determined and used as the deviation duration of the sampled current.

[0097] This implementation takes into account that when determining the deviation duration of the sampling current, it can also be determined based on the current change curve at the sampling position, which is relatively simple and convenient in implementation, and can be determined in advance as described above. Figure 4 and Figure 5 Based on the current change curve, the theoretical current I in the current rising stage can be determined. up The theoretical current I during the current drop phase down .

[0098] Taking the current rising stage as an example, it is necessary to determine the theoretical current I in the current rising stage within a single carrier cycle. up The corresponding moment on the current change curve is called the first moment for convenience of description. Figure 4 For example, Figure 4 I shown in up The horizontal axis position of the current. And it is necessary to determine the sampling current I in the current rising phase within this carrier cycle. up_real The corresponding moment on the current change curve is called the second moment for convenience of description, that is, Figure 4 I shown in up_real The horizontal axis position of the first moment and the second moment is the deviation duration of the determined sampling current. Figure 4 The deviation duration △t is recorded in the middle.

[0099] The deviation duration of the sampling current can also be determined through the current drop phase, still based on Figure 4 For example, it is to determine I down The horizontal axis position is related to I down_real The deviation of the horizontal axis position is used as the determined deviation time length △t of the sampling current.

[0100] That is to say, in this implementation, the difference in occurrence time between the theoretical current in the current rising stage and the sampled current in the current rising stage is obtained through the current change curve within a single carrier cycle as the deviation duration of the sampled current. Alternatively, the difference in occurrence time between the theoretical current in the current falling stage and the sampled current in the current falling stage is used as the deviation duration of the sampled current, which is simple and easy to implement.

[0101] Step S303: Based on the working mode and the deviation duration, determine a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase.

[0102] After determining the working mode and deviation duration, the first compensation amount and / or the second compensation amount can be determined. The specific calculation method can be set and adjusted according to actual needs, as long as the first compensation amount can accurately reflect the deviation between the sampled current and the theoretical current in the current rising stage, and the second compensation amount can accurately reflect the deviation between the sampled current and the theoretical current in the current falling stage.

[0103] For example, in a specific implementation of the present invention, step S303 may specifically include:

[0104] Step 1: Based on the working mode, determine the forward duty cycle D and the inductor current ripple △I in the working mode;

[0105] Step 2: Based on the forward duty cycle D, the inductor current ripple △I, the carrier period T and the deviation time △t, determine a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising stage, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling stage;

[0106] Since the current has positive and negative sides, the positive duty cycle D in the present application solution represents the duty cycle corresponding to the increase in the absolute value of the current in the working mode.

[0107] This implementation takes into account that the forward duty cycle D and the inductor current ripple △I are calculated differently in different working modes, which will affect the subsequent compensation amount calculation. Therefore, it is necessary to determine the forward duty cycle D and the inductor current ripple △I in the working mode based on the working mode. After that, the first compensation amount and / or the second compensation amount can be determined based on the forward duty cycle D, the inductor current ripple △I, the carrier period T and the deviation time △t. This implementation can effectively ensure the accuracy of the first compensation amount and the second compensation amount.

[0108] When determining the forward duty cycle D and the inductor current ripple ΔI in the working mode, there may be multiple specific methods. For example, in one specific implementation, the above step 1 may specifically include:

[0109] When the working mode is the step-down mode, according to the low-voltage side voltage U L The high voltage side voltage U H , determine the forward duty cycle D in buck mode;

[0110] Determine the low voltage side voltage U L , the carrier period T, and the product of 1-D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the buck mode is obtained;

[0111] When the working mode is boost mode, according to the low voltage side voltage U L The high voltage side voltage U H , determine the forward duty cycle D in boost mode;

[0112] Determine the low voltage side voltage U L , the product of the carrier period T, and the forward duty cycle D, and based on the product and the inductance Ln at the sampling position, the inductor current ripple △I in the boost mode is obtained.

[0113] In this implementation, for the step-down mode, it is necessary to adjust the voltage U of the low-voltage side of the DC converter according to the voltage L The high voltage side voltage U H Determine the forward duty cycle D in the buck mode. Specifically, the low-voltage side voltage U of the DC converter can be directly L The high voltage side voltage U H The ratio of the forward duty cycle D in the buck mode can be expressed as D=U L / U H The inductor current ripple △I is the difference between the maximum current and the minimum current. This implementation method takes into account that the time for the current to rise / fall is related to the forward duty cycle D, and the rate of rise / fall is related to the size of the inductance Ln at the sampling position. The larger the inductance Ln, the greater the rate of rise / fall. Both will affect the inductor current ripple △I. Therefore, in the buck mode, the product of the low-voltage side voltage UL, the carrier period T, and 1-D can be determined, and the product is divided by the inductance Ln at the sampling position. The result is the inductor current ripple △I in the buck mode, that is, in the buck mode, the inductor current ripple △I=[U L ×T×(1-D)] / Ln.

[0114] For the boost mode, the low-voltage side voltage U of the DC converter can also be L The high voltage side voltage U H Determine the forward duty cycle D in the buck mode. For example, generally speaking, the low-voltage side voltage U of the DC converter can be determined. L The high voltage side voltage U H The ratio of 1 to the ratio is used as the forward duty cycle D in the boost mode, which can be expressed as D = 1-(U L / U H). In boost mode, the product of the low voltage side voltage UL, carrier period T, and forward duty cycle D can usually be determined, and the product is divided by the inductance Ln at the sampling position. The result is the inductor current ripple △I in boost mode, that is, in boost mode, the inductor current ripple △I=[U L ×T×D)] / Ln.

[0115] In this implementation, the forward duty cycle D and the inductor current ripple △I in different working modes can be determined based on simple calculations, which is simple and convenient to implement.

[0116] In a specific implementation of the present invention, the above step 2 may specifically include:

[0117] Based on the forward duty cycle D and the carrier cycle T, the duration of the current rising phase in a single carrier cycle is determined as the rising duration t1;

[0118] Determine the proportion of the deviation duration in the rising duration t1, and determine the first compensation amount according to the proportion of the deviation duration in the rising duration t1 and the inductor current ripple △I;

[0119] Based on the forward duty cycle D and the carrier cycle T, the duration of the current falling phase in a single carrier cycle is determined as the falling duration t2;

[0120] The proportion of the deviation duration in the rising duration t2 is determined, and the second compensation amount is determined according to the proportion of the deviation duration in the rising duration t2 and the inductor current ripple ΔI.

[0121] See also Figure 4 and Figure 5 Based on the forward duty cycle D and the carrier period T, the duration of the current rise phase in a single carrier period can be determined as the rise time t1, which can be expressed as D×T. The larger the deviation time, the larger the first compensation amount. Therefore, the proportion of the deviation time in the rise time t1 can be determined and multiplied by the inductor current ripple △I. The result is used as the determined first compensation amount, that is, the first compensation amount is . Here △t is the deviation duration.

[0122] Based on the forward duty cycle D and the carrier cycle T, the duration of the current drop phase in a single carrier cycle can also be determined as the drop duration t2. The drop duration t2 can be expressed as (1-D)×T. The larger the deviation duration, the larger the second compensation amount. Therefore, the proportion of the deviation duration in the rise duration t2 can be determined and multiplied by the inductor current ripple △I. The result is used as the determined second compensation amount, that is, the second compensation amount is .

[0123] It can be seen that in this implementation, the first compensation amount and the second compensation amount can be conveniently and accurately determined, so that the obtained first compensation amount can accurately reflect the deviation between the sampled current in the current rising stage and the theoretical current, and the second compensation amount can accurately reflect the deviation between the sampled current in the current falling stage and the theoretical current.

[0124] Step S304: Based on the deviation state, the sampling current of the corresponding stage is compensated by the first compensation amount and / or the second compensation amount.

[0125] After obtaining the first compensation amount and / or the second compensation amount, the sampling current of the corresponding stage needs to be compensated according to the deviation state. It can be seen that the first compensation amount and / or the second compensation amount are the compensation amounts obtained after considering the working mode and the deviation duration, and when performing compensation, the sampling current of the corresponding stage needs to be compensated according to the deviation state. That is to say, in the present application scheme, the accurate compensation of the sampling current is achieved after comprehensively considering the working mode, the deviation duration and the deviation state.

[0126] In a specific implementation of the present invention, step S304 may specifically include:

[0127] When the deviation state is sampling ahead, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the current value after compensation in the current rising stage; the sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the current value after compensation in the current falling stage;

[0128] When the deviation state is sampling lag, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the compensated current value in the current rising stage. The sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the compensated current value in the current falling stage.

[0129] Generally, when the deviation state is sampling advance, the sampled current in the current rising stage can be superimposed with the first compensation amount, and the result obtained is used as the compensated current value in the current rising stage, and the sampled current in the current falling stage is subtracted from the second compensation amount, and the result obtained is used as the compensated current value in the current falling stage. Correspondingly, when the deviation state is sampling lag, the sampled current in the current rising stage can be subtracted from the first compensation amount, and the result obtained is used as the compensated current value in the current rising stage, and the sampled current in the current falling stage is superimposed with the second compensation amount, and the result obtained is used as the compensated current value in the current falling stage.

[0130] In the above implementation manner, the first compensation amount is , the second compensation amount is Take this as an example to illustrate.

[0131] When the deviation state is sampling ahead, for buck mode, since D = U L / U H , and △I=[U L ×T×(1-D)] / Ln, therefore, for this case, the first compensation amount in the buck mode can be specifically expressed as And because the sampling is ahead of time, it is necessary to calculate the sampling current in the current rising stage and the first compensation amount, specifically adding the two together. Therefore, in the buck mode, in the current rising stage, the current value obtained after compensation is Ideally, the value obtained should be the same as the theoretical value in the current rising stage. In this case, the second compensation amount in the buck mode can be specifically expressed as Since the sampling is ahead of time, it is necessary to calculate the sampled current in the current drop stage with the second compensation amount. Specifically, the sampled current in the current drop stage is subtracted from the second compensation amount. Therefore, in the current drop stage, the current value obtained after compensation is , ideally, the obtained value should be the same as the theoretical value during the current falling phase.

[0132] When the deviation state is sampling ahead, for boost mode, since D=1-(U L / U H ), and △I=[U L ×T×D)] / Ln, therefore, for this case, the first compensation amount in the boost mode can be specifically expressed as And because the sampling is ahead of time, it is necessary to calculate the sampling current in the current rising stage and the first compensation amount, specifically adding the two together. Therefore, in the boost mode, in the current rising stage, the current value obtained after compensation is Ideally, the value obtained should be the same as the theoretical value in the current rising stage. In this case, the second compensation amount in the boost mode can be specifically expressed as Since the sampling is ahead of time, it is necessary to calculate the sampled current in the current drop stage with the second compensation amount. Specifically, the sampled current in the current drop stage can be subtracted from the second compensation amount. Therefore, in the current drop stage, the current value obtained after compensation is , ideally, the obtained value should be the same as the theoretical value during the current falling phase.

[0133] When the deviation state is sampling hysteresis, for buck mode, since D = U L / U H , and △I=[U L ×T×(1-D)] / Ln, therefore, for this case, the first compensation amount in the buck mode can be specifically expressed as And because of the sampling lag, the sampled current in the current rising stage is calculated with the first compensation amount. Specifically, the sampled current in the current rising stage is subtracted from the first compensation amount, and the result is used as the compensated current value in the current rising stage. Therefore, in the buck mode, in the current rising stage, the current value obtained after compensation is Ideally, the value obtained should be the same as the theoretical value in the current rising stage. In this case, the second compensation amount in the buck mode can be specifically expressed as Due to the sampling lag, it is necessary to calculate the sampling current in the current drop phase and the second compensation value. Specifically, the two are added together, that is, the current value obtained after compensation in the current drop phase , ideally, the obtained value should be the same as the theoretical value during the current falling phase.

[0134] When the deviation state is sampling hysteresis, for boost mode, since D=1-(U L / U H ), and △I=[U L ×T×D)] / Ln, therefore, for this case, the first compensation amount in the boost mode can be specifically expressed as And because of the sampling lag, it is necessary to calculate the sampled current in the current rising stage with the first compensation amount. Specifically, the sampled current in the current rising stage is subtracted from the first compensation amount, and the result is used as the compensated current value in the current rising stage. Therefore, in the boost mode, in the current rising stage, the current value obtained after compensation is Ideally, the value obtained should be the same as the theoretical value in the current rising stage. In this case, the second compensation amount in the boost mode can be specifically expressed as Due to the sampling lag, it is necessary to calculate the sampling current in the current drop phase and the second compensation value. Specifically, the two are superimposed, that is, the current value obtained after compensation in the current drop phase Ideally, the value obtained should be the same as the theoretical value during the current drop phase.

[0135] It can be seen that the first compensation amount in the buck mode can be specifically expressed as , the second compensation amount can be specifically expressed as , the first compensation amount in the boost mode can be specifically expressed as , the second compensation amount can be specifically expressed as , and then according to the deviation state, choose to add or subtract the corresponding compensation amount, and the compensated current can be determined simply and conveniently. In addition, in practical applications, in order to simplify the calculation, the calculation method of the first compensation amount and the second compensation amount in the buck mode and the calculation method of the first compensation amount and the second compensation amount in the boost mode shown here can be directly recorded and stored, and the deviation time △t and the inductor current Ln can be predetermined. It can be seen that it only needs to be combined with the current forward duty cycle D and the low-voltage side voltage U L In addition, it can be understood that after obtaining the required compensation amount, it is not necessary to recalculate the compensation amount before adjusting the working mode, that is, the compensation amount can be calculated once after starting the work, and in each subsequent carrier cycle, it is only necessary to perform the operation of step S304 to compensate the corresponding sampled current.

[0136] In a specific embodiment of the present invention, the DC converter is a multi-phase interleaved parallel DC converter, and the sampling current correction method may further include:

[0137] Based on the compensated current values, current sharing control of the multi-phase interleaved parallel DC converter is performed;

[0138] Wherein, for each phase of the multi-phase interleaved parallel DC converter, the update of the phase sampling current adopts a double sampling double updating method, or a double sampling single updating method, or a single sampling single updating method;

[0139] The double sampling and double updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage and the current value of the phase compensated in the current rising stage are obtained by the sampling current correction method as two sampling points obtained in the carrier cycle;

[0140] The single sampling and single updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage is obtained by the sampling current correction method, or the current value of the phase compensated in the current falling stage is obtained as one sampling point obtained in the carrier cycle;

[0141] The double sampling and single updating method means that in each carrier cycle, the average value of the current value of the phase compensated in the current rising stage and the average value of the current value of the phase compensated in the current falling stage obtained by the sampling current correction method are used as one sampling point obtained in the carrier cycle.

[0142] This implementation method takes into account that, in order to ensure flexibility, when updating the sampled current, a double sampling and double updating method, a double sampling and single updating method, and a single sampling and single updating method are supported. For the double sampling and double updating method, sampling and compensation are performed in both the current rising stage and the current falling stage, which means that 2 sampling points can be obtained in a single carrier cycle, which is suitable for occasions with high requirements for the sampling frequency. Correspondingly, for the single sampling and single updating method, sampling and compensation are performed in the current rising stage or the current falling stage, which means that 1 sampling point can be obtained in a single carrier cycle, which is suitable for occasions where the sampling frequency requirements are not particularly high.

[0143] The double sampling and single update method will sample and compensate in both the current rising stage and the current falling stage, but will further calculate the average value of the two. It can be understood that the current values ​​obtained after compensation in the current rising stage and the current falling stage should be consistent under ideal circumstances. However, due to interference, measurement errors and other reasons, there may be a certain degree of deviation between the two. Therefore, by calculating the average value of the two as a sampling point obtained within the carrier period, the accuracy of the sampling point can be further guaranteed, which is conducive to further ensuring the effective implementation of current sharing and improving control accuracy.

[0144] By applying the technical solution provided in the embodiment of the present invention, considering that adjusting the sampling moment is prone to errors and thus affecting the reliability of the control algorithm, the sampling moment is not adjusted. Instead, the sampling current is compensated by the compensation amount, so that the value after compensation is a more accurate sampling value, thereby ensuring the reliability of the current sharing control.

[0145] Specifically, different working modes and different deviation durations of the sampling current will affect the calculation of the compensation amount, and the sampling moment may be the current rising stage or the current falling stage. Therefore, in the present application scheme, based on the working mode and the deviation duration, a first compensation amount for reflecting the deviation between the sampling current in the current rising stage and the theoretical current and / or a second compensation amount for reflecting the deviation between the sampling current in the current falling stage and the theoretical current will be determined to ensure the flexibility of the scheme. After obtaining the first compensation amount and / or the second compensation amount, it is necessary to combine the deviation state of the sampling current, that is, whether the sampling is advanced or delayed, to realize compensation for the sampling current in the corresponding stage, so that the current value after compensation is a more accurate value, effectively eliminating the sampling error, which is also conducive to ensuring the reliability of the current sharing control.

[0146] In summary, the present application scheme compensates the sampled current through the compensation amount, effectively eliminates the sampling error, and does not need to adjust the sampling time, which is conducive to ensuring the accuracy and reliability of current sharing control.

[0147] Corresponding to the above method embodiment, an embodiment of the present invention further provides a sampling current correction system, which can be referred to in correspondence with the above.

[0148] See also Figure 6 FIG. 1 is a schematic diagram of the structure of a sampling current correction system in the present invention, comprising:

[0149] The working mode determination module 601 is used to determine the current working mode of the DC converter; wherein the working mode includes a boost mode and a buck mode;

[0150] The deviation condition determination module 602 is used to determine the deviation state and deviation duration of the sampled current of the specified phase of the DC converter; wherein the deviation state includes sampling advance and sampling lag;

[0151] A compensation amount determination module 603 is used to determine, based on the working mode and the deviation duration, a first compensation amount used to reflect the deviation between the sampled current and the theoretical current in the current rising stage, and / or a second compensation amount used to reflect the deviation between the sampled current and the theoretical current in the current falling stage;

[0152] The compensation execution module 604 is used to compensate the sampling current of the corresponding stage through the first compensation amount and / or the second compensation amount based on the deviation state.

[0153] In a specific implementation of the present invention, the deviation state determination unit of the deviation state determination module 602 is used to:

[0154] Determine a current variation curve at a sampling position of a specified phase of the DC converter;

[0155] Based on the current variation curve, the theoretical current in the current rising stage and the theoretical current in the current falling stage are determined;

[0156] When it is determined that the sampled current in the current rising stage is lower than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is higher than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling ahead;

[0157] When it is determined that the sampled current in the current rising stage is higher than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is lower than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling hysteresis.

[0158] In a specific implementation of the present invention, the deviation situation determination module 602, a deviation duration determination unit, is used to:

[0159] Determine a current variation curve at a sampling position of a specified phase of the DC converter;

[0160] Based on the current variation curve, the theoretical current in the current rising stage and the theoretical current in the current falling stage are determined;

[0161] Determine the difference between the time corresponding to the theoretical current in the current rising stage on the current change curve and the time corresponding to the sampled current in the current rising stage on the current change curve within a single carrier cycle, and use it as the deviation duration of the sampled current;

[0162] Alternatively, the difference between the time corresponding to the theoretical current in the current decreasing phase on the current variation curve and the time corresponding to the sampled current in the current decreasing phase on the current variation curve in a single carrier cycle is determined and used as the deviation duration of the sampled current.

[0163] In a specific implementation of the present invention, the compensation amount determination module 603 includes:

[0164] A parameter calculation unit, used for determining a forward duty cycle D and an inductor current ripple △I in the working mode based on the working mode;

[0165] A compensation amount calculation unit, for determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase, based on the forward duty cycle D, the inductor current ripple △I, the carrier period T and the deviation time △t;

[0166] The forward duty cycle D represents the duty cycle corresponding to the increase of the absolute value of the current in the working mode.

[0167] In a specific implementation of the present invention, the compensation amount calculation unit is specifically used to:

[0168] Based on the forward duty cycle D and the carrier cycle T, the duration of the current rising phase in a single carrier cycle is determined as the rising duration t1;

[0169] Determine the proportion of the deviation duration in the rising duration t1, and determine a first compensation amount according to the proportion of the deviation duration in the rising duration t1 and the inductor current ripple ΔI;

[0170] Based on the forward duty cycle D and the carrier cycle T, the duration of the current falling phase in a single carrier cycle is determined as the falling duration t2;

[0171] The proportion of the deviation duration in the rising duration t2 is determined, and the second compensation amount is determined according to the proportion of the deviation duration in the rising duration t2 and the inductor current ripple ΔI.

[0172] In a specific implementation of the present invention, the parameter calculation unit is specifically used for:

[0173] When the working mode is the step-down mode, according to the low-voltage side voltage U L With high voltage side voltage U H , determine the forward duty cycle D in buck mode;

[0174] Determine the low voltage side voltage U L , the carrier period T, and the product of 1-D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the buck mode is obtained;

[0175] When the working mode is the boost mode, according to the low voltage side voltage U L With high voltage side voltage U H , determine the forward duty cycle D in buck mode;

[0176] Determine the low voltage side voltage U L , the product of the carrier period T, and the forward duty cycle D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the boost mode is obtained.

[0177] In a specific embodiment of the present invention, the DC converter is a multi-phase staggered parallel DC converter, and the sampling current correction system further includes a current sharing control module for:

[0178] Based on the compensated current values, current sharing control of the multi-phase interleaved parallel DC converter is performed;

[0179] Wherein, for each phase of the multi-phase interleaved parallel DC converter, the update of the phase sampling current adopts a double sampling double updating method, or a double sampling single updating method, or a single sampling single updating method;

[0180] The double sampling and double updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage and the current value of the phase compensated in the current falling stage are obtained by the sampling current correction method as two sampling points obtained in the carrier cycle;

[0181] The single sampling and single updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage is obtained by the sampling current correction method, or the current value of the phase compensated in the current falling stage is obtained as one sampling point obtained in the carrier cycle;

[0182] The double sampling and single updating method means that in each carrier cycle, the average value of the current value of the phase compensated in the current rising stage and the average value of the current value of the phase compensated in the current falling stage obtained by the sampling current correction method are used as one sampling point obtained in the carrier cycle.

[0183] In a specific implementation of the present invention, the compensation execution module 604 is specifically used to:

[0184] When the deviation state is sampling advance, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the current value after compensation in the current rising stage, and the sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the current value after compensation in the current falling stage;

[0185] When the deviation state is sampling lag, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the compensated current value in the current rising stage; the sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the compensated current value in the current falling stage.

[0186] Corresponding to the above method and system embodiments, an embodiment of the present invention further provides a sampling current correction device and a computer-readable storage medium, which can be referred to in correspondence with the above.

[0187] See also Figure 7 FIG. 1 is a schematic diagram of the structure of a sampling current correction device in the present invention, comprising:

[0188] Memory 701, used for storing computer programs;

[0189] The processor 702 is used to execute a computer program to implement the steps of the sampling current correction method in any of the above embodiments.

[0190] The computer readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the sampling current correction method in any of the above embodiments are implemented. The computer readable storage medium mentioned here includes random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the technical field.

[0191] It should also be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0192] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. Specific examples are used in this application to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A sampling current correction method, characterized in that: include: Determine the current working mode of the DC converter; wherein the working mode includes a boost mode and a buck mode; Determine the deviation state and deviation duration of the sampled current of the specified phase of the DC converter; wherein the deviation state includes sampling advance and sampling lag; Based on the working mode and the deviation duration, determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase; Based on the deviation state, the sampling current of the corresponding stage is compensated by the first compensation amount and / or the second compensation amount.

2. The sampling current correction method according to claim 1, characterized in that: Determining the deviation state of the sampled current of the specified phase of the DC converter includes: Determining a current variation curve at a sampling position of a specified phase of the DC converter; Based on the current variation curve, determining a theoretical current in a current rising phase and a theoretical current in a current falling phase; When it is determined that the sampled current in the current rising stage is lower than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is higher than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling ahead; When it is determined that the sampled current in the current rising stage is higher than the theoretical current in the current rising stage, and / or when it is determined that the sampled current in the current falling stage is lower than the theoretical current in the current rising stage, the deviation state of the sampled current is determined to be sampling hysteresis.

3. The sampling current correction method according to claim 1, characterized in that: Determine the deviation duration of the sampling current, including: Determining a current variation curve at a sampling position of a specified phase of the DC converter; Based on the current variation curve, determining a theoretical current in a current rising phase and a theoretical current in a current falling phase; Determine the difference between the time corresponding to the theoretical current in the current rising stage on the current change curve and the time corresponding to the sampled current in the current rising stage on the current change curve within a single carrier cycle, and use it as the deviation duration of the sampled current; Alternatively, the difference between the time corresponding to the theoretical current in the current decreasing phase on the current variation curve and the time corresponding to the sampled current in the current decreasing phase on the current variation curve within a single carrier cycle is determined and used as the deviation duration of the sampled current.

4. The sampling current correction method according to claim 1, characterized in that: Based on the working mode and the deviation duration, determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase, includes: Based on the working mode, determining the forward duty cycle D and the inductor current ripple ΔI in the working mode; Based on the forward duty cycle D, the inductor current ripple ΔI, the carrier period T and the deviation duration Δt, determine a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase; The forward duty cycle D represents the duty cycle corresponding to the increase of the absolute value of the current in the working mode.

5. The sampling current correction method according to claim 4, characterized in that: Based on the forward duty cycle D, the inductor current ripple ΔI, the carrier period T and the deviation duration Δt, determining a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase, including: Based on the forward duty cycle D and the carrier cycle T, the duration of the current rising phase in a single carrier cycle is determined as the rising duration t1; Determine the proportion of the deviation duration in the rising duration t1, and determine a first compensation amount according to the proportion of the deviation duration in the rising duration t1 and the inductor current ripple ΔI; Based on the forward duty cycle D and the carrier cycle T, the duration of the current falling phase in a single carrier cycle is determined as the falling duration t2; The proportion of the deviation duration in the rising duration t2 is determined, and the second compensation amount is determined according to the proportion of the deviation duration in the rising duration t2 and the inductor current ripple ΔI.

6. The sampling current calibration method according to claim 4, characterized in that: Based on the working mode, determining the forward duty cycle D and the inductor current ripple ΔI in the working mode includes: When the working mode is the step-down mode, according to the low-voltage side voltage U L With high voltage side voltage U H , determine the forward duty cycle D in buck mode; Determine the low voltage side voltage U L , the carrier period T, and the product of 1-D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the buck mode is obtained; When the working mode is the boost mode, according to the low voltage side voltage U L With high voltage side voltage U H , determine the forward duty cycle D in buck mode; Determine the low voltage side voltage U L , the product of the carrier period T, and the forward duty cycle D, and according to the product and the inductance Ln at the sampling position, the inductor current ripple △I in the boost mode is obtained.

7. The sampling current calibration method according to claim 1, characterized in that: The DC converter is a multi-phase interleaved parallel DC converter, and the sampling current correction method further includes: Based on the compensated current values, current sharing control of the multi-phase interleaved parallel DC converter is performed; Wherein, for each phase of the multi-phase interleaved parallel DC converter, the update of the phase sampling current adopts a double sampling and double updating method, or a double sampling and single updating method, or a single sampling and single updating method; The double sampling and double updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage and the current value of the phase compensated in the current falling stage are obtained by the sampling current correction method as two sampling points obtained in the carrier cycle; The single sampling and single updating method means that in each carrier cycle, the current value of the phase compensated in the current rising stage, or the current value of the phase compensated in the current falling stage is obtained by the sampling current correction method as one sampling point obtained in the carrier cycle; The double sampling and single updating method means that in each carrier cycle, the average value of the current value of the phase compensated in the current rising stage and the average value of the current value of the phase compensated in the current falling stage obtained by the sampling current correction method are used as one sampling point obtained in the carrier cycle.

8. The sampling current calibration method according to any one of claims 1 to 7, characterized in that: Based on the deviation state, compensating the sampling current of the corresponding stage by using the first compensation amount and / or the second compensation amount includes: When the deviation state is sampling advance, the sampled current in the current rising stage is calculated with the first compensation amount, and the result is used as the current value after compensation in the current rising stage, and the sampled current in the current falling stage is calculated with the second compensation amount, and the result is used as the current value after compensation in the current falling stage; When the deviation state is sampling lag, the sampled current in the current rising phase is calculated with the first compensation amount, and the result is used as the compensated current value in the current rising phase; the sampled current in the current falling phase is calculated with the second compensation amount, and the result is used as the compensated current value in the current falling phase.

9. A sampling current correction system, characterized in that: include: A working mode determination module, used to determine the current working mode of the DC converter; wherein the working mode includes a boost mode and a buck mode; A deviation condition determination module, used to determine the deviation state and deviation duration of the sampled current of the specified phase of the DC converter; wherein the deviation state includes sampling advance and sampling lag; A compensation amount determination module, for determining, based on the working mode and the deviation duration, a first compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current rising phase, and / or a second compensation amount for reflecting the deviation between the sampled current and the theoretical current in the current falling phase; A compensation execution module is used to compensate the sampling current of the corresponding stage through the first compensation amount and / or the second compensation amount based on the deviation state.

10. A sampling current correction device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program to implement the steps of the sampling current correction method according to any one of claims 1 to 8.

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