An adaptive continuous-time linear equalizer and control method

Abstract

The application provides an adaptive continuous-time linear equalizer and a control method, the adaptive continuous-time linear equalizer comprising: a signal adjusting module, the signal adjusting module being configured with an adjustable resistance and an adjustable capacitance; the signal adjusting module being configured to: receive a data signal; perform high-frequency gain processing on the data signal according to a gain coefficient; an eye diagram calculation module, the eye diagram calculation module being configured to: obtain eye height data and eye width data according to the data signal; an adaptive module, the adaptive module being configured to: obtain an equalization coefficient according to the eye height data and the eye width data; the equalization coefficient being a resistance adjustment value of the adjustable resistance and a capacitance adjustment value of the adjustable capacitance; the signal adjusting module being controlled to operate according to the equalization coefficient; when the signal adjusting module operates according to the equalization coefficient, the data signal reaches a target equalization effect, so as to solve the problems that a current linear equalizer has a relatively long signal equalization processing process and the quality of the processed signal is not located at a maximum value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic devices, and in particular to an adaptive continuous-time linear equalizer and a control method. BACKGROUND

[0002] With the continuous evolution of communication technology, the demand for massive data interaction is increasing day by day, which increases the demand for high bandwidth and high-speed transmission of data. The serializer or deserializer circuit plays a crucial role in data transmission. However, in the process of data transmission, channel non-ideal factors such as loss, inter-symbol interference and reflection will cause the data at the sending end to be distorted when it reaches the receiving end.

[0003] In order to improve the transmission quality of the detected data signal, the receiving end of the serializer or deserializer circuit usually uses a continuous-time linear equalizer to compensate for the high-frequency components of the signal. The continuous-time linear equalizer has the advantages of simple structure and low power consumption, and can effectively compensate for the high-frequency components of the signal.

[0004] However, the current continuous-time linear equalizer cannot perform targeted high-frequency gain compensation on the detected data signal according to the detected data, resulting in a long process of signal equalization processing by the continuous-time linear equalizer, and the quality of the processed signal is not at the maximum value. SUMMARY

[0005] The present application provides an adaptive continuous-time linear equalizer and a control method to solve the technical problem that the current linear equalizer has a long process of signal equalization processing, and the quality of the processed signal is not at the maximum value.

[0006] The first aspect of the present application provides an adaptive continuous-time linear equalizer, comprising:

[0007] a signal conditioning module, the signal conditioning module being configured with an adjustable resistance and an adjustable capacitance; the signal conditioning module is configured to:

[0008] receive the data signal;

[0009] perform high-frequency gain processing on the data signal according to a gain coefficient; the gain coefficient is the amplification ratio of the signal conditioning module to the data signal;

[0010] an eye diagram calculation module, the eye diagram calculation module being configured to:

[0011] obtain eye height data and eye width data from the data signal;

[0012] an adaptive module, the adaptive module being configured to:

[0013] According to the eye height data and the eye width data, an equalization coefficient is obtained; the equalization coefficient is a resistance adjustment value of the adjustable resistor and a capacitance adjustment value of the adjustable capacitor;

[0014] The gain coefficient is adjusted to the equalization coefficient, and the signal adjustment module is controlled to operate according to the equalization coefficient;

[0015] When the signal adjustment module operates according to the equalization coefficient, the data signal achieves a target equalization effect.

[0016] In some embodiments, the eye diagram calculation module comprises:

[0017] A phase interpolator configured to:

[0018] According to the data signal, eye width data is obtained;

[0019] A digital-to-analog converter configured to:

[0020] According to the data signal, eye height data is obtained.

[0021] In some embodiments, the to-be-tested eye diagram comprises an eye detection area and an eye non-detection area.

[0022] The eye diagram calculation module further comprises:

[0023] A judging unit configured to:

[0024] Obtain an image scanning area of the phase interpolator or the digital-to-analog converter;

[0025] If the image scanning area is an eye detection area, a first control signal is generated;

[0026] If the image scanning area is an eye non-detection area, a second control signal is generated;

[0027] A control unit configured to:

[0028] According to the first control signal, the phase interpolator or the digital-to-analog converter is controlled to scan the to-be-tested eye diagram at a first preset step size;

[0029] According to the second control signal, the phase interpolator or the digital-to-analog converter is controlled to scan the to-be-tested eye diagram at a second preset step size; the second preset step size is greater than the first preset step size.

[0030] In some embodiments, the adaptive module is configured with a capacitance adjustment unit configured to perform a capacitance adjustment operation; the capacitance adjustment operation is configured to:

[0031] The capacitance value of the adjustable capacitor is decreased according to a preset value to obtain a capacitance adjustment value;

[0032] Eye height data and eye width data under the capacitance adjustment value are obtained;

[0033] A sum real-time value of the eye height data and the eye width data is calculated;

[0034] It is judged whether the sum real-time value is greater than a sum reference value, and if not, a target capacitance value is obtained based on the capacitance adjustment value;

[0035] If yes, the capacitance adjustment operation is repeatedly executed until the target capacitance value is obtained.

[0036] In some embodiments, the adaptive module is configured with a resistance adjustment unit, which is configured to perform a resistance adjustment operation: the resistance adjustment operation is configured to:

[0037] The resistance value of the adjustable resistance is increased according to a preset value to obtain a resistance adjustment value;

[0038] Eye height data and eye width data under the resistance adjustment value are obtained;

[0039] A sum real-time value of the eye height data and the eye width data is calculated;

[0040] It is judged whether the sum real-time value is greater than a sum reference value, and if not, a target resistance value is obtained based on the resistance adjustment value;

[0041] If yes, the resistance adjustment operation is repeatedly executed until the target resistance value is obtained.

[0042] The adaptive module is further configured to:

[0043] A balance coefficient is obtained based on the target capacitance value and the target resistance value.

[0044] In some embodiments, the sum reference value is determined by the following steps:

[0045] Eye height data and eye width data under a set environment are obtained; the set environment is configured such that the adjustable resistance is a minimum value and the adjustable capacitance is a maximum value;

[0046] A sum reference value of the eye height data and the eye width data is calculated.

[0047] In some embodiments, the signal adjustment module is configured with a TAS circuit;

[0048] The adjustable resistance and the adjustable capacitance are configured in the TAS circuit.

[0049] In some embodiments, the TAS circuit is configured with a high-pass circuit and a low-pass circuit.

[0050] The low-pass circuit is an RC low-pass filter.

[0051] In some embodiments, the signal conditioning module is further configured with a TIS circuit, which is electrically connected to the TAS circuit.

[0052] The TIS circuit is configured with a first inverter and a second inverter, which are respectively connected to the TAS circuit.

[0053] The second aspect of the present application provides a control method of an adaptive continuous-time linear equalizer, which is applied to the adaptive continuous-time linear equalizer of any one of the first aspect.

[0054] receiving a data signal;

[0055] performing high-frequency gain processing on the data signal according to a gain coefficient; the gain coefficient is an amplification ratio of the data signal;

[0056] obtaining eye height data and eye width data according to the data signal;

[0057] obtaining an equalization coefficient according to the eye height data and the eye width data; the equalization coefficient is a resistance adjustment value of an adjustable resistor and a capacitance adjustment value of an adjustable capacitor;

[0058] adjusting the gain coefficient to the equalization coefficient, and controlling a signal conditioning module to operate according to the equalization coefficient; the signal conditioning module is configured with the adjustable resistor and the adjustable capacitor;

[0059] wherein, when the signal conditioning module operates according to the equalization coefficient, the data signal achieves a target equalization effect.

[0060] The application provides an adaptive continuous-time linear equalizer and a control method, the adaptive continuous-time linear equalizer comprising: a signal conditioning module configured with an adjustable resistance and an adjustable capacitance; the signal conditioning module is configured to: receive the data signal; perform high-frequency gain processing on the data signal according to a gain coefficient; the gain coefficient is the amplification ratio of the signal conditioning module to the data signal; an eye diagram calculation module configured to: obtain eye height data and eye width data according to the data signal; an adaptive module configured to: obtain an equalization coefficient according to the eye height data and the eye width data; the equalization coefficient is the resistance adjustment value of the adjustable resistance and the capacitance adjustment value of the adjustable capacitance; the gain coefficient is adjusted to the equalization coefficient, and the signal conditioning module is controlled to operate according to the equalization coefficient; wherein when the signal conditioning module operates according to the equalization coefficient, the data signal reaches a target equalization effect, so as to realize linear equalizer reduction of signal equalization processing time length, and the signal quality after processing is located at a maximum value. BRIEF DESCRIPTION OF DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the application, the drawings needed in the embodiments will be briefly introduced below, and obviously, other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0062] Figure 1 It is a structural schematic diagram of the adaptive continuous-time linear equalizer in the application.

[0063] Figure 2 It is a structural schematic diagram of the eye diagram calculation module in the application.

[0064] Figure 3 It is a flow chart of the adaptive logic in the application.

[0065] Figure 4 It is a structural schematic diagram of the signal conditioning module in the application.

[0066] Figure 5 It is a frequency response curve diagram of the continuous-time linear equalizer normalization when the resistance value of the adjustment resistance is changed in the application.

[0067] Figure 6 It is a frequency response curve diagram of the continuous-time linear equalizer normalization when the capacitance value of the adjustment capacitance is changed in the application.

[0068] Figure 7 It is a schematic diagram of eye height data sampling in the application.

[0069] Figure 8 It is a schematic diagram of eye width data sampling in the application.

[0070] Figure 9 Figure 1 is a structural schematic diagram of an adaptive continuous-time linear equalizer based on a spectrum equalization method in the present application;

[0071] Figure 10 Figure 2 is a structural schematic diagram of an adaptive continuous-time linear equalizer based on an asynchronous sampling histogram in the present application;

[0072] Figure 11 Figure 3 is a structural schematic diagram of an adaptive continuous-time linear equalizer based on a random sigma tracking eye diagram detector in the present application;

[0073] Figure 12 Figure 4 is a structural schematic diagram of a traditional current mode logic continuous-time linear equalizer in the present application;

[0074] Figure 13 Figure 5 is a structural schematic diagram of a TAS-TIS with an active inductor as a load in the present application;

[0075] Figure 14 Figure 6 is a structural schematic diagram of a programmable two-path continuous-time linear equalizer in the present application;

[0076] Figure 15 Figure 7 is a structural schematic diagram of a continuous-time linear equalizer with a TAS-TIS structure in the present application.

[0077] BRIEF DESCRIPTION OF DRAWINGS

[0078] 1 - signal conditioning module; 2 - eye diagram calculation module; 21 - phase interpolator; 22 - digital-to-analog converter; 23 - judging unit; 24 - control unit; 3 - adaptive module. DETAILED DESCRIPTION

[0079] In order to make the person skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0080] Since in some technologies, the process of signal equalization processing by a linear equalizer is long, and the quality of the processed signal is not at the maximum, in order to solve the technical problem, the present application provides an adaptive continuous-time linear equalizer and a control method, which will be described below.

[0081] With the continuous evolution of communication technology, the demand for massive data interaction is increasing day by day, which increases the demand for high bandwidth and high speed transmission of data. SerDes (Serializer / De-serializer) circuit plays a crucial role in the interconnection transmission of chip to chip, board to board and system to system. However, in the process of data transmission, channel non-ideal factors such as loss, inter-symbol interference and reflection will cause the data of the sending end to be distorted when it reaches the receiving end. In order to improve the quality of data transmission, the SerDes receiving end usually adopts continuous time linear equalizer circuit. Continuous time linear equalizer circuit has the advantages of simple structure and low power consumption, and can effectively compensate the high frequency components of the signal.

[0082] However, for high-speed SerDes circuit, the continuous time linear equalizer at this stage still has the following problems:

[0083] As shown in Figure 9 , it is an adaptive continuous time linear equalizer based on frequency spectrum equalization method.

[0084] Because it is troublesome to manually configure the equalization parameters of the continuous time linear equalizer, and the flexibility is poor, the adaptive continuous time linear equalizer is used to realize parameter adaptive equalization. In the frequency spectrum equalization method, adaptive equalization is realized by comparing the high frequency component and the low frequency component of the signal power and generating a feedback signal until the power spectrum is balanced. However, the precision of this scheme is easily affected by process variation, and the capacitors in the filter and feedback loop occupy a large silicon area.

[0085] As shown in Figure 10 , it is an adaptive continuous time linear equalizer based on asynchronous sampling histogram.

[0086] In the adaptive equalization method based on asynchronous sampling histogram, the optimal value is obtained by traversing the histogram of different equalization degrees, which has the disadvantages of long equalization process and slow algorithm convergence.

[0087] As shown in Figure 11 , it is an adaptive continuous time linear equalizer based on random sigma tracking eye diagram detector.

[0088] In the adaptive equalization method based on random sigma tracking eye diagram detector, the enhancement gain of the continuous time linear equalizer is scanned to find the optimal enhancement gain of the continuous time linear equalizer that maximizes the eye opening area, which also has the trade-off between adaptation time and precision.

[0089] As shown in Figure 12 , it is a traditional CML (Current Mode Logic) type continuous time linear equalizer.

[0090] Traditional CML continuous-time linear equalizers (CMLs) create a feedback loop by introducing resistors and capacitors at the source of the input transistor. The coupling of the resistors and capacitors creates a degenerate structure, providing a high-pass path for the input signal, thereby compensating for the channel's high-frequency losses. The transfer function shows that this CML has one zero and two poles, limited single-stage high-frequency compensation capability, a narrow adjustment range, and bandwidth limited by the load capacitance. As data rates continue to increase, this has become difficult to meet anticipated requirements.

[0091] like Figure 13 As shown in FIG, it is a TAS-TIS structure with active inductance as load.

[0092] In a TAS-TIS structure with an active inductor as a load, a continuous-time linear equalizer uses the TAS-TIS structure and active inductors to expand bandwidth. However, for an adaptive system, the mid- and low-frequency gain is not adjustable, and the adjustment range is limited.

[0093] like Figure 14 As shown, it is a programmable dual-channel continuous-time linear equalizer.

[0094] In a programmable dual-channel continuous-time linear equalizer, mid- and low-frequency gains are adjustable over a wide range. However, the disadvantage is that adaptive continuous-time linear equalizers require an additional comparator load compared to manually controlled continuous-time linear equalizers. For adaptive systems, the subsequent load limits bandwidth compared to TAS-TIS architectures.

[0095] like Figure 15 As shown in FIG, a continuous time linear equalizer with a TAS-TIS structure.

[0096] The TAS-TIS CTLE structure offers adjustable mid- and low-frequency gain over a wide adjustment range. The TAS-TIS continuous-time linear equalizer topology offers low output impedance, extending bandwidth. However, its disadvantage is that the high-pass and low-pass circuits each consist of two differential pairs. While this improves high-frequency gain, it also increases power consumption. Furthermore, the multi-stage stacking creates a complex zero-pole environment, making adjustment less convenient than a single-stage circuit.

[0097] Depend on Figure 1 It can be seen that the first aspect of the present application provides an adaptive continuous-time linear equalizer, which is applied to an eye diagram detector, wherein the eye diagram detector is used to obtain a data signal; comprising:

[0098] A signal conditioning module 1 is configured with an adjustable resistance and an adjustable capacitance; the signal conditioning module 1 is configured to receive the data signal; the data signal is input through a channel, and the adaptive continuous-time linear equalizer is used to convert an unbalanced signal into an equalized signal, so that the unbalanced signal input into the adaptive continuous-time linear equalizer is input into the signal conditioning module 1 and converted into an equalized signal by the adaptive continuous-time linear equalizer.

[0099] According to the gain coefficient, the data signal is subjected to high-frequency gain processing; the gain coefficient is the amplification ratio of the signal conditioning module 1 to the data signal; an eye diagram calculation module 2 is configured to obtain eye height data and eye width data according to the data signal; an adaptive module 3 is configured to obtain an equalization coefficient according to the eye height data and the eye width data; the equalization coefficient is the resistance adjustment value of the adjustable resistance and the capacitance adjustment value of the adjustable capacitance; the gain coefficient is adjusted to the equalization coefficient to control the signal conditioning module 1 to operate according to the equalization coefficient; wherein when the signal conditioning module 1 operates according to the equalization coefficient, the data signal achieves a target equalization effect. Wherein when the data signal achieves the target equalization effect, the frequency response curve of the data signal tends to be flat within the Nyquist frequency. Wherein the Nyquist frequency is the minimum sampling frequency defined to prevent aliasing of the data signal.

[0100] In view of the problems of large area, long equalization process and slow algorithm convergence of the adaptive continuous-time linear equalizer, the application provides an adaptive continuous-time linear equalizer, and a structure of the adaptive continuous-time linear equalizer is shown in Figure 1 The main circuit includes a signal conditioning module 1, an eye diagram calculation module 2 and an adaptive module 3. The eye height and the eye width of the signal output by the signal conditioning module 1 are detected by the eye diagram calculation module 2, and then the adaptive module 3 switches the state of the corresponding switch in the signal conditioning module 1 according to the sum of the eye height and the eye width, so as to change the values of the resistance and the capacitance in the circuit of the signal conditioning module 1, thereby changing the high-frequency gain of the circuit of the signal conditioning module 1, realizing the equalization configuration of different channels, and improving the system bit error rate. The application is realized by a digital algorithm, and the balance between time and precision is broken by the application of non-uniform scanning of the eye diagram calculation module 2.

[0101] As shown in Figure 2 , it is a structure schematic diagram of the eye diagram calculation module 2.

[0102] In this embodiment, the eye diagram calculation module 2 comprises: a phase interpolator 21 configured to obtain eye width data according to the to-be-tested eye diagram; the phase interpolator 21 is used to obtain the eye width data of the to-be-tested eye diagram according to the data signal, and the specific detection process is as shown in Figure 8 .

[0103] a digital-to-analog converter 22 configured to obtain eye height data according to the data signal. The digital-to-analog converter 22 is used to obtain the eye height data of the to-be-tested eye diagram according to the data signal, and the specific detection process is as shown in Figure 7 .

[0104] In this embodiment, the to-be-tested eye diagram comprises: an eye detection area and an eye non-detection area; as shown in Figure 7 and Figure 8 , the eye detection area is the black part in the figure, and the eye non-detection area is the white part in the figure; the eye detection area is the eye diagram part for detecting the eye height data and the eye width data, and the eye non-detection area is the part unnecessary for the eye diagram part for detecting the eye height data and the eye width data.

[0105] The eye diagram calculation module 2 further comprises: a judgment unit 23 configured to obtain the image scanning area of the phase interpolator 21 or the digital-to-analog converter 22; if the image scanning area is the eye detection area, a first control signal is generated; if the image scanning area is the eye non-detection area, a second control signal is generated; a control unit 24 configured to control the phase interpolator 21 or the digital-to-analog converter 22 to scan the to-be-tested eye diagram at a first preset step according to the first control signal; control the phase interpolator 21 or the digital-to-analog converter 22 to scan the to-be-tested eye diagram at a second preset step according to the second control signal; the second preset step is greater than the first preset step. As shown in Figure 7 and Figure 8 , which are schematic diagrams of the first preset step and the second preset step.

[0106] It can be understood that when obtaining the eye diagram data, the eye detection area needs to be carefully detected and finely scanned, and the eye non-detection area does not need to be finely scanned like the eye detection area, but needs to complete the scanning process as soon as possible to improve the scanning efficiency of the eye image; therefore, the to-be-tested eye diagram is scanned at the first preset step for the eye detection area, and the to-be-tested eye diagram is scanned at the second preset step for the eye non-detection area, and the second preset step is much greater than the first preset step.

[0107] For example, the eye diagram calculation module 2 with more information and higher accuracy, namely the EOM (eye-opening monitor), is slow and has a large hardware overhead, which hinders the rapid convergence of the adaptive equalizer or clock recovery. In order to break the trade-off between eye diagram accuracy and measurement time, the eye diagram calculation module 2 provided in the present application uses a non-uniform scanning algorithm to increase the scanning speed by adopting a larger step size in the non-detection area of ​​the eye. First, a PI (phase interpolator) is used to scan the eye width. When scanning the transition area (i.e., the first control signal PDF = 1) (PDF, probability density function), the scanning step size is minimized to 1 to maintain accuracy. In the data center area where no signal conversion occurs (i.e., the second control signal PDF = 0), a larger step size is used to speed up the scanning process. After determining the eye width, a DAC (Digital-to-Analog Converter) is used at the horizontal center of the eye to scan in the eyelid area (i.e., PDF = 1) with a step size of 1, while a larger step size is applied in the center of the eye diagram (i.e., PDF = 0) to quickly obtain the eye height. The eye diagram calculation module 2 controls the scanning step of the DAC and PI and calculates the eye width data and eye height data.

[0108] like Figure 3 The figure shows the adaptive logic flow chart of the adaptive module 3.

[0109] In this embodiment, the adaptive module 3 is configured with a capacitance adjustment unit, and the capacitance adjustment unit is configured to perform a capacitance adjustment operation; the capacitance adjustment operation is configured as follows: reducing the capacitance value C_CODE of the adjustable capacitor according to a preset value to obtain a capacitance adjustment value C_CODE-1; obtaining the eye height data EH and the eye width data EW under the capacitance adjustment value; calculating the total real-time value EWH_TEMP=EH+EW of the eye height data and the eye width data; judging whether the total real-time value is greater than the total reference value EWH, if not, obtaining the target capacitance value based on the capacitance adjustment value; if so, repeating the capacitance adjustment operation until the target capacitance value is obtained.

[0110] In this embodiment, the adaptive module 3 is configured with a resistance adjusting unit, which is configured to perform a resistance adjusting operation: the resistance adjusting operation is configured to increase the resistance value R_CODE of the adjustable resistance according to a preset value to obtain a resistance adjusting value R_CODE+1; obtain the eye height data EH and the eye width data EW under the resistance adjusting value; calculate the sum real-time value EWH_TEMP = EH + EW of the eye height data and the eye width data; judge whether the sum real-time value is greater than a sum reference value EWH, if not, obtain a target resistance value based on the resistance adjusting value; if yes, repeatedly perform the resistance adjusting operation until the target resistance value is obtained; the adaptive module 3 is further configured to obtain an equalization coefficient based on the target capacitance value and the target resistance value. The equalization coefficient is the target capacitance value and the target resistance value, and by adjusting the resistance value and the capacitance value of the adjustable resistance and the adjustable capacitance in the signal adjusting module 1 to the target resistance value and the target capacitance value, the equalization processing of the data signal can be realized.

[0111] In this embodiment, the sum reference value is determined by the following steps: obtaining the eye height data and the eye width data under a set environment; the set environment is configured that the adjustable resistance is the minimum value and the adjustable capacitance is the maximum value; calculating the sum reference value EWH = EH + EW of the eye height data and the eye width data. Wherein, the eye height data and the eye width data are the eye height data and the eye width data collected by the eye diagram calculation module 2 when the adjustable resistance is the minimum value and the adjustable capacitance is the maximum value. The adaptive module 3 uses an adder to obtain the sum of the eye height and the eye width, and stores it in a register. The maximum value is obtained by comparing the eye opening degree of the adaptive continuous-time linear equalizer under different configurations, so as to determine the best equalization coefficient. In order to reduce the time of determining the equalization coefficient, under high loss, the equalization coefficient starts to adjust from the configuration with high high-frequency gain, that is, the adaptive module 3 adjusts from the configuration with the minimum adjustable resistance and the maximum adjustable capacitance.

[0112] For example, in use, the signal adjusting module 1 accesses the differential input signal through the differential input end, and the adaptive module 3 can complete the configuration of the corresponding equalization coefficient, so as to obtain the best high-frequency gain of the transmission signal, so that the frequency response curve of the transmission signal tends to be flat within the Nyquist frequency, so as to serve as the input of DFE or DEMUX.

[0113] As shown in Figure 4 , it is the circuit diagram of the signal adjusting module 1 in the present application.

[0114] In this embodiment, the signal conditioning module 1 is configured with a TAS circuit; the adjustable resistance and the adjustable capacitance are configured in the TAS circuit. The TAS circuit is configured with a high-pass circuit and a low-pass circuit; the low-pass circuit is an RC low-pass filter. The signal conditioning module 1 is also configured with a TIS circuit, which is electrically connected to the TAS circuit; the TIS circuit is configured with a first inverter and a second inverter, which are respectively connected to the TAS circuit.

[0115] Compared with the current signal conditioning module 1 circuit structure, the signal conditioning module 1 in this application uses a TAS-TIS structure, the output impedance is lower, and the structure can expand the bandwidth for higher rate data passing. At the same time, due to the use of two-way structure in TAS, the input signal can be more finely balanced at low and high frequencies, and the adjustment range is large. And the power consumption of the same bandwidth in this application is lower than that of the current signal conditioning module 1 circuit structure, the adjustment variable is less, the convergence speed is fast, and it is convenient for adaptive adjustment. In addition, the additional load of the eye diagram calculation module 2 to the signal conditioning module 1, that is, a comparator, will not cause serious bandwidth influence to the signal conditioning module 1 of the TAS-TIS structure.

[0116] This application needs to use high and low frequency adjustable, and can realize high bandwidth adaptive continuous time linear equalizer under the additional load of the eye diagram calculation module 2, therefore, the signal conditioning module 1 with high and low frequency adjustable TAS-TIS structure is adopted, which is composed of TAS circuit and TIS circuit, as shown in Figure 4 In the TAS circuit, the idea of subtracting the high-pass branch from the low-pass branch to improve the high-frequency gain is adopted, and a double-path structure is used. In addition to the current single-zero, double-pole structure for high-frequency equalization, an RC low-pass filter is additionally added to the main path to produce a new pair of zero-pole to provide low-frequency equalization, and the equalization capability of the two paths can be configured. Finally, the two signals are superimposed in the form of current as the input signal of the next stage TIS circuit. The size of resistance and capacitance can be adjusted by connecting multiple transistors in parallel and controlling the gate level. The TIS circuit adopts a transimpedance amplifier structure based on inverters, which is different from the current amplifier structure. In this application, the two inverters provided by the TIS circuit are separately powered, which improves the overall gain.

[0117] Exemplarily, in order to solve the problems of large area, PVT sensitivity or long equalization process, slow algorithm convergence and the like in the existing adaptive continuous-time linear equalizer, the application provides an adaptive continuous-time linear equalizer, which detects the eye opening degree through an on-chip eye detector, and accurately and quickly evaluates the signal quality. The signal conditioning module circuit provided by the application realizes an adaptive continuous-time linear equalizer with adjustable high and low frequencies and high bandwidth, uses a TAS-TIS topology, has low output impedance, and expands the bandwidth. Meanwhile, in the TAS part, the middle and low frequency gain is adjustable, and the adjustment range is large. The overall circuit has low power consumption, few adjustment variables, fast convergence speed, and is convenient for adaptive adjustment.

[0118] Figure 5 and Figure 6 respectively, are the frequency responses of the adaptive continuous-time linear equalizer under the changed configuration. The frequency response is used to describe the difference in the processing capability of an instrument for signals of different frequencies. The frequency response refers to the curve of the amplitude gain with the frequency. When the capacitance value or the resistance value of the adjustable capacitor or the adjustable resistor is changed, the signal variation amplitude of the linear equalizer tends to be stable within the Nyquist frequency, that is, the signal equalization is more stable and fast when the adaptive continuous-time linear equalizer provided by the application is used.

[0119] Exemplarily, under the load, the adaptive continuous-time linear equalizer can provide an 8dB high-frequency gain adjustment range for 24Gb / s data by adjusting the resistance, and can adjust the low-frequency gain in the range of 100M-5GHz by adjusting the capacitance.

[0120] The following table shows the EW / EH detection time comparison:

[0121]

[0122] Among them, when the eye detector applied to the adaptive continuous-time linear equalizer provided by the application adopts a 28nm CMOS process, the detection time for eye width data and eye height data is 2.90us and 3.28us respectively; when the eye detector applied to the adaptive continuous-time linear equalizer based on asynchronous sampling histogram adopts a 130nm CMOS process, the detection time for eye height data is 1150us; and when the eye detector applied to the adaptive continuous-time linear equalizer based on random sigma tracking eye, the detection time for eye profile data is 4793us. The adaptive continuous-time linear equalizer provided by the application uses a non-uniform scanning eye detector to detect the eye opening degree, improves the speed of optimizing the equalization coefficient, and breaks the trade-off between the adaptation time and the accuracy.

[0123] The following table shows the adaptive continuous-time linear equalizer bandwidth and power consumption comparison under the 28nm CMOS process:

[0124]

[0125] Among them, the adaptive continuous time linear equalizer provided by the application has a bandwidth of 12GHz and a power consumption of 4.681mW; the equalizer without TIS circuit structure has a bandwidth of 8GHz and a power consumption of 3.240mW; the programmable two-way equalizer has a bandwidth of 8GHz and a power consumption of 6.480mW; the equalizer with TAS-TIS structure has a bandwidth of 12GHz and a power consumption of 8.676mW; the application provides a signal adjustment module 1 circuit structure that can adjust the high bandwidth of the application, and the power consumption is lower than that of the adaptive continuous time linear equalizer with the high bandwidth circuit structure.

[0126] The second aspect of the application provides a control method of an adaptive continuous time linear equalizer, which is applied to the adaptive continuous time linear equalizer in any of the above embodiments, and includes: receiving a data signal; performing high-frequency gain processing on the data signal according to a gain coefficient; the gain coefficient is the amplification ratio of the data signal; obtaining eye height data and eye width data according to the data signal; obtaining an equalization coefficient according to the eye height data and the eye width data; the equalization coefficient is the resistance adjustment value of a tunable resistor and the capacitance adjustment value of a tunable capacitor; adjusting the gain coefficient to the equalization coefficient, and controlling a signal adjustment module to operate according to the equalization coefficient; the signal adjustment module is configured with the tunable resistor and the tunable capacitor; wherein, when the signal adjustment module operates according to the equalization coefficient, the data signal achieves a target equalization effect. The effect of the above method embodiment can refer to the effect of the adaptive continuous time linear equalizer embodiment, which is not repeated here.

[0127] The application provides an adaptive continuous-time linear equalizer, which is generally applied to a receiver and has the ability to eliminate ISI (inter symbol interference) of a transmission signal and improve a transmission data rate. The main circuit comprises a signal adjusting module 1, an eye diagram calculating module 2 and an adaptive module 3. The eye height and the eye width of the output signal of the signal adjusting module 1 are detected by the eye diagram calculating module 2, and then the state of the corresponding switch in the signal adjusting module 1 is switched by the adaptive module 3 to change the resistance of the adjustable resistor and the capacitance value of the adjustable capacitor in the signal adjusting module circuit, so as to change the high-frequency gain of the signal adjusting module 1 circuit, thereby realizing the equalization configuration of different channels. The signal adjusting module 1 adopts a high-low-frequency adjustable low-power TAS-TIS (trans-admittance trans-impedance) structure, the TAS circuit adopts two branches of an HF (high pass) circuit and an LF (low pass) circuit, has the ability to adjust the low-frequency and high-frequency gains of the transmission signal, and the TIS part is based on an inverter, reduces the influence of the load capacitance on the signal bandwidth and thereby expands the bandwidth. The eye diagram calculating module 2 adopts non-uniform sampling and quantization, so as to shorten the time for detecting the eye height and the eye width and be conducive to obtaining the adaptive equalization coefficients of the signal adjusting module 1 faster. The adaptive continuous-time linear equalizer provided by the application can reduce the influence of the load of the rear-stage circuit of the continuous-time linear equalizer on the bandwidth and also realize the equalization of high-speed signals.

[0128] The above detailed description is further used to explain the purposes, technical solutions and beneficial effects of the embodiments of the application. It should be understood that the above is only a specific implementation of the embodiments of the application and is not used to limit the protection scope of the embodiments of the application. Any modification, equivalent replacement, improvement and the like made on the basis of the technical solutions of the embodiments of the application should be included in the protection scope of the embodiments of the application.

Claims

1. An adaptive continuous-time linear equalizer characterized by, The method comprises the following steps: A signal conditioning module (1) is configured with an adjustable resistor and an adjustable capacitor; the signal conditioning module (1) is configured to: Receive a data signal; According to a gain coefficient, the data signal is subjected to high-frequency gain processing; the gain coefficient is the amplification ratio of the signal conditioning module (1) to the data signal; An eye diagram calculation module (2) is configured to: According to the data signal, eye height data and eye width data are obtained; An adaptive module (3) is configured to: According to the eye height data and the eye width data, an equalization coefficient is obtained; the equalization coefficient is the resistance adjustment value of the adjustable resistor and the capacitance adjustment value of the adjustable capacitor; The gain coefficient is adjusted to the equalization coefficient to control the signal conditioning module (1) to operate according to the equalization coefficient; The adaptive module (3) is configured with a capacitance adjustment unit, and the capacitance adjustment unit is configured to perform a capacitance adjustment operation; the capacitance adjustment operation is configured to: The capacitance value of the adjustable capacitor is reduced according to a preset value to obtain a capacitance adjustment value; The eye height data and the eye width data under the capacitance adjustment value are obtained; The real-time value of the sum of the eye height data and the eye width data is calculated; It is judged whether the real-time value of the sum is greater than a sum reference value, if not, a target capacitance value is obtained based on the capacitance adjustment value; If yes, the capacitance adjustment operation is repeatedly executed until the target capacitance value is obtained; The adaptive module (3) is configured with a resistance adjustment unit, and the resistance adjustment unit is configured to perform a resistance adjustment operation; the resistance adjustment operation is configured to: The resistance value of the adjustable resistor is increased according to a preset value to obtain a resistance adjustment value; The eye height data and the eye width data under the resistance adjustment value are obtained; The real-time value of the sum of the eye height data and the eye width data is calculated; It is judged whether the real-time value of the sum is greater than a sum reference value, if not, a target resistance value is obtained based on the resistance adjustment value; If yes, the resistance adjustment operation is repeatedly executed until the target resistance value is obtained; The adaptive module (3) is further configured to: Based on the target capacitance value and the target resistance value, an equalization coefficient is obtained; The sum reference value is determined by the following steps: Obtain the eye height data and the eye width data under a set environment; the set environment is configured such that the adjustable resistor is at a minimum value and the adjustable capacitor is at a maximum value; The sum reference value of the eye height data and the eye width data is calculated; When the signal conditioning module (1) operates according to the equalization coefficient, the data signal achieves a target equalization effect.

2. An adaptive continuous-time linear equalizer according to claim 1, wherein, The eye diagram calculation module (2) comprises: A phase interpolator (21) is configured to: According to the data signal, eye width data is obtained; A digital-to-analog converter (22) is configured to: According to the data signal, eye height data is obtained.

3. An adaptive continuous-time linear equalizer according to claim 2, wherein, The eye diagram to be tested includes an eye detection area and an eye non-detection area; The eye diagram calculation module (2) further comprises: A judgment unit (23) is configured to: acquire an image scanning area of the phase interpolator (21) or the digital-to-analog converter (22); if the image scanning area is an eye detection area, generate a first control signal; if the image scanning area is an eye non-detection area, generate a second control signal; a control unit (24) configured to: according to the first control signal, control the phase interpolator (21) or the digital-to-analog converter (22) to scan the to-be-tested eye diagram with a first preset step size; according to the second control signal, control the phase interpolator (21) or the digital-to-analog converter (22) to scan the to-be-tested eye diagram with a second preset step size; the second preset step size is greater than the first preset step size.

4. The adaptive continuous-time linear equalizer of claim 1, wherein, The signal conditioning module (1) is configured with a TAS circuit; The adjustable resistor and the adjustable capacitor are configured in the TAS circuit.

5. An adaptive continuous-time linear equalizer as recited in claim 4, wherein, The TAS circuit is configured with a high-pass circuit and a low-pass circuit; The low-pass circuit is an RC low-pass filter.

6. An adaptive continuous-time linear equalizer according to claim 4, wherein, The signal conditioning module (1) is also configured with a TIS circuit, which is electrically connected to the TAS circuit; The TIS circuit is configured with a first inverter and a second inverter, which are respectively connected to the TAS circuit.

7. A control method of an adaptive continuous-time linear equalizer, applied to the adaptive continuous-time linear equalizer of any one of claims 1 to 6, characterized in that, It includes: receiving a data signal; According to the gain coefficient, the data signal is processed by high frequency gain; The gain coefficient is the amplification ratio of the data signal; According to the data signal, eye height data and eye width data are obtained; According to the eye height data and the eye width data, an equalization coefficient is obtained; The equalization coefficient is the resistance adjustment value of the adjustable resistor and the capacitance adjustment value of the adjustable capacitor; Adjust the gain coefficient to the equalization coefficient, and control the signal conditioning module to operate according to the equalization coefficient; the signal conditioning module is configured with the adjustable resistor and the adjustable capacitor; When the signal conditioning module operates according to the equalization coefficient, the data signal achieves the target equalization effect.

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