Power amplifier with bias scheme for implementing

Abstract

The invention relates to a power amplifier utilizing a bias scheme that enables high-power operation. The disclosed structure includes a power amplifier and circuitry for implementing a bias scheme to enable high power operation. A power amplifier includes a chain of parallel transistors connected to input and output transformers. Each chain includes first, second, and third n-type field effect transistors (NFETs) connected in series with a front gate and a back gate. An output transformer receives a variable positive supply voltage generated using average power tracking. The front gate and the back gate of each third NFET receive a positive bias voltage and a negative bias voltage greater than or equal to the variable positive supply voltage, respectively. By negative back-biasing the third NFET, its threshold voltage rises, so a high positive bias voltage can be applied to the front gate to improve power output without violating the reliability specification. Optionally, the voltage at the source region of the third NFET remains constant by correlating the negative bias voltage with temperature.

Description

Technical Field

[0001] The present disclosure relates to power amplifiers and, more particularly, to embodiments including circuit configurations for power amplifiers utilizing biasing schemes that enable high power operation. Background Art

[0002] A radio frequency integrated circuit (RFIC) is an integrated circuit (IC) that includes RF devices and / or circuits configured to operate at frequencies within the radio spectrum, and optionally includes other non-RF devices. The radio spectrum includes RF signals with frequencies ranging from 3Hz to 300GHz. RFIC applications include, but are not limited to, wireless communication applications (e.g., mobile phones, Wi-Fi devices, Bluetooth devices, satellite transceivers, etc.), radar system applications, military applications, imaging applications, etc. RFIC applications under development are designed to operate at faster speeds and in new frequency bands including, but not limited to, 7-24GHz. RFICs operating in new frequency bands will require power amplifiers with relatively high saturation power (Psat). For example, currently available RFICs operating in the 28GHz band require power amplifiers that exhibit a Psat of about 22dBm, while RFICs operating in the 13GHz band require power amplifiers that exhibit a higher Psat of about 28dBm. However, currently available power amplifiers are generally unable to reliably achieve such operating parameters. Summary of the invention

[0003] An embodiment of a circuit structure including a power amplifier is disclosed herein. The power amplifier may include an output transformer connected to receive a positive supply voltage and having an input terminal. The power amplifier may also include parallel transistor chains, which are respectively connected to the input terminals of the output transformer. Each transistor chain may include an N-type field effect transistor (NFET), the N-type field effect transistor having a front gate connected to receive a positive bias voltage and a back gate connected to receive a negative bias voltage.

[0004] Some embodiments of the circuit structure disclosed herein may include a power amplifier and a plurality of voltage generators. The voltage generator may output a positive supply voltage, a negative bias voltage, a first positive bias voltage, and a second positive bias voltage. The positive supply voltage may be higher (i.e., at a higher positive voltage level) than the first positive bias voltage and lower (i.e., at a lower positive voltage level) than the second positive bias voltage. The power amplifier may include an input transformer having an output terminal. The power amplifier may also include an output transformer connected to receive the positive supply voltage and having an input terminal. The power amplifier may also include a parallel transistor chain connected between the input transformer and the output transformer. Each transistor chain may include a first N-type field effect transistor NFET, a second NFET, and a third NFET connected in series between a ground and an input terminal of the output transformer. In addition, the first NFET in each transistor chain may have a first back gate connected to the ground and a first front gate connected to the output terminal of the input transformer. The second NFET in each transistor chain has a second back gate connected to the ground and a second front gate connected to receive the first positive bias voltage. The third NFET in each transistor chain has a third back gate connected to receive the negative bias voltage and a third front gate connected to receive the second positive bias voltage.

[0005] Other embodiments of the circuit structure disclosed herein may include a power amplifier and a plurality of voltage generators. The voltage generator may output a positive supply voltage, a negative bias voltage, a first positive bias voltage, and a second positive bias voltage. The positive supply voltage may be higher than the first positive bias voltage and lower than the second positive bias voltage. The power amplifier may include an input transformer having an output terminal; and an output transformer connected to receive the positive supply voltage and having an input terminal. The power amplifier may also include a parallel transistor chain connected between the input transformer and the output transformer. Each transistor chain may include a first N-type field effect transistor NFET, a second NFET, and a third NFET connected in series between the ground and the input terminal of the output transformer. In addition, the first NFET and the second NFET in each transistor chain may have a threshold voltage lower than that of the third NFET. In addition, the first NFET has a first back gate connected to the ground and a first front gate connected to the output terminal of the input transformer. The second NFET has a second back gate connected to the ground and a second front gate connected to receive the first positive bias voltage. The third NFET has a third back gate connected to receive the negative bias voltage and a third front gate connected to receive the second positive bias voltage.

[0006] It should be noted that all aspects, examples and features of the disclosed embodiments mentioned in the above summary of the invention can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary of the invention, can be combined to form an embodiment not specifically described herein. The details of one or more embodiments are set forth in the drawings and the following description. Other features, objects and advantages will be apparent from the specification and drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be better understood by reference to the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0008] Figure 1A is a schematic diagram of a disclosed embodiment showing a circuit structure;

[0009] Figure 1B is shown in more detail Figure 1A a schematic diagram of a circuit within the circuit structure;

[0010] Figure 2 is a cross-sectional view showing a parallel transistor chain of a power amplifier implemented as a fully depleted semiconductor-on-insulator structure;

[0011] Figure 3A It is shown Figure 1A A table of example voltage conditions that may be employed at room temperature and in normal operating mode in a circuit configuration of

[0012] Figure 3B It is shown Figure 1A The circuit structure is Figure 3A A graph of example power gain versus power output curves exhibited under voltage conditions;

[0013] Figure 3C It is shown Figure 1A The circuit structure is Figure 3A A graph of an example power added efficiency versus power output curve for voltage conditions of

[0014] Figure 3D is a graph showing example curves showing the variation of drain-source voltage (Vds) at a 1 dB compression point (P1dB) over time and the variation of drain-gate voltage (Vdg) at P1dB over time;

[0015] Figure 4A It is shown Figure 1A A table of example voltage conditions that may be employed at room temperature and in power control mode in a circuit configuration of

[0016] Figure 4B It is shown Figure 1A The circuit structure is Figure 4A A graph of example power gain versus power output curves shown under voltage conditions. DETAILED DESCRIPTION

[0017] As described above, RFIC applications being developed are designed to operate at faster speeds and in new frequency bands including, but not limited to, the 7-24 GHz range. RFICs operating in new frequency bands will require power amplifiers with relatively high saturation powers (Psat). For example, currently available RFICs operating in the 28 GHz band require power amplifiers that exhibit a Psat of about 22 dBm, while RFICs operating in the 13 GHz band require power amplifiers that exhibit a higher Psat of about 28 dBm. However, currently available power amplifiers are generally unable to reliably achieve such operating parameters.

[0018] In view of the foregoing, embodiments of circuit structures including a power amplifier and additional circuits (e.g., a plurality of different voltage generators) for implementing a biasing scheme that enables high power operation (e.g., RFIC operation in the 13 GHz band using a power amplifier exhibiting a Psat of about 28 dBm) are disclosed herein. The power amplifier may include two parallel symmetrical transistor chains, with opposite ends of the chains connected to an input transformer and an output transformer. Each transistor chain may include a first, second, and third n-type field effect transistors (NFETs) connected in series. For example, the circuit structure may be implemented in a fully depleted semiconductor-on-insulator (e.g., fully depleted silicon-on-insulator (FDSOI)) technology processing platform such that each NFET within the chain has both a front gate and a back gate, as discussed in more detail below, and specific bias conditions applied to its front gate and back gate facilitate the desired high power operation. Specifically, the output transformer may receive a variable positive supply voltage that is generated, for example, using average power tracking (i.e., based on the average power output of the power amplifier). The drain region of the third NFET can be connected to different input terminals of the output transformer respectively, and its source region can be connected to the second NFET. The front gate of the third NFET can be connected to receive the same positive bias voltage. The back gate of the third NFET can be connected to receive a negative bias voltage, which is optionally temperature-dependent. By negatively reverse biasing the third NFET, its threshold voltage is increased. Therefore, a relatively high positive bias voltage can be applied to the front gate to increase the power output of the power amplifier without violating the reliability specification of the third NFET. For example, the positive bias voltage applied to the front gate of the third NFET can be at a voltage level that is the same as or higher than the voltage level of the variable positive supply voltage coupled to the output transformer. In addition, by making the negative bias voltage temperature-dependent, the voltage of the source region of the third NFET, which can vary with temperature, can be kept constant. The gate biasing of the first and second NFETs in each chain is discussed in more detail below. Optionally, such a circuit structure can operate in a power control mode (also referred to herein as a battery save mode), during which various bias voltages (including but not limited to a variable positive supply voltage, a variable positive bias voltage, and a negative bias voltage) can be scaled (e.g., on demand or automatically when the average output power of the power amplifier drops below a certain threshold level).

[0019] More specifically, Figure 1A1 is a schematic diagram illustrating an embodiment of a circuit structure 100, which includes a power amplifier 10 and additional circuitry 20 (e.g., a plurality of different voltage generators, discussed in more detail below) for generating various voltages that can be used to implement a biasing scheme that enables high power operation. That is, given the biasing scheme, the power amplifier 10 can exhibit a relatively high Psat (e.g., a Psat of about 28 dBm) and, therefore, can be incorporated into a next generation RFIC operating in a frequency band in the 7-24 GHz range (e.g., a 13 GHz band). Figure 1B is a schematic diagram showing the additional circuit 20 in more detail.

[0020] refer to Figure 1A , the power amplifier 10 may include an input stage (S1), a driver stage (S2), a power stage (S3) and an output stage (S4).

[0021] The input stage (S1) may include, for example, a radio frequency (RF) input transformer 102 (also referred to herein as an input transformer) to match the input impedance of the input stage (S1) to the input impedance of the previous stage. The input transformer 102 may include two magnetically coupled input windings 103 and 104. The input winding 103 may have input terminals at opposite ends. In some embodiments, as shown, one input terminal of the input winding 103 may be electrically connected to an input node 101 for receiving an RF input signal, and the other input terminal may be electrically connected to ground 199, so that the input transformer 102 is a balun (i.e., a balanced to unbalanced signal conversion transformer). In other embodiments not shown, the input terminals of the input winding 103 may be electrically connected to a positive input node and a negative input node for receiving a differential RF input signal, respectively. The input winding 104 may have output terminals 105a, 105b at opposite ends. The output terminals 105a, 105b may be electrically connected to transistor chains 170a, 170b, as discussed in more detail below. The input winding 104 may also have a center tap electrically connected to receive a bias voltage (VGB). Alternatively, the input stage (S1) may have any other suitable configuration.

[0022] The output stage (S4) may include a voltage output transformer 192 (also referred to herein as an output transformer). The output transformer 192 may include two magnetically coupled output windings 193 and 194. The output winding 193 may have output terminals at opposite ends. In some embodiments, as shown, one output terminal of the output winding 193 may be electrically connected to an output node 191 for outputting a voltage output signal (Vout), and the other output terminal may be electrically connected to ground 199. In other embodiments not shown, the output terminal of the output winding 193 may be electrically connected to positive and negative output nodes for outputting a differential voltage output signal. The output winding 194 may have input terminals 195a, 195b at opposite ends. One input terminal 195a may be electrically connected to the transistor chain 170a, and the other input terminal 195b may be electrically connected to the transistor chain 170b. In addition, the output winding 194 may have a center tap electrically connected to receive a positive power supply voltage. As discussed in more detail below, the positive supply voltage may alternatively be a variable positive supply voltage (eg, an average power tracking positive supply voltage VDD_APT). Alternatively, the output stage (S4) may have any other suitable configuration.

[0023] The power amplifier 10 may also include two symmetrical parallel transistor chains 170a and 170b (also referred to herein as transistor chains). Each transistor chain 170a, 170b may include first, second, and third n-type field effect transistors (NFETs) connected in series, one end of which is connected to the input transformer 102 and the opposite end is connected to the output transformer 192.

[0024] The first NFETs 110a, 110b may be included in a driver stage (S2). Each of the first NFETs 110a, 110b may have a first source region electrically connected to ground (VSS), a first drain region electrically connected to a second source region of a second NFET 120a, 120b, and a first front gate 111a, 111b electrically connected to an output terminal 105a, 105b of an input winding 104 of an input transformer 102.

[0025] The second NFET 120a, 120b and the third NFET 130a, 130b may be located within the power stage (S3). Each second NFET 120a, 120b may have a second source region electrically connected to the first drain region of the first NFET 110a, 110b, a second drain region electrically connected to the third source region of the third NFET 130a, 130b, and a second front gate 121a, 121b electrically connected to receive a first positive bias voltage (VG1) (also referred to as a first DC gate voltage). Each third NFET 130a, 130b may have a third source region electrically connected to the second drain region of the second NFET 120a, 120b, a third drain region electrically connected to the input terminal 195a, 195b of the output winding 194 of the output transformer 192, and a third front gate 131a, 131b electrically connected to receive a second positive bias voltage (VG2) different from VG1 (also referred to herein as a second DC gate voltage). In addition, within the power stage (S3), the power amplifier 10 may also include capacitors 125a, 125b for the second NFET 120a, 120b and / or capacitors 135a, 135b for the third NFET 130a, 130b. More specifically, as Figure 1A As shown, each capacitor 125a, 125b can be electrically connected between the second front gate 121a, 121b of the second NFET 120a, 120b and ground (VSS). Similarly, each capacitor 135a, 135b can be electrically connected between the third front gate 131a, 131b of the third NFET 130a, 130b and ground (VSS). Such capacitors can be used to tune the gate capacitance of the second NFET and / or the third NFET (e.g., to achieve stability and / or improve performance).

[0026] In such a circuit structure, reliability specifications (e.g., temperature dependent dielectric breakdown (TDDB) off-state reliability specifications) limit the maximum gate-to-drain voltage (Vgd_max) of the transistors within the power amplifier 10. For example, in some embodiments, the Vgd_maxc may be 1.8V. As a result, such reliability specifications limit the Psat that can be achieved. However, in the disclosed embodiment, the circuit structure 100 can be implemented using a fully depleted semiconductor-on-insulator technology processing platform (e.g., using a fully depleted silicon-on-insulator (FDSOI) technology processing platform) so that the first, second, and third NFETs of the transistor chains 170a, 170b all have front gates and back gates, so that they can optionally have mixed threshold voltage types, and so that a unique biasing scheme can be adopted that allows a relatively high Psat to be achieved without violating the reliability specifications.

[0027] More specifically, Figure 21 is a cross-sectional view of a parallel transistor chain 170a, 170b of a power amplifier 10 showing a circuit structure 100 in more detail, which circuit structure 100 is specifically incorporated into a fully depleted semiconductor-on-insulator (e.g., FDSOI) structure 200. Structure 200 may include a semiconductor substrate 201. Semiconductor substrate 201 may be, for example, a single crystal silicon substrate or a substrate of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.). Structure 200 may also include a semiconductor-on-insulator region (e.g., an SOI region). The semiconductor-on-insulator region may include an insulator layer 202 located on semiconductor substrate 201. Insulator layer 202 may be, for example, a relatively thin layer of a thin silicon dioxide layer or any other suitable insulator material. The semiconductor-on-insulator region may also include a thin semiconductor layer 203 located on insulator layer 202. Semiconductor layer 203 may be, for example, a single crystal silicon layer or a layer of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.).

[0028] As described above, each transistor chain 170a, 170b of the power amplifier 10 of the circuit structure 100 may include a first NFET 110a, 110b, a second NFET 120a, 120b, and a third NFET 130a, 130b connected in series. Figure 2As shown, each NFET 110a, 110b, 120a, 120b, 130a, 130b can include an active device region in a corresponding portion of the semiconductor layer 203. The boundary of the corresponding portion of the semiconductor layer 203 (and thus the boundary of the active device region) can be defined by an isolation region 205. The isolation region 205 can be, for example, a shallow trench isolation (STI) region. That is, the trench can extend from the top surface of the semiconductor layer 203 to and optionally through the insulator layer 202, can laterally surround the active device region of the transistor, and can be filled with one or more layers of isolation material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, etc.). Each NFET 110a, 110b, 120a, 120b, 130a, 130b can also include a channel region (c) between the source region and the drain region (s / d) within its active device region. The source / drain regions may have a relatively high conductivity level of N-type conductivity (e.g., may be N+ source / drain regions), and the channel region may be intrinsic (i.e., undoped) or may have a relatively low conductivity level of P-type conductivity (e.g., may be a P-channel region). Each NFET 110a, 110b, 120a, 120b, 130a, 130b may also include a corresponding front gate 111a, 111b, 121a, 121b, 131a, 131b (also referred to herein as a main gate or control gate) adjacent to (e.g., located above and immediately adjacent to) an active device region at the channel region. The front gate 111a, 111b, 121a, 121b, 131a, 131b may include a relatively thin gate dielectric layer (including one or more layers of gate dielectric material) adjacent to the channel region and a gate conductor layer (including one or more layers of gate conductor material) located on the gate dielectric layer. The front gate may be any of a gate-first polysilicon gate structure, a gate-first high-K metal gate (HKMG) structure, a gate-last HKMG structure (also referred to as a replacement metal gate (RMG) structure), or any other suitable type of front gate structure.

[0029] One advantage of a fully depleted semiconductor-on-insulator (e.g., FDSOI) structure is that FETs can be formed on an insulator layer above wells of different conductivity types to achieve different threshold voltages (VT). For the purposes of this disclosure, a well (also referred to herein as a well region) refers to a region of semiconductor material that is doped (e.g., via a dopant implantation process or any other suitable doping process) to have a particular type of conductivity (e.g., N-type conductivity or P-type conductivity). A well doped with N-type conductivity is referred to herein as an N-well, and a well doped with P-type conductivity is referred to herein as a P-well (see the different dopants discussed below for achieving different N-type and P-type conductivities). For ultra-low threshold voltage (SLVT) or low threshold voltage (LVT) FETs, an NFET can be formed above an N-well, and a PFET can be formed above a P-well. For conventional threshold voltage (RVT) or high threshold voltage (HVT) FETs, an NFET can be formed above a P-well, and a PFET can be formed above an N-well. Those skilled in the art will recognize that whether the FETs are SLVT or LVT FETs, or whether they are RVT or HVT FETs, will depend on the design (eg, device size, etc.) and process specifications (eg, dopant concentration, etc.).

[0030] In some embodiments, the first NFET 110a, 110b of the driver stage S2 of the power amplifier 10 and the second NFET 120a, 120b of the power stage (S3) of the power amplifier 10 may be LVT or SLVT NFETs. In other embodiments, the first NFET 110a, 110b of the driver stage S2 of the power amplifier 10 and the second NFET 120a, 120b of the power stage (S3) of the power amplifier 10 may be RVT NFETs. In some embodiments, the third NFET 130a, 130b of the power stage (S3) of the power amplifier 10 may be RVT or HVT NFETs. Optionally, the third NFET 130a, 130b of the power stage (S3) of the power amplifier 10 may have a relatively thick gate oxide layer compared to the other NFETs.

[0031] For example, semiconductor substrate 201 may be a single crystal semiconductor substrate (e.g., a single crystal silicon substrate). Semiconductor substrate 201 may be further doped to have a relatively low conductivity level of P-type conductivity (e.g., to become a P-type substrate). P-well 252 may be located in the upper portion of semiconductor substrate 201 and adjacent to insulator layer 202. N-well 251 may also be located in the upper portion of semiconductor substrate 201 and adjacent to insulator layer 202, and further positioned laterally adjacent to P-well 252. For example, N-well 251 may laterally surround P-well 252. Additional N-well 210 (also referred to herein as a buried N-well) may be located in semiconductor substrate 201 and below P-well 252, and further extend laterally below N-well 251. For example, the additional N-well 210 may be separated from the bottom surface of semiconductor substrate 201 by a certain distance, and thus, electrical isolation may be provided between P-well 252 and the lower portion of semiconductor substrate 201 (which is a P-substrate as described above). In an embodiment where the first NFET 110 a, 110 b and the second NFET 120 a, 120 b are LVT or SLVT NFETs, and the third NFET 130 a, 130 b are RVT or HVT NFETs, the first NFET 110, 110 b and the second NFET 120, 120 b may be located on the insulator layer 202 above the N-well 251, and the third NFET 130 a, 130 b may be located on the insulating layer 202 above the P-well 252.

[0032] Another advantage of a fully depleted semiconductor-on-insulator (e.g., FDSOI) structure is that back bias (also referred to herein as back gate bias) can be used to fine-tune the threshold voltage (regardless of whether the FET is a SLVT / LVT or RVT / HVT FET). Forward back bias (FBB) refers to applying a gate bias voltage to the back gate (specifically, to the well below the FET) to reduce the VT of the FET, thereby increasing the switching speed. Typically, for PFETs, FBB is achieved by applying 0.0 volts (V) or a negative gate bias voltage (VN) to the well; while for NFETs, FBB is achieved by applying a positive gate bias voltage (VP) to the well. Reverse back bias (RBB) specifically refers to applying a gate bias voltage to the back gate (specifically, to the well below the FET) to increase the VT of the FET, thereby reducing the switching speed and reducing the leakage current. Typically, for PFETs, RBB is achieved by applying VP to the well; while for NFETs, RBB is achieved by applying VN to the well. More specifically, given the above structure 200, each NFET 110a, 110b, 120a, 120b, 130a, 130b also has a corresponding back gate (e.g., see the first back gate 112a, 112b of the first NFET 110b, 110b, the second back gate 122a, 122b of the second NFET 120a, 120b, and the third back gate 132a, 132b of the third NFET 130a, 130b). Each back gate 112a, 112b, 122a, 122b, 132a, 132b includes an adjacent portion of the insulator layer 202 located below the active device region of the NFET 110a, 110b, 120a, 120b, 130a, 130b, and the P-well 252 or N-well 251 located thereunder.

[0033] Each of the wells 251-252 may have one or more corresponding contact regions 253-254 (also referred to herein as taps) respectively adjacent thereto. That is, the structure 200 may also include a body region (also referred to as a hybrid region). The body region may not have an insulator layer 202, but may include one or more contact regions 253-254 on the semiconductor substrate 201 adjacent to each well 251-252 and electrically isolated from the active device region of the transistor (e.g., by an isolation region 205). Each contact region 253-254 may include, for example, an epitaxially grown single crystalline semiconductor layer (e.g., an epitaxially grown silicon layer or an epitaxially grown layer of any other suitable semiconductor material) located on the top surface of the semiconductor substrate 201 and adjacent to the well. Such a contact region (i.e., a tap) may be doped (e.g., in-situ doping or subsequent implantation) so as to have the same type of conductivity (e.g., N-type conductivity or P-type conductivity) as the underlying well, optionally with a higher conductivity level. For example, the contact region 254 for the P well 252 may be a P+ contact region (ie, a P tap), and the contact region 253 for the N well 251 may be an N+ contact region (eg, an N tap). Optionally, the contact region may further include a silicide layer (not shown) thereon.

[0034] Generally, a fully depleted semiconductor-on-insulator structure (e.g., an FDSOI structure) including a semiconductor-on-insulator region having a semiconductor-on-insulator NFET and / or PFET and a body region having a well tap to a P-well and / or N-well in a substrate below the FET is well known in the art and may have various configurations. Therefore, details thereof and processing techniques (e.g., conventional FDSOI processing techniques) are omitted from the specification and drawings in order to allow the reader to focus on the salient aspects of the disclosed embodiments (e.g., relating to selectable hybrid threshold voltages of FETs within the power amplifier 10, and also relating to the proposed biasing scheme for the FETs, as described below).

[0035] As described above, by forming the NFETs 110a, 110b, 120a, 120b, 130a, 130b with front gates and back gates, a unique biasing scheme may be employed that allows relatively high Psat to be achieved without violating reliability specifications.

[0036] More specifically, again referring to Figure 1A-1B , the circuit structure 100 further includes an additional circuit 20. Figure 1B As shown, the additional circuit 20 may include a plurality of different voltage generators 21-24.

[0037] One of the different voltage generators may be a positive supply voltage generator 21. The positive supply voltage generator 21 may be connected to receive the maximum available supply from the power supply 29. For example, the positive supply voltage generator 21 may be electrically connected to a battery, and the maximum available supply may be, for example, a battery supply voltage (VBAT). Alternatively, the power supply 29 may be any other suitable power supply. The positive supply voltage generator 21 may further generate and output (i.e., may be configured to generate and output) a positive supply voltage (VDD) that is less than the maximum available supply (e.g., VDD < VBAT). In some embodiments, the positive supply voltage may be variable. Specifically, in some embodiments, the positive supply voltage generator 21 may be an average power tracking (APT) voltage generator. The APT voltage generator may track (i.e., may be configured to track or monitor) the power output (Pout) of the power amplifier 10, and may increase or decrease the positive supply voltage (VDD) in order to fine-tune Pout. If Pout needs to be increased for a particular application, VDD may be increased, and vice versa. In this case, VDD may be referred to as an average power tracking VDD (VDD_APT).

[0038] Another of the different voltage generators may be a voltage generator 23. The voltage generator 23 may be electrically connected to receive a positive power supply voltage (e.g., VDD_APT). That is, it may be powered by the same VDD_APT as the power amplifier 10. Therefore, the voltage generator 23 is also referred to herein as an internal voltage generator. The voltage generator 23 may further generate and output (i.e., may be configured to generate and output) a first bias voltage (VG1) (also referred to herein as a first gate bias voltage), which is less than the positive power supply voltage (e.g., VG1 < VDD_APT < VBAT).

[0039] Another one of the different voltage generators may be a low dropout voltage regulator 22. The low dropout voltage regulator 22 may be connected to receive the same maximum available supply (e.g., VBAT) as the positive supply voltage generator 21. The low dropout voltage regulator 22 may further generate and output (i.e., may be configured to generate and output) a second bias voltage (VG2) (also referred to herein as a second gate bias voltage) that is less than the maximum available supply but greater than or equal to the positive supply voltage (e.g., VDD_APT ≤ VG2). <VBAT)。

[0040] Yet another of the different voltage generators may be a negative bias voltage generator 24. The negative bias voltage generator 24 may generate and output (i.e., may be configured to generate and output) a negative bias voltage (VBGN) at a predetermined negative voltage level. Optionally, the VBGN may be a temperature-dependent VBGN. That is, the negative bias voltage generator 24 may generate and output a VBGN that is variable and tracks the operating temperature. Specifically, in order to keep the threshold voltage (VT) of the third NFET 130a, 130b substantially constant, the VBGN will become more negative as the temperature (T) increases, and the VBGN will become less negative as T decreases. For example, at T = 110°C, VBGN = -2.5V, and at T = -40°C, VBGN = -1.5V.

[0041] Voltage generators (e.g., negative bias voltage generators, APT voltage generators, low dropout voltage generators, etc.) are well known in the art. Therefore, details thereof are omitted from the present specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments related to the specific voltages generated by these voltage generators (e.g., VBGN, VDD_APT, VG1, and VG2), their use in power amplifier 10, and their relationship to each other, as described herein.

[0042] Specifically, combined Figure 1A-1B refer to Figure 2 , the (one or more) N-type contact regions 253 (i.e., (one or more) N taps) for the N-well 251 can be electrically connected to ground (VSS). Therefore, the first back gates 112a, 112b of the first NFET 110a, 110b in the driver stage (S2) and the second back gates 122a, 122b of the second NFET 120a, 120b in the power stage (S3) are, for example, zero biased. The (one or more) P-type contact regions 254 (i.e., (one or more) P taps) for the P-well 252 can be electrically connected to the output of the negative bias voltage generator 24 to receive VBGN. Therefore, the third back gates 132a, 132b of the third NFET 130a, 130b are negatively biased (i.e., the third NFCET 130a, 130b is an RBB NFET).

[0043] In addition, as described above, the first front gates 111a, 111b of the first NFETs 110a, 110b within the driver stage (S2) can be electrically connected to the output terminals 105a, 105b of the input winding 104 of the input transformer 102 in the input stage (S1). The second front gates 121a, 121b of the second NFETs 120a, 120b within the power stage (S3) can be electrically connected to the output of the internal voltage generator 23 to receive VG1. In addition, the third front gates 131a, 131b of the third NFETs 130a, 130b can be electrically connected to the output of the low dropout voltage regulator 22 to receive VG2.

[0044] Finally, the output winding 194 of the output transformer 192 in the output stage (S4) can be electrically connected to the output of the positive supply voltage generator 21 to receive VDD_APT. As described above, the input terminals 195a, 195b of the output winding 194 are also electrically connected to the third drain region of the third NFETs 130a, 130b.

[0045] With the above-described biasing scheme, applying VBGN to the third back gates 132a, 132b of the third NFETs 130a, 130b reversely back-biases these third NFETs 130a, 130, thereby increasing their threshold voltages (VT). By increasing the VT of the third NFETs 130a, 130b, VG2 can be set at a relatively high voltage level (e.g., at or above VDD_APT) to increase the power output (Pout) of the power amplifier 10 without violating the TDDB off-state reliability specification of the third NFETs 130a, 130b (e.g., without violating the maximum gate-drain voltage (Vgd_max), e.g., 1.6-1.8V). Therefore, the power amplifier 10 can exhibit a relatively high Psat (e.g., a Psat of about 28dBm), and therefore, can be incorporated into a next-generation RFIC operating at a frequency band in the range of 7-24GHz (e.g., a 13GHz band). In addition, by making VBGN temperature-dependent, the voltage at the junction between the drain region of the second NFET 120a, 120b and the source region of the third NFET 130a, 130b in each transistor chain 170a, 170b, specifically the positive bias voltage (VCP) and the negative bias voltage (VCM), respectively, can be kept substantially constant. By keeping VCP and VCM constant, the second NFET 120a, 120b can operate reliably over the entire operating temperature range.

[0046] Figure 3A is a table showing example values ​​that may be used for VDD_APT, VG1, VG2, VBGN at room temperature, and VCP / VCM. Figure 3B It is shown Figure 3A301. As shown, in this case, the power gain constant value is about 18.5 dB, Psat is about 28.0 dBm, and the 1 dB compression point (P1dB) (i.e., the Pout level at which the power gain is reduced by 1 dB from its constant value) is about 26.5P1dB. Figure 3C It is shown Figure 3A 302 is a graph of an example power added efficiency versus power output curve under voltage conditions of . As shown, in this case, the power added efficiency (PAE) increases with power output. Specifically, at 9 dB back-off, the PAE is about 15%, at 6 dB back-off, the PAE is about 25%, and at Psat, the PAE is about 39%. Figure 3D 3 is a graph showing example curves 303 and 304 showing the variation of the drain-source voltage (Vds) at P1dB over time, and the variation of the drain-gate voltage (Vdg) at P1dB over time.

[0047] In some embodiments, the disclosed circuit structure 100 can selectively operate in a normal mode or a power control mode (also referred to herein as a battery power saving mode). During the normal mode, the power supply can be set (e.g., according to Figure 3A The power control mode may be configured to provide a power amplifier (power amplifier) ​​with a power supply voltage of 0.1 V to 0.1 V. ... Figure 4A is shown when VDD_APT is reduced from 2.6V in normal mode (e.g. Figure 3A Table of example values ​​that can be used for VG1, VG2, VBGN at room temperature, and VCP / VCM when the VG1 voltage drops to 1.8V in power control mode as shown in the figure. Figure 4B It is shown Figure 4A4. As shown in the figure, in this case, the power gain constant value is about 17dB, Psat is about 25.0dBm, and the 1dB compression point (P1dB) (i.e., the Pout level where the power gain decreases by 1dB from its constant value) is about 23P1dB. Therefore, in the power control mode, there is a trade-off between power conservation and maximum power output.

[0048] It should be understood that in the above structures and methods, semiconductor materials refer to materials whose conductive properties can be changed by doping with impurities. Such semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining III-group elements such as aluminum (Al), gallium (Ga) or indium (In) with V-group elements such as nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as non-intrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, non-intrinsic silicon is more conductive than intrinsic silicon; non-intrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. In addition, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with Group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with Group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity, and doped with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels depend on the relative concentration levels of (one or more) dopants in a given semiconductor region. In addition, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, its conductivity is higher (lower resistance) than the other semiconductor region or layer; and when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, its conductivity is lower (higher resistance) than the other semiconductor region or layer.

[0049] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having either or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0050] It should be understood that the terms used herein are used to describe the disclosed structures and methods and are not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, as used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof. In addition, as used herein, when oriented and shown in the figures, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "below", "under", "underlying", "above", "overlying", "parallel", "vertical", etc. are intended to describe relative positions (unless otherwise specified), and terms such as "touching", "direct contact", "adjacent", "directly adjacent", "immediately adjacent", etc. are intended to indicate that at least one element is in physical contact with another element (no other elements separate the elements). The term "laterally" is used herein to describe the relative position of elements and, more specifically, to indicate that one element is to the side of another element, rather than above or below the other element, when the elements are oriented and shown in the figures. For example, an element positioned laterally adjacent to another element will be to the side of the other element, an element positioned laterally next to another element will be directly to the side of the other element, and an element laterally surrounding another element will be adjacent to and bordering the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed.

[0051] The description of the various disclosed embodiments is given for the purpose of illustration, but is not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements to technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: an output transformer connected to receive a positive supply voltage and having input terminals; as well as transistor chains, which are respectively connected to the input terminals of the output transformer, Each transistor chain includes an N-type field effect transistor (NFET) having a front gate connected to receive a positive bias voltage and a back gate connected to receive a negative bias voltage.

2. The structure according to claim 1, wherein: The negative bias voltage is temperature dependent.

3. The structure according to claim 1, wherein: The positive supply voltage is related to power output.

4. The structure according to claim 1, wherein: The positive bias voltage is higher than the positive power supply voltage.

5. The structure according to claim 1, in, Each transistor chain includes at least a first NFET, a second NFET and a third NFET connected in series between ground and an input terminal of the output transformer, and The third NFET has the front gate connected to receive the positive bias voltage and the back gate connected to receive the negative bias voltage.

6. The structure according to claim 5, in, The first NFET has a first back gate connected to ground and a first front gate connected to an output terminal of an input transformer, and The second NFET has a second back gate connected to ground and a second front gate connected to receive a different positive bias voltage that is lower than the positive bias voltage and the positive power supply voltage.

7. The structure according to claim 5, wherein: The first NFET and the second NFET have a lower threshold voltage than the third NFET.

8. A structure comprising: a voltage generator that outputs a positive power supply voltage, a negative bias voltage, a first positive bias voltage, and a second positive bias voltage, wherein the positive power supply voltage is higher than the first positive bias voltage and lower than the second positive bias voltage; and An amplifier comprising: an input transformer having output terminals; an output transformer connected to receive the positive supply voltage and having an input terminal; and a transistor chain connected between the input transformer and the output transformer, wherein each transistor chain comprises a first N-type field effect transistor (NFET), a second NFET and a third NFET connected in series between ground and an input terminal of the output transformer, wherein the first NFET has a first back gate connected to ground and a first front gate connected to the output terminal of the input transformer, wherein the second NFET has a second back gate connected to ground and a second front gate connected to receive the first positive bias voltage, and The third NFET has a third back gate connected to receive the negative bias voltage and a third front gate connected to receive the second positive bias voltage.

9. The structure according to claim 8, wherein: The positive supply voltage, the negative bias voltage, the first positive bias voltage, and the second positive bias voltage are mode dependent.

10. The structure according to claim 8, wherein: The voltage generator includes a negative bias voltage generator that generates a temperature-dependent negative bias voltage and outputs it to the third back gate of the third NFET in each of the transistor chains.

11. The structure according to claim 10, wherein: The temperature dependent negative bias voltage ensures that the voltage at the junction between the second NFET and the third NFET in each transistor chain remains substantially constant over varying temperatures.

12. The structure according to claim 8, wherein: The voltage generator further includes an average power tracking voltage generator that monitors the power output of the amplifier, generates a power output related positive power supply voltage and outputs it to the output transformer.

13. The structure according to claim 8, wherein: The voltage generator also includes a voltage regulator that generates and outputs the second positive bias voltage at a voltage level higher than the positive supply voltage to avoid a gate-to-drain voltage that violates a time-dependent dielectric breakdown off-state reliability level of the third NFET.

14. The structure according to claim 8, wherein: The first NFET and the second NFET have a lower threshold voltage than the third NFET.

15. A structure comprising: a voltage generator that outputs a positive power supply voltage, a negative bias voltage, a first positive bias voltage, and a second positive bias voltage, wherein the positive power supply voltage is higher than the first positive bias voltage and lower than the second positive bias voltage; and An amplifier comprising: an input transformer having output terminals; an output transformer connected to receive the positive supply voltage and having an input terminal; and a transistor chain connected between the input transformer and the output transformer, wherein each transistor chain comprises a first N-type field effect transistor (NFET), a second NFET and a third NFET connected in series between ground and an input terminal of the output transformer, wherein the first NFET and the second NFET have a lower threshold voltage than the third NFET, wherein the first NFET has a first back gate connected to ground and a first front gate connected to the output terminal of the input transformer, wherein the second NFET has a second back gate connected to ground and a second front gate connected to receive the first positive bias voltage, and The third NFET has a third back gate connected to receive the negative bias voltage and a third front gate connected to receive the second positive bias voltage.

16. The structure of claim 15, further comprising: A semiconductor substrate comprising: A P-well and an N-well laterally surrounding the P-well; and an additional N-well located below the P-well and the N-well; and an insulator layer located on the semiconductor substrate and above the P-well and the N-well, wherein the third NFET of each transistor chain is located on the insulator layer above the P-well, and the first NFET and the second NFET of each transistor chain are located on the insulator layer above the N-well.

17. The structure of claim 15, wherein: The positive supply voltage, the negative bias voltage, the first positive bias voltage, and the second positive bias voltage are mode dependent.

18. The structure according to claim 15, in, The voltage generator includes a negative bias voltage generator that generates a temperature-dependent negative bias voltage and outputs it to the third back gate of the third NFET in each of the transistor chains, and The temperature-dependent negative bias voltage ensures that the voltage at the junction between the second NFET and the third NFET in each transistor chain remains substantially constant under varying temperatures.

19. The structure of claim 15, wherein: The voltage generator also includes an average power tracking voltage generator that monitors the power output of the amplifier and generates a power output related positive power supply voltage and outputs it to the output transformer.

20. The structure of claim 15, wherein: The voltage generator also includes a voltage regulator that generates and outputs the second positive bias voltage at a voltage level higher than the positive supply voltage to avoid a gate-to-drain voltage that violates a time-dependent dielectric breakdown off-state reliability level of the third NFET.

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