Broadband high-linearity power amplifier

Abstract

The invention discloses a broadband high-linearity power amplifier which comprises an input matching network, an intermediate-stage linearity improving network and an output matching network. The intermediate-stage linearity improving network comprises two matching branches with the same structure, and the two matching branches are connected in parallel to the output end of the input matching network; and the outputs of the two matching branches are respectively connected with the output-stage matching network. The integral matching circuit mainly adopts a capacitor, a microstrip line, an inductor and a resistor to isolate alternating current and improve stability.

Description

Technical Field

[0001] The invention belongs to the technical field of microwave integrated circuits, and in particular relates to a broadband high-linearity power amplifier. Background Art

[0002] With the continuous development of wireless technology, combat platforms in modern warfare have become increasingly complex. They are not limited to combat equipment with single functions and tasks, but need to simultaneously meet a variety of different combat requirements, such as reconnaissance, interference, detection, and communication. A large number of independent systems need to be deployed on a combat platform. In order to reduce the cost and size of combat platforms and achieve more intelligent collaborative operations, the new generation of electronic systems is constantly developing from a single function to a multi-functional electronic integration direction. A single system can integrate multiple functions such as electronic warfare, radar, and communications.

[0003] Different combat platforms have different requirements for performance indicators such as working frequency band, output power, and linearity. For example, 2-6GHz and 6-18GHz are important frequency bands for electronic warfare applications, mainly including electronic reconnaissance, electronic jamming and other functions, and the system needs to carry out high-power precision jamming strikes; and among them, the Ku band (12-18GHz) is an important frequency band for airborne satellite communication applications, which is used for command and control information of aircraft in airborne command posts and long-range early warning information of early warning aircraft, requiring narrowband continuous wave signals and having high requirements for linearity.

[0004] Currently, mainstream broadband power amplifier chips mainly focus on high power and high efficiency, lack consideration of power amplifier linearity, and are limited to application in high power and high efficiency scenarios. They are unable to cope with a variety of complex application scenarios, especially communication needs.

[0005] In 2015, Philippe Dennler and others from the Fraunhofer Center for Applied Physics in Germany designed a GaN MMIC 8W power amplifier operating at 6-18GHz. The amplifier has a gain of 21dB, but the PAE is only 10%, and there is no linearity improvement design. See [Dennler P, Maroldt S, Quay R, et al. Monolithic three-stage 6-18GHz high power amplifier with distributed interstage in GaN technology[C]. 2015 10th European Microwave Integrated Circuits Conference (EuMIC), Paris, 2015, 29-32].

[0006] In 2018, Bei Liu et al. from Nanyang Technological University, Singapore, used GaN technology to design and manufacture a power amplifier operating at 2.6-6.4 GHz. The power amplifier has an output power of more than 34.3 dBm and a drain efficiency of more than 62% within the operating bandwidth, and has a wireless linearity improvement design. See [Liu B, Mao M, Khanna D, et al. A Novel 2.6-6.4 GHz Highly Integrated Broadband GaN Power Amplifier [J]. IEEE Microwave & Wireless Components Letters, 2017, PP (99): 1-3].

[0007] Macom's product CMPA2560025D uses GaN HEMT technology, operates at 2-6GHz, has an output power of 45dBm, a large signal gain greater than 20dB, and a PAE higher than 30%. However, the third-order intermodulation IMD3 is only -25dBc when the power is backed off by 10dB, and there is no linearity improvement design. See [https: / / www.macom.com / products / product-detail / CMPA2560025].

[0008] Qorvo's product QPA1013D uses GaN HEMT technology, has an operating frequency of 6 to 18 GHz, a small signal gain of 25 dB, a large signal gain of 20 dB, and an output power of 40 dBm, but the third-order intermodulation IMD3 is only -20 dBc when the power is backed off by 10 dB, and there is no specific linearization design. See [https: / / www.qorvo.com / products / p / QPA1013D].

[0009] It can be seen that the current broadband power amplifier chips mainly focus on high power and high efficiency, and there is no good integrated design method to improve their linearity to meet communication needs. In specific applications, an external linearity improvement circuit is required. Summary of the invention

[0010] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a broadband high linearity power amplifier which can improve linearity to a certain extent while maintaining ultra-wideband, high power and high efficiency.

[0011] The object of the present invention is achieved through the following technical solutions: a broadband high linearity power amplifier, comprising an input matching network, an intermediate stage linearity enhancement network and an output matching network;

[0012] (1) The input matching network includes a series-connected DC blocking capacitor C0, microstrip lines MLIN1-MLIN3, a first transistor Q1, a microstrip line MLIN5 and a DC blocking capacitor C4, as well as input matching capacitors C1, C2, C3, a first gate power supply circuit, and a first drain matching circuit; the DC blocking capacitor C0 is connected to the RF input Input Pad, and MLIN3 is connected to the gate of the first transistor Q1; the drain of the first transistor Q1 is connected to MLIN5, and the source is grounded; the capacitor C4 is connected to the intermediate-stage linearity improvement network;

[0013] One end of the capacitor C1 is connected between the DC blocking capacitor C0 and MLIN1, one end of the capacitor C2 is connected between MLIN1 and MLIN2, one end of the capacitor C3 is connected between MLIN2 and MLIN3, and the other ends of the capacitors C1, C2, and C3 are all grounded; one end of the first gate power supply circuit is connected in parallel between MLIN3 and the first transistor Q1, and the other end is connected to the first-stage gate power supply to provide a gate bias for the first transistor Q1; one end of the first drain matching circuit is connected between MLIN5 and the capacitor C4, and the other end is connected to the first drain power supply;

[0014] (2) The intermediate-stage linearity enhancement network includes two matching branches with the same structure, and the two matching branches are connected in parallel at the output end of capacitor C4; each matching branch includes a three-stage matching circuit;

[0015] ① The primary matching circuit includes a microstrip line MLIN6, a microstrip line MLIN7, a second transistor Q2, a microstrip line MLIN9, a DC blocking capacitor C7, a DC blocking capacitor C8, a second gate power supply circuit, a second drain matching circuit, a power matching circuit, and a cold mode linearization matching circuit connected in series; MLIN6 is connected to the output end of the capacitor C4, and the output end of the capacitor C8 is connected to the secondary matching circuit;

[0016] The microstrip line MLIN7 is connected to the gate of the second transistor Q2; the drain of the second transistor Q2 is connected to MLIN9, and the source is grounded; one end of the second gate power supply circuit is connected between MLIN7 and the second transistor Q2, and the other end is connected to the second gate power supply to provide a gate bias for the second transistor Q2; one end of the second drain matching circuit is connected between the second transistor Q2 and MLIN9, and the other end is connected to the second drain power supply; one end of the power matching circuit is connected between MLIN9 and the capacitor C7, and the other end is connected to the power supply Vc;

[0017] The cold mode linearization matching circuit includes a cold mode tube Q3, the gate of the cold mode tube Q3 is connected between MLIN9 and the capacitor C7 through an air bridge, the drain is connected between the capacitors C7 and C8, and the source is grounded;

[0018] ② The secondary matching circuit includes two secondary matching branches with the same structure, and the two secondary matching branches are connected in parallel at the output end of the capacitor C8; the secondary matching branch includes a microstrip line MLIN10, a fourth transistor Q4 and a microstrip line MLIN11 connected in series, and a third gate power supply circuit; one end of MLIN10 is connected to the capacitor C8, and the other end is connected to the gate of the fourth transistor Q4; the drain of the fourth transistor Q4 is connected to MLIN11, and the source is grounded; one end of the third gate power supply circuit is connected between MLIN10 and the third transistor Q4, and the other end is connected to the third gate power supply to provide a gate bias for the third transistor Q4;

[0019] ③ The three-stage matching circuit includes microstrip lines MLIN13 and MLIN14 connected in series, and a third drain matching circuit; the outputs of the two secondary matching branches are respectively connected to MLIN13, and MLIN14 is connected to the output matching network; one end of the third drain matching circuit is connected between the secondary matching branch and MLIN13, and the other end is connected to the third drain power supply;

[0020] (3) The output matching network includes a microstrip line MLIN15 and a DC blocking capacitor C14 connected in series. The outputs of the two matching branches of the intermediate-stage linearity enhancement network are respectively connected to MLIN15, and the capacitor C14 is directly connected to the RF output Output Pad.

[0021] The amplifier also includes a plurality of DC blocking capacitors; wherein one end of capacitor C5 is connected to the output end of capacitor C4, and the other end is grounded; one end of capacitor C6 is connected between microstrip lines MLIN6 and MLIN7, and the other end is grounded; one end of capacitor C9 is connected to the output end of capacitor C8, and the other end is grounded; one end of capacitor C10 is connected between the secondary matching branch and MLIN13, and the other end is grounded; one end of capacitor C11 is connected between MLIN13 and MLIN14, and the other end is grounded; one end of capacitor C12 is connected between the intermediate-stage linearity enhancement network and MLIN15, and the other end is grounded; one end of capacitor C13 is connected between MLIN15 and capacitor C14, and the other end is grounded.

[0022] The beneficial effects of the present invention are as follows: the present invention proposes a broadband high linearity power amplifier, the overall scheme is a three-stage amplification circuit, the matching networks and transistors of each stage are arranged completely symmetrically, and the driving ratio is 1:2:4. The matching network is divided into an input stage matching circuit, an intermediate stage matching circuit and an output stage matching circuit. Through the three-stage matching circuit, gain can be provided for the signal to achieve high power and high efficiency. A cold-mode linearization matching circuit composed of a cold-mode tube is added to the intermediate stage matching circuit, and the cold-mode linearization technology is combined with the broadband gain compensation technology, which not only realizes broadband positive slope gain matching, but also improves the linearity of the power amplifier. At the same time, the linearity can be improved under various working conditions by adjusting the cold-mode tube control voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic structural diagram of a broadband high linearity power amplifier of the present invention;

[0024] Figure 2 This is a power efficiency simulation diagram of Example 1 of the present invention;

[0025] Figure 3 This is a comparison diagram of the third-order intermodulation simulation at 6 GHz, 10 GHz, 14 GHz and 18 GHz according to Example 1 of the present invention;

[0026] Figure 4 This is a simulation diagram of the third-order intermodulation of the 12 GHz regulation control voltage according to Example 1 of the present invention. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0028] like Figure 1 As shown, a 6-18GHz broadband high linearity power amplifier circuit provided by this embodiment includes an input matching network, an intermediate stage linearity enhancement network and an output matching network; the characters C and Cc in the figure both represent capacitors (they play different roles in the circuit, so different letters are used to distinguish them), R represents resistors, L represents inductors, MLIN represents bias microstrip lines, and Q1 to Q4 are all transistors (they play different roles in the circuit and have different names). The overall matching circuit mainly uses capacitors and microstrip lines, and inductors and resistors are used to isolate and improve stability. A broadband cold-mode tube linearization structure is introduced in the second and third stage inter-stage matching circuits to improve full-band linearity.

[0029] (1) The input matching network includes a series-connected DC blocking capacitor C0, microstrip lines MLIN1-MLIN3, a first transistor Q1, a microstrip line MLIN5 and a DC blocking capacitor C4, as well as input matching capacitors C1, C2, C3, a first gate power supply circuit, and a first drain matching circuit; the DC blocking capacitor C0 is connected to the RF input Input Pad, and MLIN3 is connected to the gate of the first transistor Q1; the drain of the first transistor Q1 is connected to MLIN5, and the source is grounded; the capacitor C4 is connected to the intermediate-stage linearity improvement network;

[0030] One end of capacitor C1 is connected between DC blocking capacitor C0 and MLIN1, one end of capacitor C2 is connected between MLIN1 and MLIN2, one end of capacitor C3 is connected between MLIN2 and MLIN3, and the other ends of capacitors C1, C2, and C3 are all grounded; input matching microstrip lines MLIN1, MLIN2, and MLIN3 and input matching capacitors C1, C2, and C3 form a third-order LC matching network. One end of the first gate power supply circuit is connected in parallel between MLIN3 and the first transistor Q1, and the other end is connected to the first-stage gate power supply to provide gate bias for the first transistor Q1; one end of the first drain matching circuit is connected between MLIN5 and capacitor C4, and the other end is connected to the first drain power supply.

[0031] (2) The intermediate-stage linearity enhancement network includes two matching branches M1 and M2 with the same structure, and the two matching branches are connected in parallel at the output end of the DC blocking capacitor C4; each matching branch includes a three-stage matching circuit;

[0032] ① The primary matching circuit includes a microstrip line MLIN6, a microstrip line MLIN7, a second transistor Q2, a microstrip line MLIN9, a DC blocking capacitor C7, a DC blocking capacitor C8, a second gate power supply circuit, a second drain matching circuit, a power matching circuit, and a cold mode linearization matching circuit connected in series; MLIN6 is connected to the output end of the capacitor C4, and the output end of the capacitor C8 is connected to the secondary matching circuit;

[0033] The microstrip line MLIN7 is connected to the gate of the second transistor Q2; the drain of the second transistor Q2 is connected to MLIN9, and the source is grounded; one end of the second gate power supply circuit is connected between MLIN7 and the second transistor Q2, and the other end is connected to the second gate power supply to provide a gate bias for the second transistor Q2; one end of the second drain matching circuit is connected between the second transistor Q2 and MLIN9, and the other end is connected to the second drain power supply; one end of the power matching circuit is connected between MLIN9 and the capacitor C7, and the other end is connected to the power supply Vc;

[0034] The cold mode linearization matching circuit comprises a cold mode tube Q3, a gate of the cold mode tube Q3 is connected between MLIN9 and the capacitor C7 through an air bridge, a drain is connected between the capacitors C7 and C8, and a source is grounded.

[0035] ② The secondary matching circuit includes two secondary matching branches M3 and M4 with the same structure, and the two secondary matching branches are connected in parallel at the output end of the capacitor C8; the secondary matching branch includes a microstrip line MLIN10, a fourth transistor Q4 and a microstrip line MLIN11 connected in series, and a third gate power supply circuit; one end of MLIN10 is connected to the capacitor C8, and the other end is connected to the gate of the fourth transistor Q4; the drain of the fourth transistor Q4 is connected to MLIN11, and the source is grounded; one end of the third gate power supply circuit is connected between MLIN10 and the third transistor Q4, and the other end is connected to the third gate power supply to provide a gate bias for the third transistor Q4.

[0036] ③ The three-stage matching circuit includes microstrip lines MLIN13 and MLIN14 connected in series, and a third drain matching circuit; the outputs of the two secondary matching branches are respectively connected to MLIN13, and MLIN14 is connected to the output matching network; one end of the third drain matching circuit is connected between the secondary matching branch and MLIN13, and the other end is connected to the third drain power supply.

[0037] (3) The output matching network includes a microstrip line MLIN15 and a DC blocking capacitor C14 connected in series. The outputs of the two matching branches of the intermediate-stage linearity enhancement network are respectively connected to MLIN15, and the capacitor C14 is directly connected to the RF output Output Pad.

[0038] The structures of the first gate power supply circuit, the second gate power supply circuit and the third gate power supply circuit are the same; they include DC blocking inductors L1 / L2 / L3 and decoupling capacitors Cc1 / Cc3 / Cc6, the DC blocking inductors L1 / L2 / L3 and the decoupling capacitors Cc1 / Cc3 / Cc6 are connected in parallel to form a low-pass filtering structure (the DC blocking inductors L1 and the decoupling capacitors Cc1 are connected in parallel to form a low-pass filtering structure, the DC blocking inductors L2 and the decoupling capacitors Cc3 are connected in parallel to form a low-pass filtering structure, and the DC blocking inductors L3 and the decoupling capacitors Cc6 are connected in parallel to form a low-pass filtering structure), the parallel ends are connected to the first / second / third level gate power supplies, the other ends of the DC blocking inductors L1 / L2 / L3 are connected to the gates of the first transistor Q1 / the second transistor Q2 / the third transistor Q4, and the other ends of the decoupling capacitors Cc1 / Cc3 / Cc6 are grounded.

[0039] The structures of the first drain matching circuit, the second drain matching circuit, and the third drain matching circuit are the same; they include microstrip lines MLIN4 / MLIN8 / MLIN12 and decoupling capacitors Cc2 / Cc4 / Cc7, ​​the microstrip lines MLIN4 / MLIN8 / MLIN12 are connected in parallel with the decoupling capacitors Cc2 / Cc4 / Cc7, ​​and the parallel ends thereof are connected to the first / second / third drain power supply; the other end of the microstrip line MLIN4 is connected between MLIN5 and the capacitor C4, the other end of MLIN8 is connected between the second transistor Q2 and MLIN9, and the other end of MLIN12 is connected between the secondary matching branch and MLIN13; the other end of the decoupling capacitors Cc2 / Cc4 / Cc7 is grounded. The microstrip line MLIN4, on the one hand, forms a low-pass filter structure with the decoupling capacitor Cc2, and on the other hand, participates in the intermediate matching network and forms an LC parallel network with the DC blocking capacitor C4. The microstrip line MLIN8 forms a low-pass filter structure with the decoupling capacitor Cc4 and is connected to the second-stage drain power supply Pad, and participates in the intermediate matching network. The microstrip line MLIN12 forms a low-pass filter structure with the decoupling capacitor Cc4 and participates in the intermediate matching network.

[0040] The power matching circuit includes a resistor R1 and a decoupling capacitor Cc5, which are connected in parallel, and the parallel end is connected to the power supply Vc. The other end of the resistor R1 is connected between the microstrip line MLIN9 and the capacitor C7, and the other end of the decoupling capacitor Cc5 is grounded. The resistor R1 uses a large resistor to isolate the cross; the decoupling capacitor Cc5 is used to filter the ripple. The Vc voltage is flexibly adjusted according to the working conditions to achieve the optimal linearization effect.

[0041] The amplifier also includes a plurality of DC blocking capacitors; one end of capacitor C5 is connected to the output end of capacitor C4, and the other end is grounded; one end of capacitor C6 is connected between microstrip lines MLIN6 and MLIN7, and the other end is grounded; microstrip lines MLIN6, MLIN7 and capacitors C5 and C6 form a two-stage LC matching network, wherein the overall matching network S21 presents a positive slope gain curve with low low-frequency gain and high high-frequency gain, compensating for the gain roll-off trend of the transistor. One end of capacitor C9 is connected to the output end of capacitor C8, and the other end is grounded; MLIN10 and the second and third stage matching capacitors C9 form a first-order LC matching network. One end of capacitor C10 is connected between the secondary matching shunt and MLIN13, and the other end is grounded; one end of capacitor C11 is connected between MLIN13 and MLIN14, and the other end is grounded; one end of capacitor C12 is connected between the intermediate linearity improvement network and MLIN15, and the other end is grounded; microstrip lines MLIN13, MLIN13, MLIN14 and parallel matching capacitors C10, C11, C12 form a third-order LC matching network. One end of capacitor C13 is connected between MLIN15 and capacitor C14, and the other end is grounded.

[0042] The size of the cold mold tube needs to be selected according to the optimal input impedance of the transistor Q4 to control the insertion loss within 4dB. At the same time, the matching circuit S21 needs to present a positive slope gain curve with low low-frequency gain and high high-frequency gain to compensate for the gain roll-off trend of the transistor.

[0043] A cold mode tube is a triode working in the deep triode region, that is, when Vds<<2(Vgs-Vth), where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. At this time, it is equivalent to a resistor, and the resistance value changes with Vgs, which is called a cold mode (ColdMode) tube. The resistance value of the cold mode tube gradually increases with the increase of power. If it is connected in parallel in the circuit, it will bring about the increase of S21 with the increase of input power, that is, gain expansion, which is just used to compensate for the gain compression of the power amplifier and improve linearity. The input impedance of the cold mode tube changes little with respect to frequency, and the resistance value can be adjusted by Vgs. The optimal input impedance of the power amplifier gradually increases with the increase of frequency. Therefore, the insertion loss of the cold mode tube gradually decreases with the increase of frequency. This effect can just compensate for the gain roll-off of the power amplifier, that is, to achieve a gain matching network with a positive slope.

[0044] Example 1

[0045] The cold mold tube size is selected by the input impedance Zin before the power tube; the input impedance Zin before the power tube gin The calculation formula for cold mold tube insertion loss can be obtained by adding Zin control through S parameter simulation: The equivalent circuit of the cold mold tube consists of three parts, among which C off With R off are the cold mold tube equivalent off-state capacitance and off-state equivalent resistance, R ds is the equivalent internal resistance of the cold mold tube, and ω is the frequency. ds Equivalent off-state capacitance C of cold mold tube off The input impedance Z of the cold mold tube can be directly din The real and imaginary parts of the cold mold tube are directly obtained, and the cold mold tube insertion loss IL is further converted into the input impedance Z of the cold mold tube. din The input impedance Z before the power tube gin The calculation formula By selecting the cold mold tube size, the insertion loss is changed to be less than 3dB and presents a positive slope insertion loss curve with low high-frequency insertion loss and high low-frequency differential loss.

[0046] Figure 2 This is the output power simulation diagram of Example 1, from Figure 2 It can be seen that the amplifier circuit has an output power greater than 40dBm, a power added efficiency greater than 15%, and a gain greater than 20dB in the entire operating frequency range of 6 to 18GHz;

[0047] Figure 3 (a), (b), (c), and (d) are respectively the comparison diagrams of the third-order intermodulation simulation at 6GHz, 10GHz, 14GHz, and 18GHz in Example 1, where the original power amplifier is the linearized broadband power amplifier of this invention, the cold mode linearization module is removed, and the second and third level matching networks are redesigned, and the other parts remain unchanged, and the bias is consistent with the power amplifier of this invention, which is in the common AB class with a gate width of 100mA / mm. Figure 3 It can be seen that the three-level intermodulation of the power amplifier is improved in the entire frequency band, and is less than -30dBc after the output power is backed off by 8dB.

[0048] Figure 4 This is a simulation diagram of the third-order intermodulation of the 12GHz control voltage regulation of Example 1. Figure 4 It can be seen that adjusting the cold mode tube gate voltage Vc can flexibly adjust the third-order intermodulation curve to adapt to different output power conditions. For example, when the output is 36dBm, Vc=-0.5V can be selected to have the best linearity effect, and when the output is 30dBm, Vc=-1.7V can be selected to have the best linearity effect, and other frequency points are similar.

[0049] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A broadband high linearity power amplifier, characterized in that: Including input matching network, intermediate linearity improvement network and output matching network; (1) The input matching network includes a series-connected DC blocking capacitor C0, microstrip lines MLIN1-MLIN3, a first transistor Q1, a microstrip line MLIN5 and a DC blocking capacitor C4, as well as input matching capacitors C1, C2, C3, a first gate power supply circuit, and a first drain matching circuit; the DC blocking capacitor C0 is connected to the RF input Input Pad, and MLIN3 is connected to the gate of the first transistor Q1; the drain of the first transistor Q1 is connected to MLIN5, and the source is grounded; the capacitor C4 is connected to the intermediate-stage linearity improvement network; One end of the capacitor C1 is connected between the DC blocking capacitor C0 and MLIN1, one end of the capacitor C2 is connected between MLIN1 and MLIN2, one end of the capacitor C3 is connected between MLIN2 and MLIN3, and the other ends of the capacitors C1, C2, and C3 are all grounded; one end of the first gate power supply circuit is connected in parallel between MLIN3 and the first transistor Q1, and the other end is connected to the first-stage gate power supply to provide a gate bias for the first transistor Q1; one end of the first drain matching circuit is connected between MLIN5 and the capacitor C4, and the other end is connected to the first drain power supply; (2) The intermediate-stage linearity enhancement network includes two matching branches with the same structure, and the two matching branches are connected in parallel at the output end of capacitor C4; each matching branch includes a three-stage matching circuit; ① The primary matching circuit includes a microstrip line MLIN6, a microstrip line MLIN7, a second transistor Q2, a microstrip line MLIN9, a DC blocking capacitor C7, a DC blocking capacitor C8, a second gate power supply circuit, a second drain matching circuit, a power matching circuit, and a cold mode linearization matching circuit connected in series; MLIN6 is connected to the output end of the capacitor C4, and the output end of the capacitor C8 is connected to the secondary matching circuit; The microstrip line MLIN7 is connected to the gate of the second transistor Q2; the drain of the second transistor Q2 is connected to MLIN9, and the source is grounded; one end of the second gate power supply circuit is connected between MLIN7 and the second transistor Q2, and the other end is connected to the second gate power supply to provide a gate bias for the second transistor Q2; one end of the second drain matching circuit is connected between the second transistor Q2 and MLIN9, and the other end is connected to the second drain power supply; one end of the power matching circuit is connected between MLIN9 and the capacitor C7, and the other end is connected to the power supply Vc; The cold mode linearization matching circuit includes a cold mode tube Q3, the gate of the cold mode tube Q3 is connected between MLIN9 and the capacitor C7 through an air bridge, the drain is connected between the capacitors C7 and C8, and the source is grounded; ② The secondary matching circuit includes two secondary matching branches with the same structure, and the two secondary matching branches are connected in parallel at the output end of the capacitor C8; the secondary matching branch includes a microstrip line MLIN10, a fourth transistor Q4 and a microstrip line MLIN11 connected in series, and a third gate power supply circuit; one end of MLIN10 is connected to the capacitor C8, and the other end is connected to the gate of the fourth transistor Q4; the drain of the fourth transistor Q4 is connected to MLIN11, and the source is grounded; one end of the third gate power supply circuit is connected between MLIN10 and the third transistor Q4, and the other end is connected to the third gate power supply to provide a gate bias for the third transistor Q4; ③ The three-stage matching circuit includes microstrip lines MLIN13 and MLIN14 connected in series, and a third drain matching circuit; the outputs of the two secondary matching branches are respectively connected to MLIN13, and MLIN14 is connected to the output matching network; one end of the third drain matching circuit is connected between the secondary matching branch and MLIN13, and the other end is connected to the third drain power supply; (3) The output matching network includes a microstrip line MLIN15 and a DC blocking capacitor C14 connected in series. The outputs of the two matching branches of the intermediate-stage linearity enhancement network are respectively connected to MLIN15, and the capacitor C14 is directly connected to the RF output Output Pad.

2. A broadband high linearity power amplifier according to claim 1, characterized in that: The structures of the first gate power supply circuit, the second gate power supply circuit and the third gate power supply circuit are the same; they include DC blocking inductors L1 / L2 / L3 and decoupling capacitors Cc1 / Cc3 / Cc6, the DC blocking inductors L1 / L2 / L3 and the decoupling capacitors Cc1 / Cc3 / Cc6 are connected in parallel to form a low-pass filtering structure, the parallel ends are connected to the first / second / third level gate power supply, the other ends of the DC blocking inductors L1 / L2 / L3 are connected to the gates of the first transistor Q1 / the second transistor Q2 / the third transistor Q4, and the other ends of the decoupling capacitors Cc1 / Cc3 / Cc6 are grounded.

3. A broadband high linearity power amplifier according to claim 1, characterized in that: The structures of the first drain matching circuit, the second drain matching circuit and the third drain matching circuit are the same; they include microstrip lines MLIN4 / MLIN8 / MLIN12 and decoupling capacitors Cc2 / Cc4 / Cc7, ​​the microstrip lines MLIN4 / MLIN8 / MLIN12 are connected in parallel with the decoupling capacitors Cc2 / Cc4 / Cc7, ​​and the parallel ends thereof are connected to the first / second / third drain power supply; the other end of the microstrip line MLIN4 is connected between MLIN5 and the capacitor C4, the other end of MLIN8 is connected between the second transistor Q2 and MLIN9, the other end of MLIN12 is connected between the secondary matching branch and MLIN13; the other end of the decoupling capacitors Cc2 / Cc4 / Cc7 is grounded.

4. The broadband high linearity power amplifier according to claim 1, characterized in that: The power matching circuit includes a resistor R1 and a decoupling capacitor Cc5, which are connected in parallel, and the parallel end is connected to the power supply Vc, the other end of the resistor R1 is connected between the microstrip line MLIN9 and the capacitor C7, and the other end of the decoupling capacitor Cc5 is grounded.

5. The broadband high linearity power amplifier according to claim 1, characterized in that: The amplifier also includes a plurality of DC blocking capacitors; wherein one end of capacitor C5 is connected to the output end of capacitor C4, and the other end is grounded; one end of capacitor C6 is connected between microstrip lines MLIN6 and MLIN7, and the other end is grounded; one end of capacitor C9 is connected to the output end of capacitor C8, and the other end is grounded; one end of capacitor C10 is connected between the secondary matching branch and MLIN13, and the other end is grounded; one end of capacitor C11 is connected between MLIN13 and MLIN14, and the other end is grounded; one end of capacitor C12 is connected between the intermediate-stage linearity enhancement network and MLIN15, and the other end is grounded; one end of capacitor C13 is connected between MLIN15 and capacitor C14, and the other end is grounded.

Images