Multi-gate differential power amplifier

Abstract

The invention relates to a multi-gate differential power amplifier. A differential power amplifier circuit includes: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier coupled in parallel with the first differential power amplifier and including a plurality of multi-gate transistors.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits and, more particularly, to multi-gate differential power amplifiers. Background Art

[0002] Power amplifiers are used in many integrated circuit applications. For example, power amplifiers are often included in wireless communication devices such as cellular phones, two-way radios, etc. One type of power amplifier is a differential power amplifier, which is configured to amplify the difference between two input signals and reject any common mode (common) signals. Summary of the invention

[0003] Some aspects of the present disclosure include a differential power amplifier circuit comprising: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier coupled in parallel with the first differential power amplifier and including a plurality of multi-gate transistors.

[0004] Some aspects of the present disclosure also include a differential power amplifier circuit, comprising: a first differential power amplifier, comprising a first and a second parallel branch, wherein the first differential power amplifier comprises a first and a second neutralization capacitor cross-coupled between the first and the second parallel branches; and a second multi-gate differential power amplifier, comprising a first and a second parallel branch, wherein the first and the second parallel branches of the second differential power amplifier are respectively coupled to the first and the second parallel branches of the first differential power amplifier.

[0005] Some aspects of the present disclosure also include a radio frequency (RF) differential power amplifier circuit, comprising: an RF input stage, which is used to receive an RF input signal; a first differential power amplifier, which includes a first and a second parallel branch coupled to the RF input stage, wherein the first differential power amplifier includes a first and a second neutralization capacitor cross-coupled between the first and the second parallel branches; a second multi-gate differential power amplifier, which includes a first and a second parallel branch coupled to the RF input stage, wherein the first and the second parallel branches of the second differential power amplifier are respectively coupled to the first and the second parallel branches of the first differential power amplifier; and an RF output stage, which is coupled to the first and the second differential power amplifiers for outputting an amplified RF signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure may be better understood by the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale. In the accompanying drawings, like reference numerals represent like features throughout the various views.

[0007] Figure 1 A conventional differential power amplifier in a radio frequency (RF) environment is shown.

[0008] Figure 2 A conventional differential power amplifier including cross-coupled neutralizing transistors in an RF environment is shown.

[0009] Figure 3 A conventional dual-gate implementation of a single-ended power amplifier is shown.

[0010] Figure 4 and 5 A dual-gate differential power amplifier circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0011] The present disclosure will now be described with reference to a multi-gate differential power amplifier. Although the present disclosure will be described below in conjunction with specific devices and methods thereof, it will be understood that it is not intended to limit the present disclosure to such specific devices and methods. On the contrary, it is intended to cover all alternatives, modifications and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims.

[0012] To generally understand the features of the present disclosure, reference is made to the accompanying drawings. However, the drawings are not drawn to scale and like reference numerals are used throughout to identify like elements.

[0013] It will be readily understood that the devices and methods of the present disclosure, as generally described and illustrated in the figures herein, may be arranged and designed in a variety of different configurations in addition to the devices and methods described herein. Therefore, the following detailed description of the devices and methods illustrated in the figures is not intended to limit the scope defined by the appended claims, but is merely representative of selected devices and methods. The following description is by way of example only and simply illustrates certain concepts of the devices and methods disclosed and claimed herein.

[0014] Figure 1 A conventional differential power amplifier 10 is shown in a radio frequency (RF) environment. Such a differential power amplifier 10 may be used, for example, in a wireless transmitter.

[0015] The differential power amplifier 10 includes a driver stage 12 including a pair of common-source transistors M1 and M2 and a power stage 14 including a pair of common-gate transistors M3 and M4. The common-source transistors M1 and M2 each include a parasitic gate-drain capacitance Cgd, and the common-gate transistors M3 and M4 include a parasitic drain-source capacitance Cds. In the configuration shown, the differential power amplifier 10 is unstable due to the parasitic capacitances Cds and Cgs.

[0016] Figure 2A technique for improving the operation of a differential power amplifier 10 is shown. Specifically, the gain and stability of the differential power amplifier 10 can be improved by using a cross-coupled neutralization capacitor Cn to offset the effect of the parasitic capacitance Cgd. As shown, a first neutralization capacitor Cn can be coupled between the gate of the drive transistor M1 and a node (node ​​B) between the drive transistor M2 and the power transistor M4. A second neutralization capacitor Cn can be coupled to a node between the gate of the drive transistor M2 and a node (node ​​A) between the drive transistor M1 and the power transistor M3.

[0017] Each of the transistors M1, M2 in the driver stage 12 of the differential power amplifier 10 can be implemented using multiple (N) power primitives. Similarly, each of the transistors M3, M4 in the power stage 14 of the differential power amplifier 10 can be implemented using multiple (M) power primitives. At this point, the differential power amplifier 10 can be implemented using a total of 2x(M+N) power primitives. Typically, M≥N. As is well known in the art, each power primitive can include one or more power transistors designed to improve the efficiency, linearity, output, and cost of the power amplifier. The transistors in the power primitive can be connected in series (e.g., stacked) to provide each of the transistors M1-M4.

[0018] Multi-gate (eg, dual-gate) implementations have been used to provide transistors in single-ended power amplifiers to reduce parasitic capacitance, thereby improving Psat (saturated output power) / PAE (power added efficiency) of the single-ended power amplifier. Figure 3 An example of a single-ended power amplifier 20 including a dual-gate implementation is shown that merges transistor M1 (having gate G1) with transistor M3 (having gate G3). As described herein, merging refers to the merging of source and drain diffusion regions of multiple stacked transistors, thereby producing a single effective transistor with multiple gate regions.

[0019] Multi-gate implementation cannot be used for Figure 2 Specifically, if the transistors M1 and M3 of the differential power amplifier 10 are combined using a dual-gate implementation, and the transistors M2 and M4 are also combined using a dual-gate implementation, then the nodes A and B are no longer accessible, thereby preventing Figure 2 The connection of the neutralizing capacitor Cn is shown. To date, multi-gate (eg, dual-gate) implementations of differential power amplifiers remain to be developed.

[0020] Figure 4A multi-gate (hereinafter referred to as "dual gate") differential power amplifier circuit 100 according to an embodiment of the present disclosure is shown. As shown, the dual gate differential power amplifier circuit 100 includes a first differential power amplifier 102, which includes a cross-coupled neutralization capacitor Cn and is connected in parallel with a second differential power amplifier 104 implemented using a multi-gate (hereinafter referred to as "dual gate") transistor array 106. It should be understood that the dual gate differential power amplifier circuit 100 can be configured to operate within a radio frequency (RF) band (i.e., 3kHz to 300GHz), and can be configured to operate within its millimeter wave (mmWave) band (e.g., 30GHz-300GHz), for example.

[0021] The first differential power amplifier 102 includes a plurality of stages. These stages may include, but are not limited to, a radio frequency (RF) input stage 110, a driver stage 112, a power stage 114, and an RF output stage 116. For example, as described in further detail below, the driver stage 112 may include a pair of common source transistors M1, M2 (hereinafter referred to as driver transistors M1, M2), and the power stage 114 may include first and second common gate transistors M3, M4 (hereinafter referred to as power transistors M3, M3) connected in series with the driver transistors M1, M2 in the driver stage, respectively. At this point, the first differential power amplifier 102 includes two parallel branches located between the RF input stage 110 and the RF output stage 116, each branch including a driver transistor and a power transistor.

[0022] The RF input stage 110 may be configured to receive an RF input signal at an RF input node RFin, and the RF output stage 116 may be configured to provide impedance matching of an RF output signal at an RF output node RFout. The driver stage 112 may be connected between the RF input stage 110 and the power stage 114, and, for example, may be configured to regulate a current through the first differential power amplifier circuit 102 of the dual-gate differential power amplifier circuit 100.

[0023] In a transistor, a semiconductor (or channel region) is located between a conductive "source" region and a similarly conductive "drain" region, and when the semiconductor is in a conductive state, the semiconductor allows current to flow between the source and the drain. A "gate" is a conductive element that is electrically separated from the semiconductor by a "gate dielectric", and the current / voltage in the gate changes the conductivity of the transistor channel region. The transistors M1, M2 in the driver stage 112 and the transistors M3, M4 in the power stage can be n-type field effect transistors. In some embodiments, the transistors M1-M4 in the first differential power amplifier 102 can be implemented using an advanced semiconductor-on-insulator processing technology platform (e.g., a fully depleted semiconductor-on-insulator (FDSOI) technology platform).

[0024] Those skilled in the art will recognize that FDSOI is a planar process technology that uses an ultra-thin insulator layer, called a buried oxide, positioned on top of the base silicon. A very thin, optionally undoped silicon film implements the transistor channel. Details of the FDSOI transistor are omitted from this article to allow the reader to focus on the significant aspects of the systems and methods described herein. Alternatively, the first differential power amplifier 102 can be implemented in any other suitable technology platform.

[0025] The power stage 114 may be connected between the driver stage 112 and the RF output stage 116 and, for example, may be configured to amplify the RF input signal and convert it from a lower power RF signal to a higher power RF signal. The RF output stage 116 may be connected to the power stage 114 and, for example, may be configured to receive and output a higher power output signal.

[0026] The RF input stage 110 may include an RF input node for receiving an RF input signal at an RF input node RFin. The RF input stage 110 may also include an RF input transformer 118, for example, to match the input impedance of the RF input stage with the impedance of the previous stage. The input transformer 118 may include two magnetically coupled input windings 120, 122. The input winding 120 may include a first terminal electrically connected to the RF input node RFin. The second opposite terminal of the input winding 120 may be electrically connected to the ground, as shown, so that the input transformer 118 is a balun (i.e., a balanced to unbalanced signal conversion transformer). In other embodiments, the second opposite terminal of the input winding 120 may be connected to the negative pole of the differential input instead of the ground (not shown). The first terminal of the input winding 122 may be electrically connected to the gate of the driving transistor M1 to provide the positive input voltage Vinp to the gate of the driving transistor M1. The second terminal of the input winding 122 may be electrically connected to the gate of the driving transistor M2 to provide the negative input voltage Vinm to the gate of the driving transistor M2. The center tap of the input winding may be used to bias the drive transistors M1 , M2 .

[0027] The RF output stage 116 may include an RF output node RFout for outputting the amplified RF signal. The RF output stage 116 may also include, for example, an RF output transformer 124, which includes two magnetically coupled output windings 126, 128. The output winding 128 may have one terminal electrically connected to the RF output node RFout and an opposite terminal electrically connected to ground, as shown. The first and second terminals of the output winding 126 may be electrically connected to the source / drain regions (e.g., drain regions in the case of NFET driver transistors) of the power transistors M3, M4, respectively.

[0028] In the driver stage 112, each driver transistor M1, M2 includes a gate electrically connected to the input stage 110 as described above. The source / drain region (e.g., source region in the case of an NFET driver transistor) of each driver transistor M1, M2 is electrically connected to ground. The source / drain region (e.g., drain region in the case of an NFET driver transistor) of the driver transistor M1 is electrically connected in series to the source / drain region (e.g., source region in the case of an NFET driver transistor) of the power transistor M3. Similarly, the source / drain region (e.g., drain region in the case of an NFET driver transistor) of the driver transistor M2 is electrically connected in series to the source / drain region (e.g., source region in the case of an NFET driver transistor) of the power transistor M4.

[0029] In the power stage 116, the voltage Vcas is passed through the RC network 130 to provide a bias voltage Vcf, which is applied to the gate of each power transistor M3, M4. In addition, as described above, the source / drain regions (e.g., source regions in the case of NFET drive transistors) of the power transistors M3, M4 are electrically connected to the source / drain regions (e.g., drain regions in the case of NFET drive transistors) of the drive transistors M1, M2, respectively. In addition, as described above, the source / drain regions (e.g., drain regions in the case of NFET drive transistors) of the power transistors M3, M4 can be electrically connected to the first terminal and the second terminal of the output winding 126 of the RF output stage 116, respectively.

[0030] The first neutralization capacitor Cn may be coupled between the gate of the driving transistor M1 and the node (node ​​B) between the driving transistor M2 and the power transistor M4. The second neutralization capacitor Cn may be coupled between the gate of the driving transistor M2 and the node (node ​​A) between the driving transistor M1 and the power transistor M3. The neutralization capacitor Cn is used to offset the parasitic gate-drain capacitance Cgd of the driving transistors M1 and M2, and improve the reverse isolation, power gain, and stability of the dual-gate differential power amplifier circuit 100.

[0031] like Figure 4As further shown, the dual-gate transistor array 106 includes a first dual-gate transistor DG1 (combining the driver transistor M1 and the power transistor M3) in a first parallel branch and a second dual-gate transistor DG2 (combining the driver transistor M2 and the power transistor M4) in a second parallel branch. As shown, the source / drain regions (e.g., source regions in the case of an NFET driver transistor) of the first and second dual-gate transistors DG1, DG2 are electrically connected to ground. In addition, the source / drain region (e.g., drain region in the case of an NFET driver transistor) of the first dual-gate transistor DG1 is electrically connected to a node between the source / drain region of the power transistor M3 in the first differential power amplifier 102 and the output stage 116. Similarly, the source / drain region (e.g., drain region in the case of an NFET driver transistor) of the second dual-gate transistor DG2 is electrically connected to a node between the source / drain region (e.g., drain region in the case of an NFET driver transistor) of the power transistor M4 in the first differential power amplifier 102 and the output stage 116. The first gate of the first dual-gate transistor DG1 is gated by a positive input voltage Vinp (e.g., from the input stage 110). The first gate of the second dual-gate transistor DG2 is gated by a negative input voltage Vinm (e.g., from the input stage 110). A bias voltage Vcf (e.g., from the input stage 110) is applied to the second gate of the first dual-gate transistor DG1 and the second gate of the second dual-gate transistor DG2. The back gates of the first and second dual-gate transistors DG1, DG2 are biased with a voltage Vbg. The first and second dual-gate transistors DG1, DG2 reduce parasitic capacitance and thus improve Psat (saturated output power) / PAE (power added efficiency) of the dual-gate power amplifier circuit 100.

[0032] Temporary reference Figure 2 It can be seen that a total of 2x(M+N) power primitives can be used to implement the transistors M1-M4 in the differential power amplifier 10. For example, if N=M=12, a total of 48 power primitives are required to implement the differential power amplifier 10.

[0033] According to an embodiment of the present disclosure, the transistors M1-M4 in the first differential power amplifier 102 and the dual-gate transistors DG1, DG2 in the second differential power amplifier 104 can be implemented using a total of 2x(M+N) power primitives. An example of the allocation of the 2x(M+N) power primitives between the first differential power amplifier 102 and the second differential power amplifier 104 in the dual-gate differential power amplifier circuit 100 is provided below.

[0034] In the first example, if Figure 4As shown, assuming N=M. In this case, the second differential power amplifier 104 can be implemented using N-1 dual-gate transistors DG1 connected in series in the first parallel branch and N-1 dual-gate transistors DG2 connected in series in the second parallel branch, wherein each dual-gate transistor DG1, DG2 requires 2 power primitives, which are merged into 1 merged power primitive. Assuming N=12 again, then (N-1)=(12-1)=11, a total of 11 merged power primitives can be used to implement the dual-gate transistor DG1. Similarly, a total of 11 merged power primitives can be used to implement the dual-gate transistor DG2. In addition, each transistor M1-M4 in the first differential power amplifier 102 can be implemented using 1 power primitive.

[0035] In the second example, if Figure 5 As shown, it is assumed that N≠M (usually M>N). Similar to the example of M=N, the second differential power amplifier 104 can be implemented using N-1 dual-gate transistors DG1 connected in series in the first parallel branch and N-1 dual-gate transistors DG2 connected in series in the second parallel branch, wherein each dual-gate transistor DG1, DG2 requires 2 power primitives, which are merged into 1 merged power primitive. Assuming N=12 and M=14, then (N-1)=(12-1)=11, a total of 11 merged power primitives can be used to implement each dual-gate transistor DG1, DG2. In the first differential power amplifier 102, each power transistor M3, M4, for example, can be implemented using a total of (M-N+1)=(14-12+1)=3 power primitives, and each driving transistor M1, M2 can be implemented using 1 power primitive.

[0036] The neutralizing capacitor Cn in the first differential power amplifier 102 of the dual-gate differential power amplifier circuit 100 offsets the parasitic gate-drain capacitance Cgd of the driving transistors M1, M2 and the parasitic gate-drain capacitance Cgd of DG1 and DG2, and improves the reverse isolation, power gain and stability of the dual-gate differential power amplifier circuit 100. In addition, the dual-gate transistors DG1, DG2 in the second differential power amplifier 104 of the dual-gate differential power amplifier circuit 100 reduce the parasitic capacitance and thereby improve the Psat / PAE of the dual-gate power amplifier circuit 100. According to an embodiment, the performance of the dual-gate differential power amplifier circuit 100 is controlled by the N-1 array parasitics. For example, the drain-source node between the common source and common gate in the dual-gate transistor DG1 and the common source and common gate in the dual-gate transistor DG2 has a lower parasitic capacitance than the corresponding transistors M1-M4 in the first differential power amplifier 102. As described above, since most of the power primitives can be used to implement the dual-gate transistors DG1 and DG2, the global mid-node capacitance is greatly reduced, thereby providing higher Psat and PAE.

[0037] It should be understood that the terms used herein are used to describe the disclosed structures and methods and are not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, as used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof. In addition, as used herein, when oriented and shown in the figures, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "below", "under", "underlying", "above", "overlying", "parallel", "vertical", etc. are intended to describe relative positions (unless otherwise specified), and terms such as "touching", "direct contact", "adjacent", "directly adjacent", "immediately adjacent", etc. are intended to indicate that at least one element is in physical contact with another element (no other elements separate the elements). The term "laterally" is used herein to describe the relative position of elements and, more specifically, to indicate that one element is to the side of another element, rather than above or below the other element, when the elements are oriented and shown in the figures. For example, an element positioned laterally adjacent to another element will be to the side of the other element, an element positioned laterally next to another element will be directly to the side of the other element, and an element laterally surrounding another element will be adjacent to and bordering the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed.

[0038] References herein to terms modified by approximate language such as "approximately," "about," "substantially" are not limited to the exact value specified. Approximate language may correspond to the precision of the instrument used to measure the value, and may indicate + / - 10% of the stated value unless instrument precision is relied upon.

[0039] References to terms such as "vertical", "horizontal", etc. herein are by way of example and not limitation to establish a frame of reference. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to directions perpendicular to the horizontal direction just defined. The term "lateral" refers to a direction within a horizontal plane.

[0040] A feature that is “connected” or “coupled” to or “connected to” or “coupled to” another feature may be directly connected or coupled to or connected to or coupled to the other feature, or one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or “directly connected to” or “directly coupled to” another feature if there are no intervening features. A feature may be “indirectly connected” or “indirectly coupled” to or “indirectly connected to” or “indirectly coupled to” another feature if there are at least one intervening feature. A feature that is “on” or “contacting” another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be “directly on” or “directly in contact with” another feature if there are no intervening features. A feature may be “indirectly on” or “indirectly in contact with” another feature if there are at least one intervening feature.

[0041] The description of various embodiments of the present disclosure is given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, the practical application or technical improvement of the technology found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A differential power amplifier circuit, comprising: a first differential power amplifier including first and second cross-coupled neutralization capacitors; as well as The second differential power amplifier is coupled in parallel with the first differential power amplifier and includes a plurality of multi-gate transistors.

2. The differential power amplifier circuit according to claim 1, wherein: The multi-gate transistor includes a double-gate transistor.

3. The differential power amplifier circuit according to claim 1, wherein: The first differential power amplifier comprises: Input stage; output stage; and First and second parallel branches are connected between the input stage and the output stage, wherein each of the first and second parallel branches comprises a driver transistor and a power transistor connected in series between the input stage and the output stage, wherein a gate of the driver transistor is connected to the input stage, and wherein the gate of the power transistor is connected to a bias voltage.

4. The differential power amplifier circuit according to claim 3, wherein: The first cross-coupling neutralizing capacitor is coupled between the gate of the drive transistor in the first parallel branch and a node between the drive transistor and the power transistor in the second parallel branch, and wherein the second cross-coupling neutralizing capacitor is coupled between the gate of the drive transistor in the second parallel branch and a node between the drive transistor and the power transistor in the first parallel branch.

5. The differential power amplifier circuit according to claim 3, wherein: The input stage comprises: Input nodes; and An input transformer comprising two magnetically coupled input windings, wherein one of the input windings is connected between the input node and either ground or the other input node, and wherein the other of the input windings is connected at opposite ends to the gates of the drive transistors in the first and second parallel branches, respectively.

6. The differential power amplifier circuit according to claim 3, wherein: The second differential power amplifier comprises: first and second parallel branches, wherein each of the first and second branches of the second differential power amplifier comprises a multi-gate transistor, wherein a first gate of the multi-gate transistor is connected to the input stage of the first differential power transistor, and wherein a second gate of the multi-gate transistor is connected to the bias voltage.

7. The differential power amplifier circuit according to claim 6, wherein: The multi-gate transistor in the first parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the first parallel branch of the first differential power amplifier and the output stage, and wherein the multi-gate transistor in the second parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the second parallel branch of the first differential power amplifier and the output stage.

8. The differential power amplifier circuit according to claim 6, wherein: The differential power amplifier circuit is implemented using a plurality of X power cells.

9. The differential power amplifier circuit according to claim 8, wherein: Each drive transistor and each power transistor in the first differential power amplifier is implemented using 1 power primitive, and wherein each dual-gate transistor in the second differential power amplifier is implemented using (X-4) / 4 combined power primitives.

10. The differential power amplifier circuit according to claim 8, wherein: Each driving transistor in the first differential power amplifier is implemented using 1 power cell, each power transistor in the first differential power amplifier is implemented using 3 power cells, and each dual-gate transistor in the second differential power amplifier is implemented using (X-8) / 4 combined power cells.

11. A differential power amplifier circuit, comprising: a first differential power amplifier comprising first and second parallel branches, wherein the first differential power amplifier comprises first and second neutralizing capacitors cross-coupled between the first and second parallel branches; and A second multi-gate differential power amplifier comprises first and second parallel branches, wherein the first and second parallel branches of the second differential power amplifier are coupled to the first and second parallel branches of the first differential power amplifier, respectively.

12. The differential power amplifier circuit according to claim 11, wherein: The first differential power amplifier comprises: input stage; and Output stage; wherein the first and second parallel branches are connected between the input stage and the output stage, wherein each of the first and second parallel branches comprises a drive transistor and a power transistor connected in series between the input stage and the output stage, wherein the gate of the drive transistor is connected to the input stage, and wherein the gate of the power transistor is connected to a bias voltage.

13. The differential power amplifier circuit according to claim 11, wherein: The first cross-coupling neutralizing capacitor is coupled between the gate of the drive transistor in the first parallel branch and a node between the drive transistor and the power transistor in the second parallel branch, and wherein the second cross-coupling neutralizing capacitor is coupled between the gate of the drive transistor in the second parallel branch and a node between the drive transistor and the power transistor in the first parallel branch.

14. The differential power amplifier circuit according to claim 11, wherein: The input stage comprises: Input nodes; and An input transformer comprising two magnetically coupled input windings, wherein one of the input windings is connected between the input node and either ground or the other input node, and wherein the other of the input windings is connected at opposite ends to the gates of the drive transistors in the first and second parallel branches, respectively.

15. The differential power amplifier circuit according to claim 11, wherein: Each of the first and second parallel branches of the second multi-gate differential power amplifier comprises a multi-gate transistor, wherein a first gate of the multi-gate transistor is connected to the input stage of the first differential power transistor, and wherein a second gate of the multi-gate transistor is connected to the bias voltage.

16. The differential power amplifier circuit according to claim 15, wherein: The multi-gate transistor in the first parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the first parallel branch of the first differential power amplifier and the output stage, and wherein the multi-gate transistor in the second parallel branch of the second differential power amplifier is connected between ground and a node between the power transistor in the second parallel branch of the first differential power amplifier and the output stage.

17. The differential power amplifier circuit according to claim 15, wherein: The differential power amplifier circuit is implemented using a plurality of X power cells.

18. The differential power amplifier circuit according to claim 17, wherein: Each drive transistor and each power transistor in the first differential power amplifier is implemented using 1 power primitive, and wherein each dual-gate transistor in the second differential power amplifier is implemented using (X-4) / 4 combined power primitives.

19. The differential power amplifier circuit according to claim 15, wherein: Each driving transistor in the first differential power amplifier is implemented using 1 power cell, each power transistor in the first differential power amplifier is implemented using 3 power cells, and each dual-gate transistor in the second differential power amplifier is implemented using (X-8) / 4 combined power cells.

20. A radio frequency (RF) differential power amplifier circuit, comprising: an RF input stage for receiving an RF input signal; a first differential power amplifier comprising first and second shunt branches coupled to the RF input stage, wherein the first differential power amplifier comprises first and second neutralizing capacitors cross-coupled between the first and second shunt branches; a second multi-gate differential power amplifier comprising first and second parallel branches coupled to the RF input stage, wherein the first and second parallel branches of the second differential power amplifier are coupled to the first and second parallel branches of the first differential power amplifier, respectively; and An RF output stage is coupled to the first and second differential power amplifiers for outputting an amplified RF signal.

Images