Low-noise circuit for supplying power to operational transconductance amplifier OTA

Abstract

The invention relates to a low-noise circuit for supplying power to an operational transconductance amplifier OTA. The circuit comprises a first switched capacitor circuit and a second switched capacitor circuit, the first switched capacitor circuit and the second switched capacitor circuit respectively comprise at least four switches and at least one capacitor; wherein when the connection between the capacitor and the OTA is conducted, the capacitor is used for supplying power to the OTA; when the connection between the capacitor and the OTA is disconnected, the capacitor is in a charging state; each switch is switched on or switched off in response to a clock signal so as to control the on-off of the connection between the corresponding capacitor and the OTA; according to the circuit provided by the invention, the problem of noise caused by using a traditional MOSFET current source to supply power to the OTA can be avoided, a low-noise power supply circuit is realized, and power consumption can be saved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a low-noise circuit for powering an operational transconductance amplifier (OTA). Background Art

[0002] Currently, a method for powering an operational transconductance amplifier (OTA) is to use a metal-oxide-semiconductor field-effect transistor (MOSFET) current source for powering. Figure 1 Figure 1 shows a schematic diagram of a traditional high-gain, high-linearity, high-energy-efficiency OTA, where: Figure 1 A in FIG shows a method of using a complementary metal oxide semiconductor (CMOS) process to achieve high gain, high linearity, and high energy efficiency OTA. In order to save voltage headroom, the bias current (i.e. Figure 1 The A in the I B ) does not flow through the resistor R used for source degeneration d If a conventional MOSFET current source is used to bias the OTA (e.g. Figure 1 As shown in B in the figure, since this type of current source (i.e. Figure 1 The noise of Mb1, Mb2, Mb3 and Mb4 in B is non-common mode noise. This type of current source noise will deteriorate the input equivalent noise of the OTA. Under the premise of keeping the bias current unchanged, it is necessary to reduce the current source noise of this type. Figure 1 The ratio of the transconductance of Mb1-Mb4 in B to the drain current (i.e. g m / I d ), resulting in Mb1-Mb4 needing to occupy a higher voltage margin, which in turn causes the OTA to require a higher supply voltage and thus leads to higher power consumption. Summary of the Invention

[0003] In view of this, the present application proposes a low-noise circuit for powering an operational transconductance amplifier OTA, which can avoid the noise problem introduced by using a traditional MOSFET current source for power supply, realize a low-noise power supply circuit, and save power consumption.

[0004] According to one aspect of the present application, a circuit for powering an operational transconductance amplifier (OTA) is provided, comprising: a first switched capacitor circuit and a second switched capacitor circuit; the first switched capacitor circuit and the second switched capacitor circuit respectively comprise at least four switches and at least one capacitor; wherein, when the connection between the capacitor and the OTA is turned on, the capacitor is used to power the OTA; when the connection between the capacitor and the OTA is turned off, the capacitor is in a charging state; each of the switches is closed or opened in response to a clock signal to control the on / off connection between the corresponding capacitor and the OTA.

[0005] In a possible implementation, the first switch capacitor circuit includes a first capacitor, a first switch, a second switch, a third switch, and a fourth switch; the second switch capacitor circuit includes a second capacitor, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; the first end of the first switch, the first end of the third switch, the first end of the fifth switch, and the first end of the seventh switch are respectively connected to the OTA; the second end of the first switch and the first end of the second switch are connected to the first end of the first capacitor; the second end of the third switch and the first end of the fourth switch are connected to the second end of the first capacitor; the second end of the fifth switch and the first end of the sixth switch are connected to the first end of the second capacitor; the second end of the seventh switch and the first end of the eighth switch are connected to the second end of the second capacitor; the second end of the second switch and the second end of the sixth switch are connected to a first voltage; the second end of the fourth switch and the second end of the eighth switch are connected to a second voltage; The first switch and the seventh switch are closed in response to a first level in the first clock signal and are opened in response to a second level in the first clock signal; the second switch, the fourth switch, the sixth switch and the eighth switch are closed in response to the first level in the second clock signal and are opened in response to the second level in the second clock signal; wherein the first clock signal and the second clock signal have the same clock period and opposite levels; when the first switch, the third switch, the fifth switch and the seventh switch are closed in response to the first clock signal, the second switch, the fourth switch, the sixth switch and the eighth switch are opened in response to the second clock signal, and the first capacitor and the second capacitor are used to power the OTA; when the second switch, the fourth switch, the sixth switch and the eighth switch are closed in response to the second clock signal, the first switch, the third switch, the fifth switch and the seventh switch are opened in response to the first clock signal, and the first capacitor and the second capacitor are in a charging state.

[0006] In a possible implementation, the first switch capacitor circuit further includes a third capacitor, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch; the second switch capacitor circuit further includes a fourth capacitor, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; the first end of the ninth switch is connected to the first end of the first switch; the first end of the eleventh switch is connected to the first end of the third switch; the first end of the thirteenth switch is connected to the first end of the fifth switch; the first end of the fifteenth switch is connected to the first end of the seventh switch; the second end of the ninth switch and the first end of the tenth switch are connected to the first end of the third capacitor; the second end of the eleventh switch and the first end of the twelfth switch are connected to the second end of the third capacitor; the second end of the thirteenth switch and the first end of the fourteenth switch are connected to the first end of the fourth capacitor; the second end of the fifteenth switch and the first end of the sixteenth switch are connected to the second end of the fourth capacitor; the second end of the tenth switch and the second end of the fourteenth switch are connected to the first voltage; the second end of the twelfth switch and the first end of the fourth switch are connected to the first voltage. Second terminals of the sixteen switches are connected to the second voltage; the tenth switch, the twelfth switch, the fourteenth switch, and the sixteenth switch are closed in response to the first level in the first clock signal and opened in response to the second level in the first clock signal; the ninth switch, the eleventh switch, the thirteenth switch, and the fifteenth switch are closed in response to the first level in the second clock signal and opened in response to the second level in the second clock signal; wherein, when the tenth switch, the twelfth switch, the fourteenth switch, and the sixteenth switch are closed in response to the first clock signal, the ninth switch, the eleventh switch, the thirteenth switch, and the fifteenth switch are opened in response to the second clock signal, and the third capacitor and the fourth capacitor are in a charging state; when the ninth switch, the eleventh switch, the thirteenth switch, and the fifteenth switch are closed in response to the second clock signal, the tenth switch, the twelfth switch, the fourteenth switch, and the sixteenth switch are opened in response to the first clock signal, and the third capacitor and the fourth capacitor are used to power the OTA.

[0007] In a possible implementation, the OTA includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor; the gate of the first PMOS transistor and the gate of the second NMOS transistor are connected to form a first input end of the OTA; the gate of the third PMOS transistor and the gate of the fourth NMOS transistor are connected to form a second input end of the OTA; the source of the first PMOS transistor, the first end of the first resistor, and the first end of the first switch are connected; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, forming a first output end of the OTA; the first NMOS transistor The source of the second NMOS transistor is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor and the first end of the second resistor are connected to the first end of the third switch; the source of the third PMOS transistor and the second end of the first resistor are connected to the first end of the fifth switch; the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor, forming a second output end of the OTA; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor and the second end of the second resistor are connected to the first end of the seventh switch; the gate of the second PMOS transistor and the gate of the fourth PMOS transistor are connected to a first gate voltage; the gate of the first NMOS transistor and the gate of the third NMOS transistor are connected to a second gate voltage.

[0008] In one possible implementation, the circuit further includes a fifth capacitor and a sixth capacitor; a first end of the fifth capacitor is connected to the source of the first PMOS transistor; a second end of the fifth capacitor is connected to the source of the second NMOS transistor; a first end of the sixth capacitor is connected to the source of the third PMOS transistor; and a second end of the sixth capacitor is connected to the source of the fourth NMOS transistor.

[0009] In a possible implementation, the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are equal.

[0010] In a possible implementation, the duty cycle of the first clock signal and the second clock signal is 50%; the capacitance values ​​C of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are 50%. S =0.5T S I B / (V top -V bottom ); where TS I represents the clock period of the first clock signal and the second clock signal; B Indicates the bias current required for the normal operation of the OTA; V top represents the source voltage of the first PMOS tube; V bottom represents the source voltage of the second NMOS tube; V top -V bottom The value of is equal to the sum of the absolute values ​​of the drain-source voltages of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

[0011] In a possible implementation, the first capacitor includes N capacitors with a capacitance value of N·C S The first sub-capacitor; N ≥ 2; when the first capacitor is in a charging state, N first sub-capacitors are connected in parallel; when the first capacitor is used to power the OTA, N first sub-capacitors are connected in series; the second capacitor includes N capacitance values ​​of N·C S When the second capacitor is in a charging state, N second sub-capacitors are connected in parallel; when the second capacitor is used to power the OTA, N second sub-capacitors are connected in series; the third capacitor includes N capacitance values ​​of N·C S When the third capacitor is in a charging state, N of the third sub-capacitors are connected in parallel; when the third capacitor is used to power the OTA, N of the third sub-capacitors are connected in series; the fourth capacitor includes N capacitance values ​​of N·C S when the fourth capacitor is in a charging state, N of the fourth sub-capacitors are connected in parallel; when the fourth capacitor is used to power the OTA, N of the fourth sub-capacitors are connected in series.

[0012] In a possible implementation, the first voltage and the second voltage satisfy: V L +(V H -V L ) / 2=V bottom +(V top -V bottom ) / 2 and N·(V H -V L )=2·(V top -V bottom ); where V H represents the first voltage; V L represents the second voltage.

[0013] In one possible implementation, the circuit further includes: a fifth PMOS transistor, a sixth PMOS transistor, and a first operational amplifier; the first input terminal of the first operational amplifier inputs the output common-mode voltage of the OTA; the second input terminal of the first operational amplifier inputs a reference common-mode voltage; the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor are connected to the output terminal of the first operational amplifier; the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to a third voltage; the drain of the fifth PMOS transistor is connected to the source of the first PMOS transistor; and the drain of the sixth PMOS transistor is connected to the source of the third PMOS transistor; wherein the output common-mode voltage is a sum of a first output voltage output from the first output terminal of the OTA and a second output voltage output from the second output terminal of the OTA divided by 2.

[0014] The circuit for powering OTA in the present application uses a switching capacitor instead of a traditional MOSFET current source to power OTA, which can avoid the non-common-mode noise introduced by the use of a traditional MOSFET current source, realize a low-noise power supply circuit, and save power consumption.

[0015] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the description, serve to explain the principles of the application.

[0017] Figure 1 Schematic diagram showing a traditional high-gain, high-linearity, and high-energy-efficiency OTA.

[0018] Figure 2 A schematic structural diagram of a low-noise circuit for powering OTA according to an embodiment of the present application is shown.

[0019] Figure 3 A schematic diagram illustrating a first clock signal and a second clock signal according to an embodiment of the present application is shown.

[0020] Figure 4 A schematic structural diagram of a low-noise circuit for powering OTA according to an embodiment of the present application is shown.

[0021] Figure 5 A schematic structural diagram of a low-noise circuit for powering OTA according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0023] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0024] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0025] Figure 2 FIG. 1 shows a schematic diagram of a circuit for powering an OTA with low noise according to an embodiment of the present application. Figure 2 As shown, the circuit includes a first switched capacitor circuit and a second switched capacitor circuit; the first switched capacitor circuit and the second switched capacitor circuit respectively include at least four switches and at least one capacitor; wherein, when the connection between the capacitor and the OTA is turned on, the capacitor is used to power the OTA; when the connection between the capacitor and the OTA is turned off, the capacitor is in a charging state; each of the switches is closed or opened in response to a clock signal to control the on / off connection between the corresponding capacitor and the OTA.

[0026] In a possible implementation, the first switched capacitor circuit includes a first capacitor C s,a1 , first switch S 1a , the second switch S 2a , the third switch S 3a and the fourth switch S 4a The second switched capacitor circuit includes a second capacitor C s,a2 , the fifth switch S 1b , the sixth switch S 2b , the seventh switch S 3b and the eighth switch S 4b .

[0027] Among them, S 1a The first end, S 3a The first end, S 1b The first end, S 3b The first end of S is connected to the OTA respectively; 1a The second end, S 2a The first end and C s,a1The first end (i.e. C s,a1 The upper plate) is connected; S 3a The second end, S 4a The first end and C s,a1 The second end (i.e. C s,a1 The lower plate) is connected; S 1b The second end, S 2b The first end and C s,a2 The first end (i.e. C s,a2 The upper plate of the 3b The second end, S 4b The first end and C s,a2 The second end (i.e. C s,a2 The lower plate) is connected; S 2a The second end and S 2b The second terminal is connected to the first voltage V H ;S 4a The second end and S 4b The second terminal is connected to the second voltage V L .

[0028] For example, S 1a 、S 3a 、S 1b and S 3b Closed in response to the first level of the first clock signal Φ1, and opened in response to the second level of Φ1; S 2a 、S 4a 、S 2b and S 4b The first level in response to the second clock signal Φ2 is closed, and the second level in response to the second level in Φ2 is opened. As an example, the first level can be a high level and the second level can be a low level, that is, S 1a 、S 3a 、S 1b and S 3b It can be closed when Φ1 is high and opened when Φ1 is low; S 2a 、S 4a 、S 2b and S 4b It can be closed when Φ2 is high and opened when Φ2 is low.

[0029] Figure 3 A schematic diagram showing a first clock signal and a second clock signal according to an embodiment of the present application is shown in FIG. Figure 3 As shown, the clock periods of Φ1 and Φ2 are the same, but the levels are opposite. Ideally, the duty cycle of Φ1 and Φ2 can be set to 50%, but since the rise time and fall time of the actual clock generation circuit are not zero, and Φ1 and Φ2 need to be non-overlapping, the duty cycle of Φ1 and Φ2 is less than 50% in practice. The clock period of Φ1 and Φ2 can be recorded as TS .

[0030] The circuit of the embodiment of the present application can be used for Figure 1 The high-gain, high-linearity, and high-energy-efficiency OTA shown in A is used for power supply. Figure 2 The switched capacitor circuit in is equivalent to a switched-capacitor power supply (Switched-CapacitorSupply). Figure 2 As shown, the OTA may include a first PMOS transistor M 1,a , the second PMOS tube M 2,a , the third PMOS tube M 1,b , the fourth PMOS tube M 2,b , the first NMOS tube M 3,a , the second NMOS tube M 4,a , the third NMOS tube M 3,b , the fourth NMOS tube M 4,b , the first resistor R d1 and the second resistor R d2 . M 1,a and M 1,b Can be the same, M 2,a and M 2,b Can be the same, M 3,a and M 3,b Can be the same, M 4,a and M 4,b Can be the same.

[0031] Among them, M 1,a The gate and M 4,a The gate of the OTA is connected to form the first input terminal, and the input voltage of the first input terminal is V i+ ;M 1,b The gate and M 4,b The gate of the OTA is connected to form the second input terminal of the OTA. The input voltage of the second input terminal is V i- ;M 1,a The source, R d1 The first end and S 1a The first end of the connection is connected, and the connection point is marked as S M1 ;M 1,a The drain and M 2,a Source connection of M 2,a The drain and M 3,a The drain of the OTA is connected to form the first output terminal, and the output voltage of the first output terminal is V O- ;M 3,a The source and M 4,a Drain connection; M 4,a The source, R d2 The first end and S 3a The first end of the connection is connected, and the connection point is marked as SM4 ;M 1,b The source, R d1 The second end and S 1b The first end of the connection is connected, and the connection point is marked as S M2 ;M 1,b The drain and M 2,b Source connection of M 2,b The drain and M 3,b The drain of the OTA is connected to form the second output terminal of the OTA. The output voltage of the second output terminal is V O+ ;M 3,b The source and M 4,b Drain connection; M 4,b The source, R d2 The second end and S 3b The first end of the connection is connected, and the connection point is marked as S M3 ;M 2,a The gate and M 2,b The gate is connected to the first gate voltage V bcasp ;M 3,a The gate and M 3,b The gate is connected to the second gate voltage V bcasn The OTA output differential mode voltage V O =V O+ -V O- , output common mode voltage V O,cm =(V O+ +V O- ) / 2. The circuit structure of the OTA is similar to Figure 1 The circuit structure of the OTA shown in A is the same.

[0032] In one embodiment, when Φ1 is high and Φ2 is low, S 1a 、S 3a 、S 1b and S 3b Closed, S 2a 、S 4a 、S 2b and S 4b Disconnect, then C s,a1 and C s,a2 The connection between OTA is on, C s,a1 and C s,a2 Charge can be injected into OTA to power OTA; when Φ2 is high and Φ1 is low, S 2a 、S 4a 、S 2b and S 4b Closed, S 1a 、S 3a 、S 1b and S 3b Disconnect, then Cs,a1 and C s,a2 The connection with OTA is disconnected, C s,a1 and C s,a2 Connect both ends of V H and V L , C s,a1 and C s,a2 In charging state.

[0033] When the first switched capacitor circuit and the second switched capacitor circuit each include four switches and one capacitor, it is impossible to continuously power the OTA. Four switches and one capacitor can be added to the first switched capacitor circuit and the second switched capacitor circuit respectively to continuously power the OTA.

[0034] Figure 4 FIG. 1 shows a schematic diagram of a circuit for powering an OTA with low noise according to an embodiment of the present application. Figure 4 As shown, the circuit includes a first switched capacitor circuit and a second switched capacitor circuit, the first switched capacitor circuit including C s,a1 、S 1a 、S 2a 、S 3a and S 4a The second switched capacitor circuit includes C s,a2 、S 1b 、S 2b 、S 3b and S 4b ; C s,a1 、C s,a2 、S 1a 、S 2a 、S 3a 、S 4a 、S 1b 、S 2b 、S 3b and S 4b The connection method and Figure 3 The first switched capacitor circuit also includes a third capacitor C s,b1 , the ninth switch S 5a , the tenth switch S 6a , eleventh switch S 7a and the twelfth switch S 8a The second switched capacitor circuit also includes a fourth capacitor C s,b2 , 13th switch S 5b , fourteenth switch S 6b , the fifteenth switch S 7b and the sixteenth switch S 8b .

[0035] Among them, S 5a The first end and S1a The first end of the connection; S 7a The first end and S 3a The first end of the connection; S 5b The first end and S 1b The first end of the connection; S 7b The first end and S 3b The first end of the connection; S 5a The second end, S 6a The first end and C s,b1 The first end (i.e. C s,b1 The upper plate of the 7a The second end, S 8a The first end and C s,b1 The second end (i.e. C s,b1 The lower plate) is connected; S 5b The second end, S 6b The first end and C s,b2 The first end (i.e. C s,b2 The upper plate of the 7b The second end, S 8b The first end and C s,b2 The second end (i.e. C s,b2 The lower plate) is connected; S 6a The second end and S 6b The second terminal is connected to V H ;S 8a The second end and S 8b The second terminal is connected to V L .

[0036] For example, S 6a 、S 8a 、S 6b and S 8b Closed in response to the first level in Φ1, opened in response to the second level in Φ1; S 5a 、S 7a 、S 5b and S 7b In response to the first level in Φ2, the switch is closed, and in response to the second level in Φ2, the switch is opened. As an example, the first level may be a high level, and the second level may be a low level, i.e., S 6a 、S 8a 、S 6b and S 8b It can be closed when Φ1 is high and opened when Φ1 is low; S 5a 、S 7a 、S 5b and S 7b It can be closed when Φ2 is high and opened when Φ2 is low.

[0037] For example, Cs,a1 、C s,a2 、C s,b1 、C s,b2 The capacitance values ​​are equal. C s,a1 、C s,a2 、C s,b1 、C s,b2 It can be called a switched capacitor.

[0038] In one embodiment, to ensure that the input MOSFETs (ie, M 1,a 、M 1,b 、M 4,a 、M 4,b ) remains unchanged, the switched capacitor can power the OTA in a ping-pong manner, that is, when Φ1 is high and Φ2 is low, S 1a 、S 3a 、S 6a 、S 8a 、S 1b 、S 3b 、S 6b and S 8b Closed, S 2a 、S 4a 、S 5a 、S 7a 、S 2b 、S 4b 、S 5b and S 7b Disconnect, then C s,a1 and C s,a2 The connection between OTA is on, C s,a1 and C s,a2 The charge is injected into the OTA to power the OTA. At the same time, C s,b1 and C s,b2 Connect both ends of V H and V L , C s,b1 and C s,b2 is charged; when Φ2 is high and Φ1 is low, S 2a 、S 4a 、S 5a 、S 7a 、S 2b 、S 4b 、S 5b and S 7b Closed, S 1a 、S 3a 、S 6a 、S 8a 、S 1b 、S 3b 、S 6b and S 8b Disconnect, then Cs,b1 and C s,b2 The connection between OTA is on, C s,b1 and C s,b2 The charge is injected into the OTA to power the OTA. At the same time, C s,a1 and C s,a2 Connect both ends of V H and V L , C s,a1 and C s,a2 In this way, the circuit of the embodiment of the present application can realize continuous power supply for OTA.

[0039] When powering OTA, C s,a1 / C s,a2 / C s,b1 / C s,b2 The amount of charge injected into the OTA each time should be equal to half a clock cycle (i.e. 0.5T S ) flows through the OTA, C s,a1 、C s,a2 、C s,b1 、C s,b2 The capacitance value is recorded as C S , then C S ·(V H -V L )=0.5T S I B , and V H -V L =V top -V bottom , then C can be calculated according to the following formula S Value:

[0040] C S =0.5T S I B / (V top -V bottom ) (1)

[0041] Among them, T S Indicates the clock period of Φ1 and Φ2; I B Indicates the bias current required for OTA to operate normally. 1,a and M 1,b Same, M 2,a and M 2,b Same, M 3,a and M 3,b Same, M 4,a and M 4,b Under the same conditions, V top Indicates M 1,a The source voltage and M 1,b The source voltage (i.e. node SM1 The voltage at node S M2 voltage at the bottom Indicates M 4,a The source voltage and M 4,b The source voltage (i.e. node S M3 The voltage at node S M4 voltage at the top -V bottom The value is equal to M 1,a 、M 2,a 、M 3,a 、M 4,a The drain-source voltage (V ds ) is the sum of the absolute values ​​of V top and V bottom The value can be adjusted based on the required OTA output common mode voltage and M 1,a 、M 2,a 、M 3,a 、M 4,a The drain-source voltage is set.

[0042] At the moment of switching between the closed state and the open state, V top and V bottom May produce instantaneous peaks. In order to prevent M 1,a 、M 1,b 、M 4,a 、M 4,b The source end (i.e. node S M1 、S M2 、S M3 、S M4 ) to see a large glitch, you can M1 、S M4 Between and node S M2 、S M3 A relatively large capacitor is additionally connected between them.

[0043] like Figure 4 As shown, the circuit of the embodiment of the present application further includes a fifth capacitor C b1 and the sixth capacitor C b2 ; C b1 The first end (i.e. C b1 The upper plate) and M 1,a Source connection; C b1 The second end (i.e. C b1 The lower plate) and M 4,a Source connection; C b2 The first end (i.e. C b2 The upper plate) and M 1,b Source connection; C b2 The second end (i.e. Cb2 The lower plate) and M 4,b Theoretically, C b1 and C b2 The larger the capacitance value, the better the glitch attenuation effect. However, since the equivalent transconductance of the OTA is source degenerated, the glitch “seen” by the OTA due to the switching operation is also attenuated due to source degeneration. Therefore, C b1 and C b2 The capacitance value can be relatively large but does not need to be very large.

[0044] In order to stabilize the output common-mode voltage of the OTA at a desired output common-mode voltage, a common-mode feedback circuit (CMFB) may be used.

[0045] like Figure 4 As shown, the circuit of the embodiment of the present application may further include a fifth PMOS transistor M P1 , the sixth PMOS tube M P2 and the first operational amplifier OP,M P1 and M P2 The first input terminal of OP inputs the output common mode voltage V of OTA. O,cm , V O,cm =(V O+ +V O- ) / 2; the second input terminal of OP inputs the reference common mode voltage V O,cm,ref , V O,cm,ref That is, the required output common mode voltage, which is determined according to actual needs; M P1 Gate, M P2 The gate of M is connected to the output terminal of OP; P1 The source and M P2 The source of the third voltage V DD , V DD The value of M P1 and M P2 V ds OK; M P1 The drain and M 1,a Source connection of M P2 The drain and M 1,b Source connection of M P1 、M P2 and OP form a CMFB circuit, and the output voltage of OP is equal to V O,cm With V O,cm,ref The difference is multiplied by the magnification factor, M P1 and M P2 Equivalent to two current sources, the current I generated by these two current sources CMFBControlled by the output voltage of OP, the OTA output V can be O,cm Stable at the required V O,cm,ref .

[0046] When C s,a1 / C s,a2 / C s,b1 / C s,b2 When the connection between the two ends of the OTA is disconnected, a part of the charge will be taken away, which is half of the charge at the moment before the connection is disconnected. In order to compensate for the charge taken away, a s,a1 / C s,a2 / C s,b1 / C s,b2 When in charging state, charge it to 2(V top -V bottom ), then every time two of the four switch capacitors are connected to the OTA, twice the charge required by the OTA will be injected into the OTA, of which 1 / 2 of the charge will be taken away by the other two switch capacitors that are disconnected from the OTA at the same time, and the remaining 1 / 2 of the charge will be injected into the OTA to provide it with bias current, thereby ensuring that the OTA is injected with the required charge in real time. However, in advanced CMOS processes, 2(V top -V bottom ) generally exceeds the normal supply voltage of the core transistor. In order to avoid the required charging voltage of the switch capacitor exceeding the normal supply voltage of the core transistor, capacitor stacking can be used to obtain 2 (V top -V bottom ) voltage, namely C s,a1 、C s,a2 、C s,b1 、C s,b2 The N capacitance values ​​can be N·C S The sub-capacitors are connected in series.

[0047] In one possible implementation, C s,a1 Including N capacitors with a value of N·C S The first sub-capacitance; N ≥ 2; C s,a1 When in the charging state, N of the first sub-capacitors are connected in parallel; C s,a1 When used to power OTA, N first sub-capacitors are connected in series; C s,a2 Including N capacitors with a value of N·C S The second sub-capacitance; C s,a2 When in the charging state, N second sub-capacitors are connected in parallel; C s,a2 When used to power OTA, N second sub-capacitors are connected in series; C s,b1Including N capacitors with a value of N·C S The third sub-capacitor; C s,b1 When in the charging state, N third sub-capacitors are connected in parallel; C s,b1 When used to power OTA, N third sub-capacitors are connected in series; C s,b2 Including N capacitors with a value of N·C S The fourth sub-capacitor; C s,b2 When in the charging state, N fourth sub-capacitors are connected in parallel; C s,b2 When used to power an OTA, N fourth sub-capacitors are connected in series.

[0048] During the charging period of the switched capacitor, only N parallel capacitors with a capacitance value of N·C are needed. S The sub-capacitor is charged to 2(V top -V bottom ) / N, that is, V H and V L The selection needs to satisfy the constraints:

[0049] N·(V H -V L )=2·(V top -V bottom ) (2)

[0050] When the switched capacitor is used to power the OTA, the N capacitors are set to N·C S The sub-capacitors are connected in series to obtain a voltage drop of 2(V top -V bottom ), the capacitance value is C S The equivalent capacitor is used to inject charge into the OTA for power supply. At the same time, in order to ensure the voltage drop of 2 (V top -V bottom ) is equal to the intermediate potential V required by OTA bottom +(V top -V bottom ) / 2,V H and V L The selection of also needs to meet the constraints:

[0051] V L +(V H -V L ) / 2=V bottom +(V top -V bottom ) / twenty three)

[0052] Thus, in V H and V LUnder the premise that the core supply voltage of the transistor does not exceed 100%, when the equivalent capacitor is used to power the OTA, a charge twice the amount required by the OTA will appear at the node S. M1 、S M4 and node S M2 、S M3 At this point, 1 / 2 of the charge will be taken away by the equivalent capacitor that is disconnected from the OTA at the same time, and the remaining 1 / 2 of the charge will be injected into the OTA to generate a current I B Bias the OTA.

[0053] Preferably, the value of N can be 3. Since a larger N value requires more switches in the circuit and a more complex switch control circuit, a smaller N value is better. However, when N=2, a negative voltage may be required to obtain the required intermediate potential. To avoid the use of negative voltage and simplify the switch control circuit as much as possible, N=3 is the preferred value.

[0054] Figure 5 FIG. 1 shows a schematic diagram of a circuit for powering an OTA with low noise according to an embodiment of the present application. Figure 5 As shown, C s,a1 、C s,a2 、C s,b1 、C s,b2 It can be divided into three capacitors with a value of 3C. S The sub-capacitor is realized. Figure 5 The light yellow portion of the first switched capacitor circuit shows the use of three capacitors with a value of 3C. S The sub-capacitor realizes C s,a1 The circuit structure diagram, the light yellow part corresponding to the second switched capacitor circuit shows the use of 3 capacitors with a value of 3C S The sub-capacitor realizes C s,a2 Schematic diagram of the circuit structure. As shown in the light yellow part, the closing and opening of the green switch is controlled by Φ1. The green switch can be closed when Φ1 is high and opened when Φ1 is low. The closing and opening of the yellow switch is controlled by Φ2. The yellow switch can be closed when Φ2 is high and opened when Φ2 is low. Figure 5 The light blue part corresponding to the first switched capacitor circuit and the light blue part corresponding to the second switched capacitor circuit respectively indicate the use of three capacitors with a value of 3C. S The sub-capacitor realizes C s,b1 and C s,b2 Schematic diagram of the circuit structure. The circuit structure of the light blue part is the same as the circuit structure of the light yellow part ( Figure 5The circuit structure of the light blue portion is not shown in the figure; the circuit structure of the light yellow portion can be referred to. The difference is that the yellow switch in the light blue portion is controlled by Φ1, and the green switch is controlled by Φ2. The yellow switch in the light blue portion can be closed when Φ1 is high and opened when Φ1 is low; the green switch can be closed when Φ2 is high and opened when Φ2 is low.

[0055] When Φ1 is high and Φ2 is low, the green switch in the light yellow part is closed and the yellow switch is open; the yellow switch in the light blue part is closed and the green switch is open; in the light yellow part, the three capacitors have a value of 3C. S The sub-capacitors are connected in series to form a voltage drop of 2(V top -V bottom ), the capacitance value is C S The equivalent capacitor of the OTA is connected to the two ends of the equivalent capacitor to inject charge into the OTA for power supply; in the light blue part, the three capacitors have a value of 3C S The sub-capacitors are connected in parallel, and the two ends of the sub-capacitors are connected to V H and V L , each sub-capacitor will be charged to V H -V L , that is, charged to 2(V top -V bottom ) / 3. When Φ1 is low and Φ2 is high, the yellow switch in the light yellow part is closed and the green switch is open; the green switch in the light blue part is closed and the yellow switch is open; in the light yellow part, the three capacitors have a value of 3C S The sub-capacitors are connected in parallel, and each sub-capacitor will be charged to 2 (V top -V bottom ) / 3; in the light blue part, the three capacitors have a value of 3C S The sub-capacitors are connected in series to form a voltage drop of 2(V top -V bottom ), the capacitance value is C S The equivalent capacitance of 3C is used to inject charge into OTA for power supply. S The sub-capacitors are stacked to realize the switched capacitor, which can be selected at V H and V L Under the premise that the core supply voltage of the transistor does not exceed the core supply voltage of the transistor, the required charge is injected into the OTA in real time, and the voltage drop of 2 (V top -V bottom ) is equal to the intermediate potential required by OTA, while avoiding the use of negative voltage.

[0056] Figure 5The purple circuit in the middle is a CMFB circuit that uses two real-time output common-mode voltages V controlled by OTA. O,cm and the desired output common-mode voltage V O,cm,ref The difference between the current source and an operational amplifier can be realized to convert the OTA output V O,cm Stable at the required V O,cm,ref These two current sources can be implemented using MOSFETs, for example, PMOS tubes (such as Figure 4 Through M P1 and M P2 The current I generated by these two current sources is CMFB The value can be much smaller than I B , for example, it can be I B One tenth or less of these two current sources will contribute noise to the OTA, but because of their low current, the corresponding current noise is 4kTγg m (k represents the Boltzmann constant, T represents the absolute temperature, γ represents the parameter related to the MOSFET manufacturing process, g m denoting the transconductance) is also low, so the noise contribution of these two current sources to the OTA can be neglected in a suitable design.

[0057] The circuit of the embodiment of the present application uses a switched capacitor to power the OTA, which can avoid the non-common-mode noise from the conventional non-common-mode tail current source (i.e., the traditional MOSFET current source). On the technical level, the circuit of the embodiment of the present application mainly has the advantage of saving power consumption. If a conventional non-common-mode tail current source is used for power supply, under the premise that the bias current of the OTA remains unchanged, the noise of such a current source needs to be reduced. m / I d values, so that these transistors require a higher drain-source voltage V ds , which requires increasing the OTA's supply voltage or compressing the OTA's output swing. A higher supply voltage means higher power consumption, while a compressed output swing means that the OTA's performance (mainly linearity) will deteriorate. The circuit of the embodiment of the present application uses switched capacitors instead of traditional MOSFET current sources to avoid the introduction of non-common-mode noise, achieving a low-noise power supply circuit, and eliminating the need to increase the OTA's supply voltage, thereby saving power consumption.

[0058] From an application perspective, the technical solution proposed in this application using switched capacitors for power supply is particularly suitable for high-gain, high-linearity, and low-noise OTA designs using advanced CMOS processes. Compared to older CMOS processes (such as 180nm CMOS processes), transistor noise is higher in advanced CMOS processes. The circuits in the embodiments of this application use switched capacitors instead of traditional MOSFET current sources for power supply, which can reduce noise while avoiding the need for higher supply voltages and thus saving power. At the same time, high-speed switching circuits are easier to design in advanced CMOS processes.

[0059] While various embodiments of the present application have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A low-noise circuit for powering an operational transconductance amplifier OTA, characterized in that: include: A first switched capacitor circuit and a second switched capacitor circuit; the first switched capacitor circuit and the second switched capacitor circuit respectively include at least four switches and at least one capacitor; wherein, when the connection between the capacitor and the OTA is turned on, the capacitor is used to power the OTA; when the connection between the capacitor and the OTA is turned off, the capacitor is in a charging state; each of the switches is closed or opened in response to a clock signal to control the on and off of the connection between the corresponding capacitor and the OTA.

2. The circuit according to claim 1, characterized in that The first switch capacitor circuit includes a first capacitor, a first switch, a second switch, a third switch and a fourth switch; the second switch capacitor circuit includes a second capacitor, a fifth switch, a sixth switch, a seventh switch and an eighth switch; The first end of the first switch, the first end of the third switch, the first end of the fifth switch, and the first end of the seventh switch are connected to the OTA respectively; the second end of the first switch and the first end of the second switch are connected to the first end of the first capacitor; the second end of the third switch and the first end of the fourth switch are connected to the second end of the first capacitor; the second end of the fifth switch and the first end of the sixth switch are connected to the first end of the second capacitor; the second end of the seventh switch and the first end of the eighth switch are connected to the second end of the second capacitor; the second end of the second switch and the second end of the sixth switch are connected to a first voltage; the second end of the fourth switch and the second end of the eighth switch are connected to a second voltage; The first switch, the third switch, the fifth switch and the seventh switch are closed in response to a first level in the first clock signal, and are opened in response to a second level in the first clock signal; The second switch, the fourth switch, the sixth switch and the eighth switch are closed in response to the first level in the second clock signal, and are opened in response to the second level in the second clock signal; Wherein, the first clock signal and the second clock signal have the same clock period and opposite levels; When the first switch, the third switch, the fifth switch and the seventh switch are closed in response to the first clock signal, the second switch, the fourth switch, the sixth switch and the eighth switch are opened in response to the second clock signal, and the first capacitor and the second capacitor are used to power the OTA; when the second switch, the fourth switch, the sixth switch and the eighth switch are closed in response to the second clock signal, the first switch, the third switch, the fifth switch and the seventh switch are opened in response to the first clock signal, and the first capacitor and the second capacitor are in a charging state.

3. The circuit according to claim 2, characterized in that The first switch capacitor circuit further includes a third capacitor, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch; the second switch capacitor circuit further includes a fourth capacitor, a thirteenth switch, a fourteenth switch, a fifteenth switch and a sixteenth switch; The first end of the ninth switch is connected to the first end of the first switch; the first end of the eleventh switch is connected to the first end of the third switch; the first end of the thirteenth switch is connected to the first end of the fifth switch; the first end of the fifteenth switch is connected to the first end of the seventh switch; the second end of the ninth switch and the first end of the tenth switch are connected to the first end of the third capacitor; the second end of the eleventh switch and the first end of the twelfth switch are connected to the second end of the third capacitor; the second end of the thirteenth switch and the first end of the fourteenth switch are connected to the first end of the fourth capacitor; the second end of the fifteenth switch and the first end of the sixteenth switch are connected to the second end of the fourth capacitor; the second end of the tenth switch and the second end of the fourteenth switch are connected to the first voltage; the second end of the twelfth switch and the second end of the sixteenth switch are connected to the second voltage; The tenth switch, the twelfth switch, the fourteenth switch and the sixteenth switch are closed in response to a first level in the first clock signal, and are opened in response to a second level in the first clock signal; the ninth switch, the eleventh switch, the thirteenth switch, and the fifteenth switch are closed in response to the first level in the second clock signal, and are opened in response to the second level in the second clock signal; Wherein, when the tenth switch, the twelfth switch, the fourteenth switch and the sixteenth switch are closed in response to the first clock signal, the ninth switch, the eleventh switch, the thirteenth switch and the fifteenth switch are opened in response to the second clock signal, and the third capacitor and the fourth capacitor are in a charging state; When the ninth switch, the eleventh switch, the thirteenth switch, and the fifteenth switch are closed in response to the second clock signal, the tenth switch, the twelfth switch, the fourteenth switch, and the sixteenth switch are opened in response to the first clock signal, and the third capacitor and the fourth capacitor are used to power the OTA.

4. The circuit according to claim 3, characterized in that The OTA includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first resistor and a second resistor; The gate of the first PMOS tube is connected to the gate of the second NMOS tube, forming a first input end of the OTA; the gate of the third PMOS tube is connected to the gate of the fourth NMOS tube, forming a second input end of the OTA; the source of the first PMOS tube and the first end of the first resistor are connected to the first end of the first switch; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the drain of the second PMOS tube is connected to the drain of the first NMOS tube, forming a first output end of the OTA; the source of the first NMOS tube is connected to the drain of the second NMOS tube; the source of the second NMOS tube, the first end of the second resistor and the third The first end of the switch is connected; the source of the third PMOS tube and the second end of the first resistor are connected to the first end of the fifth switch; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, forming the second output end of the OTA; the source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the source of the fourth NMOS tube and the second end of the second resistor are connected to the first end of the seventh switch; the gate of the second PMOS tube and the gate of the fourth PMOS tube are connected to the first gate voltage; the gate of the first NMOS tube and the gate of the third NMOS tube are connected to the second gate voltage.

5. The circuit according to claim 4, characterized in that The circuit also includes a fifth capacitor and a sixth capacitor; The first end of the fifth capacitor is connected to the source of the first PMOS tube; the second end of the fifth capacitor is connected to the source of the second NMOS tube; the first end of the sixth capacitor is connected to the source of the third PMOS tube; the second end of the sixth capacitor is connected to the source of the fourth NMOS tube.

6. The circuit according to claim 4 or 5, characterized in that The capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are equal.

7. The circuit according to claim 6, characterized in that The duty cycle of the first clock signal and the second clock signal is 50%; the capacitance values ​​C of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are S =0.5T S I B / (V top -V bottom ), where T S I represents the clock cycle of the first clock signal and the second clock signal; B Represents the bias current required for the normal operation of the OTA; V top represents the source voltage of the first PMOS tube; V bottom represents the source voltage of the second NMOS tube; V top -V bottom The value of is equal to the sum of the absolute values ​​of the drain-source voltages of the first PMOS tube, the second PMOS tube, the first NMOS tube, and the second NMOS tube.

8. The circuit according to claim 7, characterized in that The first capacitor includes N capacitors with a capacitance value of N·C S The first sub-capacitor is connected in parallel when the first capacitor is in a charging state; and the N first sub-capacitors are connected in series when the first capacitor is used to power the OTA. The second capacitor includes N capacitors with a capacitance value of N·C S When the second capacitor is in a charging state, N of the second sub-capacitors are connected in parallel; when the second capacitor is used to power the OTA, N of the second sub-capacitors are connected in series; The third capacitor includes N capacitors with a capacitance value of N·C S When the third capacitor is in a charging state, N of the third sub-capacitors are connected in parallel; when the third capacitor is used to power the OTA, N of the third sub-capacitors are connected in series; The fourth capacitor includes N capacitors with a capacitance value of N·C S when the fourth capacitor is in a charging state, N of the fourth sub-capacitors are connected in parallel; when the fourth capacitor is used to power the OTA, N of the fourth sub-capacitors are connected in series.

9. The circuit according to claim 8, characterized in that The first voltage and the second voltage satisfy: V L +(V H -V L ) / 2=V bottom +(V top -V bottom ) / 2 and N·(V H -V L )=2·(V top -V bottom ); Among them, V H represents the first voltage; V L represents the second voltage.

10. The circuit according to claim 4, characterized in that The circuit also includes: a fifth PMOS tube, a sixth PMOS tube and a first operational amplifier; the first input terminal of the first operational amplifier inputs the output common mode voltage of the OTA; the second input terminal of the first operational amplifier inputs the reference common mode voltage; the gate of the fifth PMOS tube and the gate of the sixth PMOS tube are connected to the output terminal of the first operational amplifier; the source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to a third voltage; the drain of the fifth PMOS tube is connected to the source of the first PMOS tube; the drain of the sixth PMOS tube is connected to the source of the third PMOS tube; wherein the output common mode voltage is the sum of the first output voltage output from the first output terminal of the OTA and the second output voltage output from the second output terminal of the OTA divided by 2.

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