Simple current mode relaxation oscillator

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a simple current mode relaxation oscillator. According to the invention, the input comparator generates a pair of different high and low flip thresholds, the MOS capacitor is charged through the IPTAT source current, when the voltage reaches the upper flip threshold, the IPTAT sink current discharges the capacitor, and when the voltage reaches the lower flip threshold, the voltage returns to the stage of charging the capacitor through the IPTAT source current. A triangular wave is output through periodic charging and discharging of an IPTAT current to a capacitor, and finally a standard rectangular wave is obtained by adding two stages of buffers behind to shape the waveform. The circuit has the advantages that compared with a traditional current mode relaxation oscillator, two comparators and a high-low threshold generation circuit used for comparator input are omitted, in addition, the capacitor is an MOS capacitor, and the complexity and the area of the circuit are greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a simple current mode relaxation oscillator. Background Art

[0002] In the SIC MOSFET half-bridge drive application, the turning on of the high-side power tube will bring a large positive dv / dt to the SW. This dv / dt will be coupled to the gate of the low-side power tube through crosstalk, which may cause the low-side power tube to be turned on by mistake, so that the high-side and low-side form a direct connection from the power supply to the ground. Therefore, this risk needs to be eliminated. The common method is to give the low-side power tube a negative turn-off voltage. The generation of negative voltage usually requires a negative voltage charge pump, which requires an oscillator.

[0003] Considering that the error of the output frequency of various PVT oscillators cannot be too large, a current mode relaxation oscillator is used. The traditional current mode relaxation oscillator requires an IPTAT current generation module, two comparator circuits, an RS trigger, and high and low threshold generation circuits. Obviously, the area is too large for a SIC MOSFET drive circuit, and the circuit is too complicated, so a new circuit architecture is needed. Summary of the invention

[0004] In view of the above-mentioned needs, the present invention proposes a simple current mode relaxation oscillator circuit to meet the clock requirements of the charge pump with a smaller area, circuit complexity and power consumption.

[0005] The technical solution of the present invention is:

[0006] A simple current mode relaxation oscillator, characterized in that it includes an IPTAT current source, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a first inverter, and a second inverter;

[0007] The drain of the first NMOS tube MN1 is connected to its own gate and connected to the input of the IPTAT current source, and the source of the first NMOS tube MN1 is grounded; the gate of the second NMOS tube MN2 is connected to the gate of the first NMOS tube MN1, the drain of the second NMOS tube MN2 is connected to the drain of the first PMOS tube MP1, and the source of the second NMOS tube MN2 is grounded; the gate of the third NMOS tube MN3 is connected to the gate of the first NMOS tube MN1, the drain of the third NMOS tube MN3 is connected to the source of the fourth NMOS tube MN4, and the source of the third NMOS tube MN3 is grounded; the fourth NMOS tube MN4 The gate of the fourth NMOS tube MN4 is connected to the gate of the third PMOS tube MP3, the drain of the fourth NMOS tube MN4 is connected to the drain of the third PMOS tube MP3, and the source of the fourth NMOS tube MN4 is connected to the drain of the third NMOS tube MN3; the gate of the fifth NMOS tube MN5 is connected to the drain of the third PMOS tube MP3, and the source and drain of the fifth NMOS tube MN5 are grounded; the gate of the sixth NMOS tube MN6 is connected to the drain of the third PMOS tube MP3, the source of the sixth NMOS tube MN6 is connected to the drain of the seventh NMOS tube MN7, and the drain of the sixth NMOS tube MN6 is connected to the source of the eighth NMOS tube MN8 The gate of the seventh NMOS tube MN7 is connected to the gate of the first NMOS tube MN1, the drain of the seventh NMOS tube MN7 is connected to the source of the sixth NMOS tube MN6, and the source of the seventh NMOS tube MN7 is grounded; the gate of the eighth NMOS tube MN8 is connected to the drain of the third PMOS tube MP3, the source of the eighth NMOS tube MN8 is connected to the drain of the sixth NMOS tube MN6, and the drain of the eighth NMOS tube MN8 is connected to the drain of the sixth PMOS tube MP6; the gate of the ninth NMOS tube MN9 is connected to the gate of the third PMOS tube MP3, the drain of the ninth NMOS tube MN9 is connected to the gate of the eighth NMOS tube The drain of the ninth NMOS tube MN8 is connected to the drain of the eighth NMOS tube MN8, the source of the ninth NMOS tube MN9 is connected to the source of the eighth NMOS tube MN8; the gate of the tenth NMOS tube MN10 is connected to the drain of the eighth NMOS tube MN8, the drain of the tenth NMOS tube MN10 is connected to the drain of the ninth PMOS tube MP9, and the source of the tenth NMOS tube MN10 is connected to the drain of the eleventh NMOS tube MN11; the gate of the eleventh NMOS tube MN11 is connected to the gate of the first NMOS tube MN1, the drain of the eleventh NMOS tube MN11 is connected to the source of the tenth NMOS tube MN10, and the source of the eleventh NMOS tube MN11 is grounded;

[0008] The drain of the first PMOS tube MP1 is connected to its own gate, and the source of the first PMOS tube MP1 is connected to the power supply; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1, the drain of the second PMOS tube MP2 is connected to the source of the third PMOS tube MP3, and the source of the second PMOS tube MP2 is connected to the power supply; the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4, the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4, and the source of the third PMOS tube MP3 is connected to the drain of the second PMOS tube MP2; the gate of the fourth PMOS tube MP4 is connected to the gate of the first PMOS tube MP1, the drain of the fourth PMOS tube MP4 is connected to the source of the fifth PMOS tube MP5, and the source of the fifth PMOS tube MP5 is connected to the power supply; the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6, the drain of the fifth PMOS tube MP5 is connected to the source of the sixth PMOS tube MP6, and the source of the fifth PMOS tube MP5 is connected to the gate of the fourth PMOS tube MP4. The drain of the fifth PMOS tube MP5 is connected to the drain of the fifth PMOS tube MP5; the gate of the sixth PMOS tube MP6 is connected to the gate of the fifth PMOS tube MP5, the drain of the sixth PMOS tube MP6 is connected to the drain of the eighth NMOS tube MN8, and the source of the sixth PMOS tube MP6 is connected to the drain of the fifth PMOS tube MP5; the gate of the seventh PMOS tube MP7 is connected to the gate of the ninth NMOS tube MN9, the drain of the seventh PMOS tube MP7 is connected to the drain of the sixth PMOS tube MP6, and the source of the seventh PMOS tube MP7 is connected to the gate of the ninth NMOS tube MN9. The source of the sixth PMOS tube MP6 is connected; the gate of the eighth PMOS tube MP8 is connected to the gate of the first PMOS tube MP1, the drain of the eighth PMOS tube MP8 is connected to the source of the ninth PMOS tube MP9, and the source of the eighth PMOS tube MP8 is connected to the power supply; the gate of the ninth PMOS tube MP9 is connected to the gate of the tenth NMOS tube MN10, the drain of the ninth PMOS tube MP9 is connected to the drain of the tenth NMOS tube MN10, and the source of the ninth PMOS tube MP9 is connected to the drain of the eighth PMOS tube MP8;

[0009] The connection points of the gate of the third PMOS transistor MP3, the gate of the fourth NMOS transistor MN4, the drain of the ninth PMOS transistor MP9 and the drain of the tenth NMOS transistor MN10 sequentially pass through the first inverter and the second inverter to output the clock signal.

[0010] Beneficial effects of the present invention:

[0011] 1) Since it no longer requires two comparators and high and low threshold generation circuits like the traditional current mode relaxation oscillator, the static power consumption is significantly reduced. In addition, the structure with source current source and sink current source can also control the dynamic power consumption to a very small level. 2) The capacitors used for charging and discharging are MOS capacitors, and the high and low thresholds are generated by the hysteresis characteristics of the single-input comparator without the need for additional circuits, and the circuit area and circuit complexity are significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a structural diagram of a simple current mode relaxation oscillator circuit implementation proposed by the present invention. DETAILED DESCRIPTION

[0013] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings:

[0014] like Figure 1 As shown, the current mode relaxation oscillator of the present invention can be divided into a module capable of controlling the IPTAT current to charge and discharge the MOS capacitor and a two-stage buffer;

[0015] The module for controlling the IPTAT current to charge and discharge the MOS capacitor includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, and a ninth PMOS tube MP9; the buffer is composed of two stages of inverters connected in series.

[0016] The working principle of the present invention is:

[0017] In the initial state, there is no charge stored on the MOS capacitor MN5, and the gate voltage of MN5 is 0V. MP5 and MP6 are turned on, making the gate voltage of MN10 VDD. MN10 is turned on, so the gate voltage of MP3 is 0V. MP3 is turned on, and the IPTAT current of MP2 begins to charge the MOS capacitor MN5. The gate voltage of MN5 gradually increases. When the voltage rises to the upper flip threshold of the single input comparison composed of MN7, MN6, MN8, MN9 and MP4, MP5, MP6, and MP7, MN8 and MN6 are turned on, making the gate voltage of MN10 0V, and then MP9 is turned on, making the gate voltage of MN4 VDD, turning on MN4, and the IPTAT current of MN3 begins to discharge the charge on the MOS capacitor MN5. When the voltage of the MOS capacitor formed by MN5 drops to the down-turn threshold of the single input comparison formed by MN7, MN6, MN8, MN9 and MP4, MP5, MP6, MP7, MP5 and MP6 are turned on, making the gate voltage of MN10 VDD, and then turning on MN10 makes the gate voltage of MN4 0V, turning on MP3, and the IPTAT current of MP3 charges the MOS capacitor MN5. Finally, a periodic triangle wave is generated on the gate of MN5, and the triangle wave is shaped by the subsequent single input comparator, inverter and buffer stage to output a standard rectangular wave.

[0018] The functions of MN9 and MP7 are: when the MOS capacitor MN5 is charged to the upper flip threshold, MP7 is turned on, MP6 is short-circuited, and MN9 is turned off; when the MOS capacitor MN5 is discharged to the lower flip threshold, MP7 is turned off, MN9 is turned on, and MN8 is short-circuited.

[0019] The frequency of the output oscillator can be subsequently changed by adjusting the discharge current of MN3 and the charging circuit size of MP2 or the size of the MOS capacitor MN3. For example, the period of the output oscillator can be reduced by increasing the charging current and the discharging current, and the frequency of the clock can be increased; similarly, the period of the output oscillator can be increased by reducing the charging current and the discharging current, and the frequency of the clock can be reduced; the frequency of the clock can also be reduced by increasing or decreasing the size of the MOS capacitor.

[0020]

[0021] In summary, the input comparator with hysteresis characteristics of the present invention generates a pair of different high and low flip thresholds, charges the MOS capacitor through the IPTAT source current, and discharges the capacitor through the IPTAT sink current when the voltage reaches the upper flip threshold. When the voltage reaches the lower flip threshold, it returns to the stage where the IPTAT source current charges the capacitor. A triangular wave is output through the periodic charging and discharging of the capacitor by the IPTAT current, and finally a two-stage buffer is added at the back to shape the waveform to obtain a standard rectangular wave. The advantage of this circuit is that, compared with the traditional current mode relaxation oscillator, two comparators and a high and low threshold generation circuit for the comparator input are reduced on its basis. In addition, the capacitor adopts a MOS capacitor, which greatly reduces the complexity and area of ​​the circuit.

Claims

1. A simple current mode relaxation oscillator, characterized in that: It includes an IPTAT current source, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a first inverter, and a second inverter; The drain of the first NMOS tube MN1 is connected to its own gate and connected to the input of the IPTAT current source, and the source of the first NMOS tube MN1 is grounded; the gate of the second NMOS tube MN2 is connected to the gate of the first NMOS tube MN1, the drain of the second NMOS tube MN2 is connected to the drain of the first PMOS tube MP1, and the source of the second NMOS tube MN2 is grounded; the gate of the third NMOS tube MN3 is connected to the gate of the first NMOS tube MN1, the drain of the third NMOS tube MN3 is connected to the source of the fourth NMOS tube MN4, and the source of the third NMOS tube MN3 is grounded; the fourth NMOS tube MN4 The gate of the fourth NMOS tube MN4 is connected to the gate of the third PMOS tube MP3, the drain of the fourth NMOS tube MN4 is connected to the drain of the third PMOS tube MP3, and the source of the fourth NMOS tube MN4 is connected to the drain of the third NMOS tube MN3; the gate of the fifth NMOS tube MN5 is connected to the drain of the third PMOS tube MP3, and the source and drain of the fifth NMOS tube MN5 are grounded; the gate of the sixth NMOS tube MN6 is connected to the drain of the third PMOS tube MP3, the source of the sixth NMOS tube MN6 is connected to the drain of the seventh NMOS tube MN7, and the drain of the sixth NMOS tube MN6 is connected to the source of the eighth NMOS tube MN8 The gate of the seventh NMOS tube MN7 is connected to the gate of the first NMOS tube MN1, the drain of the seventh NMOS tube MN7 is connected to the source of the sixth NMOS tube MN6, and the source of the seventh NMOS tube MN7 is grounded; the gate of the eighth NMOS tube MN8 is connected to the drain of the third PMOS tube MP3, the source of the eighth NMOS tube MN8 is connected to the drain of the sixth NMOS tube MN6, and the drain of the eighth NMOS tube MN8 is connected to the drain of the sixth PMOS tube MP6; the gate of the ninth NMOS tube MN9 is connected to the gate of the third PMOS tube MP3, the drain of the ninth NMOS tube MN9 is connected to the gate of the eighth NMOS tube The drain of the ninth NMOS tube MN8 is connected to the drain of the eighth NMOS tube MN8, the source of the ninth NMOS tube MN9 is connected to the source of the eighth NMOS tube MN8; the gate of the tenth NMOS tube MN10 is connected to the drain of the eighth NMOS tube MN8, the drain of the tenth NMOS tube MN10 is connected to the drain of the ninth PMOS tube MP9, and the source of the tenth NMOS tube MN10 is connected to the drain of the eleventh NMOS tube MN11; the gate of the eleventh NMOS tube MN11 is connected to the gate of the first NMOS tube MN1, the drain of the eleventh NMOS tube MN11 is connected to the source of the tenth NMOS tube MN10, and the source of the eleventh NMOS tube MN11 is grounded; The drain of the first PMOS tube MP1 is connected to its own gate, and the source of the first PMOS tube MP1 is connected to the power supply; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1, the drain of the second PMOS tube MP2 is connected to the source of the third PMOS tube MP3, and the source of the second PMOS tube MP2 is connected to the power supply; the gate of the third PMOS tube MP3 is connected to the gate of the fourth NMOS tube MN4, the drain of the third PMOS tube MP3 is connected to the drain of the fourth NMOS tube MN4, and the source of the third PMOS tube MP3 is connected to the drain of the second PMOS tube MP2; the gate of the fourth PMOS tube MP4 is connected to the gate of the first PMOS tube MP1, the drain of the fourth PMOS tube MP4 is connected to the source of the fifth PMOS tube MP5, and the source of the fifth PMOS tube MP5 is connected to the power supply; the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6, the drain of the fifth PMOS tube MP5 is connected to the source of the sixth PMOS tube MP6, and the source of the fifth PMOS tube MP5 is connected to the gate of the fourth PMOS tube MP4. The drain of the fifth PMOS tube MP5 is connected to the drain of the fifth PMOS tube MP5; the gate of the sixth PMOS tube MP6 is connected to the gate of the fifth PMOS tube MP5, the drain of the sixth PMOS tube MP6 is connected to the drain of the eighth NMOS tube MN8, and the source of the sixth PMOS tube MP6 is connected to the drain of the fifth PMOS tube MP5; the gate of the seventh PMOS tube MP7 is connected to the gate of the ninth NMOS tube MN9, the drain of the seventh PMOS tube MP7 is connected to the drain of the sixth PMOS tube MP6, and the source of the seventh PMOS tube MP7 is connected to the gate of the ninth NMOS tube MN9. The source of the sixth PMOS tube MP6 is connected; the gate of the eighth PMOS tube MP8 is connected to the gate of the first PMOS tube MP1, the drain of the eighth PMOS tube MP8 is connected to the source of the ninth PMOS tube MP9, and the source of the eighth PMOS tube MP8 is connected to the power supply; the gate of the ninth PMOS tube MP9 is connected to the gate of the tenth NMOS tube MN10, the drain of the ninth PMOS tube MP9 is connected to the drain of the tenth NMOS tube MN10, and the source of the ninth PMOS tube MP9 is connected to the drain of the eighth PMOS tube MP8; The connection points of the gate of the third PMOS transistor MP3, the gate of the fourth NMOS transistor MN4, the drain of the ninth PMOS transistor MP9 and the drain of the tenth NMOS transistor MN10 sequentially pass through the first inverter and the second inverter to output the clock signal.

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