Comparator circuit, depletion type device with different threshold voltages and manufacturing method of depletion type device

Abstract

The invention discloses a comparator circuit, a depletion type device with different threshold voltages and a manufacturing method of the depletion type device. The comparator circuit with high switching speed, high voltage comparison range and high precision comprises a first depletion mode HEMT, a second depletion mode HEMT, a third depletion mode HEMT, a first enhancement mode HEMT and a second enhancement mode HEMT, the threshold voltage of the first depletion mode HEMT and the threshold voltage of the third depletion mode HEMT are equal and larger than the threshold voltage of the second depletion mode HEMT, and the threshold voltage of the first depletion mode HEMT is larger than the threshold voltage of the second depletion mode HEMT. And the threshold voltages of the first enhanced HEMT and the second enhanced HEMT are the same. The comparator circuit comprising the high-low threshold voltage depletion type device has the advantages of being high in switching speed, high in voltage comparison range and high in precision.

Description

Technical Field

[0001] The present invention relates to a voltage comparator circuit based on an enhancement-depletion (E / D) type GaN-based high electron mobility transistor (HEMT), and in particular to a voltage comparator based on a multi-threshold voltage depletion type HEMT preparation process, and in particular to a comparator circuit, a depletion type device with different threshold voltages and a manufacturing method thereof, and belongs to the technical field of semiconductor electronic devices and circuits. Background Art

[0002] As a wide bandgap semiconductor, GaN has the advantages of high critical electric field, high saturation velocity and excellent thermal stability. GaN-based HEMT composed of heterostructures such as AlGaN / GaN has high electron concentration and mobility. Smaller on-resistance and gate charge mean better conduction and switching performance. It has excellent performance under high voltage, high frequency, high temperature and other environments. GaN-based HEMT can be used as a high-efficiency power conversion system, including electric vehicles, mobile phone chargers, renewable energy and data centers, and has broad application prospects.

[0003] In the field of power electronics and radio frequency, in order to achieve certain specific functions, such as driving, protection, and control, it is usually necessary to integrate certain circuit structures inside the chip. These circuit structures are composed of the most basic logic units, such as inverters and comparators. In the GaN material system, the mobility of the two-dimensional electron gas (2DEG) induced by the polarization effect of the AlGaN / GaN heterojunction is very high, but the p-type material needs to be doped with a higher concentration of Mg due to the incomplete ionization of the acceptor Mg impurity, and the hole mobility in GaN is very low. Currently, n-channel depletion mode (D-mode) devices are used to replace GaN p-channel devices. Enhancement mode (E-mode) and depletion mode (D-mode) GaN HEMTs are combined into logic units according to the corresponding designs. The corresponding schematic diagrams of GaN-based enhancement mode and depletion mode HEMT structures are shown in the figure. Figure 1 , Figure 2 As shown in the figure, the most classic voltage comparator structure in Si-based integrated circuits consists of five transistors. This structure is similarly applied to GaN-based circuits, and a GaN-based voltage comparator is successfully implemented.

[0004] The voltage comparator compares the differential input voltage, and the output level reflects the relative size of the differential input voltage. As a basic logic module of integrated circuits, the comparator plays an important role in circuits such as overvoltage protection, waveform conversion, AC-DC conversion, and oscillators. Figure 3The circuit diagram of the existing GaN-based HEMT comparator includes three depletion-mode HEMTs D1, D2, and D3 and two enhancement-mode HEMTs E1 and E2. The left and right paths of the circuit are completely symmetrical, and the transistors D1 and D2 are of the same size, and the sizes of E1 and E2 are the same. D1 and D2 are respectively used as active loads of the left and right loops of the comparator, and D3 is used as a tail current source and works in the saturation region; E1 and E2 are differential voltage input terminals, and the differential input terminals of the comparator include the in-phase input terminal (V IN+ ) and the inverting input terminal (V IN- ), either end of which can be used as a reference voltage input terminal (V REF ), the other end can be used as the sampling voltage input end (V IN ). If V is specified IN+ V REF , V IN- V IN When the circuit sampling voltage is less than the comparator reference voltage, the output terminal maintains a high level; when the circuit sampling voltage is higher than the comparator reference voltage, the right circuit is turned on, and the output voltage jumps from a high level to a low level. By adjusting the size ratio (gate width) of the load and input transistors, the size of the output low level can be adjusted. When E2 is turned on, it is equivalent to the voltage division of the three transistors in the right channel, W D2 / W E2 The smaller the ratio, the greater the on-resistance of the D2 transistor relative to E2, the greater the voltage division, and the lower the output low level. In addition, the threshold voltage of the depletion-mode HEMT cannot be too negative, so that the tail current source D3 works in the saturation region to ensure the accuracy of the voltage comparison. The comparator is implemented on the GaN HEMT platform, and both D / E-mode HEMTs use a groove gate MIS structure.

[0005] The existing comparator circuit uses the MIS-HEMT process. Since the D / E-mode HEMT gates involve etching processes, a large number of interface states are generated, resulting in gate reliability issues. In addition, the uneven etching makes it difficult to control the device threshold voltage, and the circuit repeatability is very poor. In general circuits, all depletion-mode HEMTs have a uniform threshold voltage during the manufacturing process, and enhancement-mode HEMTs also have a uniform threshold voltage. This makes it difficult to balance the rise time and voltage comparison range when the comparator is turned on, affecting the high-frequency application of the circuit and the accuracy of the function. The specific explanation is as follows: First, the preparation of devices in existing comparators involves the AlGaN etching process. As a barrier layer, the etching depth of AlGaN has a great influence on the threshold voltage. However, dry etching has uniformity problems, especially at a target etching depth of ~10 nm, it is difficult to ensure accurate etching. For epitaxial wafers from different batches, even if the set etching time, etching gas, chamber pressure, and power are the same, the etching depth will be different due to factors such as etching at different times and the stability of the etching machine. It is difficult to achieve the required etching depth every time, so the repeatability of circuit preparation is low. At the same time, due to the limitations of the process, the above-mentioned type of comparator is more suitable for laboratory research rather than commercial production.

[0006] Secondly, the existing comparator preparation process performs gate etching on D / E-mode HEMTs, and the thickness of the barrier layer below the gate is thinned by etching to control the degree of 2DEG depletion below the gate. Dry etching will inevitably cause lattice damage and surface contamination to the GaN / AlGaN layer, introduce gate interface states, cause threshold voltage drift, gate leakage and other problems, and affect the long-term reliability of the device. Gate dielectric deposition cannot restore the etched interface to the growth state. In addition, the introduction of defects will affect the switching speed of the device, thereby reducing the circuit response speed, making it difficult to fully release the intrinsic advantages of GaN materials at high speed and high frequency.

[0007] Third, in the preparation process of the existing comparator circuit, all depletion-mode HEMT threshold voltages are the same, and all enhancement-mode HEMT threshold voltages are also the same. When the circuit is working, the tail current source D3 transistor is in a saturated state. In order not to increase the extra area, the D3 transistor is usually not driven additionally but its gate and source are shorted. When the depletion-mode HEMT threshold voltage is closer to 0 V, it is easier to enter the saturation state and the voltage comparison range is larger. However, the gate and source of the D2 transistor with the same threshold voltage are also in a shorted state, and the device size is small and V GS -V TH The small V of the transistor leads to a small current, and the load capacitor is charged slowly when the output is converted from a low level to a high level, and the circuit rise time is long. On the contrary, the more negative the threshold voltage of the depletion-type HEMT is, the more difficult it is for the tail current source D3 to enter the saturation region, affecting the voltage comparison range, but the larger V of the D2 transistor GS -V TH This allows it to reach a higher saturation current, accelerate the charging speed of the load capacitor, and shorten the circuit rise time. The single threshold of the depletion-mode HEMT makes it difficult to balance the rise time and voltage comparison range when the comparator is turned on, limiting the application of the circuit. Summary of the invention

[0008] The main purpose of the present invention is to provide a comparator circuit, a depletion-type device with different threshold voltages and a manufacturing method thereof, so as to overcome the deficiencies in the prior art.

[0009] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes: A first aspect of an embodiment of the present invention provides a comparator circuit with high switching speed, high voltage comparison range and high precision, comprising: a first depletion-mode HEMT, a second depletion-mode HEMT, a third depletion-mode HEMT, a first enhancement-mode HEMT and a second enhancement-mode HEMT, The gates of the first depletion-mode HEMT and the second depletion-mode HEMT are short-connected, the source of the first depletion-mode HEMT is connected to the drain of the first enhancement-mode HEMT, the source and gate of the second depletion-mode HEMT are short-connected and connected to the drain of the second enhancement-mode HEMT, the source of the first enhancement-mode HEMT is connected to the drain of the third depletion-mode HEMT, and the source of the second enhancement-mode HEMT is connected to the drain of the third depletion-mode HEMT, The gate of the first enhancement-mode HEMT serves as a non-inverting input port, the gate of the second enhancement-mode HEMT serves as an inverting input port, the drain of the first depletion-mode HEMT and the drain of the second depletion-mode HEMT are connected to a supply voltage, the gate and source of the second depletion-mode HEMT serve as comparator output ports at the same time, and the gate of the third depletion-mode HEMT is connected to a DC voltage and the source is grounded; The threshold voltages of the first depletion-mode HEMT and the third depletion-mode HEMT are equal and greater than the threshold voltage of the second depletion-mode HEMT, and the threshold voltages of the first enhancement-mode HEMT and the second enhancement-mode HEMT are the same.

[0010] A second aspect of an embodiment of the present invention provides a method for manufacturing the comparator circuit having high switching speed, high voltage comparison range and high precision, comprising: providing a HEMT epitaxial wafer, on which a first HEMT region, a second HEMT region, a third HEMT region, a fourth HEMT region and a fifth HEMT region are defined; Processing the epitaxial wafers of the first HEMT region, the second HEMT region, and the third HEMT region to form an electrically isolated depletion-type HEMT epitaxial structure, manufacturing electrodes matching the depletion-type HEMT epitaxial structure, forming a first depletion-type HEMT, a second depletion-type HEMT, and a third depletion-type HEMT in the first HEMT region, the second HEMT region, and the third HEMT region, respectively, and making the threshold voltages of the first depletion-type HEMT and the third depletion-type HEMT equal and greater than the threshold voltage of the second depletion-type HEMT by at least one of the following methods; Mode 1: The depletion-type HEMT epitaxial structure includes a stacked channel layer and a barrier layer, and the thickness of the gate barrier layer in the first HEMT region, the second HEMT region, and the third HEMT region is adjusted; Mode 2: The depletion-type HEMT epitaxial structure includes a stacked channel layer and a barrier layer, and a gate dielectric layer is provided on the surface of the depletion-type HEMT epitaxial structure, and the thickness of the gate dielectric layer in the gate region of the first HEMT region, the second HEMT region, and the third HEMT region is adjusted; Mode 3: The depletion-mode HEMT epitaxial structure includes a stacked channel layer, a barrier layer, and a p-type semiconductor layer, and H ions are injected into at least the gate region p-type semiconductor layer of the first HEMT region, the second HEMT region, and the third HEMT region to passivate the p-type semiconductor layer, and the conditions for H ion injection are adjusted; Mode 4: The depletion-mode HEMT epitaxial structure includes a stacked channel layer, a barrier layer and a p-type semiconductor layer, and at least the thickness of the gate region p-type semiconductor layer of the first HEMT region, the second HEMT region and the third HEMT region is adjusted; The epitaxial wafers of the fourth HEMT region and the fifth HEMT region are processed to form enhanced HEMT epitaxial structures with the same structure and electrical isolation, electrodes matching the enhanced HEMT epitaxial structures are manufactured, and a first enhanced HEMT and a second enhanced HEMT are formed in the fourth HEMT region and the fifth HEMT region respectively, and the threshold voltages of the first enhanced HEMT and the second enhanced HEMT are made to be the same.

[0011] A third aspect of an embodiment of the present invention provides a method for realizing depletion-mode devices with different threshold voltages on the same wafer, comprising: Providing an epitaxial wafer of a HEMT, the HEMT epitaxial wafer comprising a channel layer, a barrier layer and a p-type semiconductor layer stacked in sequence, and defining x electrically isolated device regions on the epitaxial wafer, the x device regions comprising y depletion-type device regions; Perform at least one of the following operations on y depletion-mode device regions to form a depletion-mode HEMT epitaxial structure, where x≥y≥2: Removing the p-type semiconductor layers of y depletion-mode device regions, and etching the gate barrier layers of the depletion-mode device regions, so that the gate barrier layers of at least two depletion-mode device regions have different thicknesses, and the thickness of the gate barrier layers corresponds to the threshold voltage of the depletion-mode HEMT; forming a gate dielectric layer in y depletion-mode device regions of the HEMT epitaxial wafer, and etching the gate dielectric layers in the gate regions of the y depletion-mode device regions so that the gate dielectric layers in the gate regions of at least two depletion-mode device regions have different thicknesses, respectively, and the thickness of the gate dielectric layer in the gate region corresponds to the threshold voltage of the depletion-mode HEMT; Performing H ion implantation on p-type semiconductor layers of y depletion-mode device regions of the HEMT epitaxial wafer to passivate the p-type semiconductor layers, and adjusting H ion implantation conditions so that the p-type semiconductor layers of at least two depletion-mode device regions have different H ion concentrations and distribution depths, and the H ion concentration and distribution depth in the p-type semiconductor layer of the gate region correspond to the threshold voltage of the depletion-mode HEMT; Thinning the p-type semiconductor layers of y depletion-mode device regions of the HEMT epitaxial wafer so that the p-type semiconductor layers of the gate regions of at least two depletion-mode device regions have different thicknesses, and the thickness of the p-type semiconductor layers of the depletion-mode device regions corresponds to the threshold voltage of the depletion-mode HEMT; Electrodes are fabricated in y depletion-mode device regions respectively to form y depletion-mode HEMTs, wherein threshold voltages of at least two depletion-mode HEMTs are different.

[0012] A fourth aspect of an embodiment of the present invention provides a device obtained by the method of realizing depletion-mode devices with different threshold voltages on the same wafer.

[0013] Compared with the prior art, the advantages of the present invention include: 1) The present invention can realize high and low threshold voltage depletion-mode HEMTs on the same wafer, which can meet the basic device requirements of logic circuits. The present invention is compatible with the commercial p-GaN HEMT platform, and can realize monolithic integration of circuits while improving circuit performance.

[0014] 2) Compared with the circuit of a single threshold voltage depletion-type device, the comparator circuit including high and low threshold voltage depletion-type devices implemented by the present invention has the characteristics of taking into account both high switching speed and high voltage comparison range and accuracy. Moreover, compared with the traditional comparator circuit, the high and low threshold voltage depletion-type devices in the present invention do not increase the circuit area.

[0015] 3) The present invention has strong applicability. The high and low threshold voltage depletion-type HEMTs in the present invention can be applied to various expansion circuits. When a stable current is required, a high threshold voltage depletion-type device is used, and the device on-state power consumption can be reduced. When a fast switching speed is required, a low threshold voltage depletion-type device is used. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of an enhanced HEMT in an existing GaN-based monolithic integrated circuit; Figure 2 It is a schematic diagram of the structure of a depletion-mode HEMT in an existing GaN-based monolithic integrated circuit; Figure 3 It is a comparator structure based on enhancement mode and depletion mode GaN HEMT in the prior art; Figure 4 is a schematic structural diagram of an enhanced HEMT epitaxial wafer provided in Example 1 of the present invention; Figure 5 It is a schematic diagram of the structure after the first gate and the second gate are manufactured in Embodiment 1 of the present invention; Figure 6 is a schematic structural diagram of depletion-mode transistors with different threshold voltages on the same epitaxial wafer in Embodiment 1 of the present invention; Figure 7 is a schematic structural diagram of depletion-mode transistors with different threshold voltages on the same epitaxial wafer in Embodiment 2 of the present invention; Figure 8 is a schematic structural diagram of depletion-mode transistors with different threshold voltages on the same epitaxial wafer in Embodiment 3 of the present invention; Fig. 9 It is a schematic diagram of a comparator circuit structure provided in a typical implementation case of the present invention, which is composed of a single threshold voltage enhancement type and high and low threshold voltage depletion type HEMTs; Fig.10 The GaN-based multi-threshold depletion-mode HEMT comparator (DV TH,D ) and the single-threshold depletion-mode HEMT-based comparator in the comparative example (SV TH,D )’s static characteristics comparison chart; Fig.11 The GaN-based multi-threshold depletion-mode HEMT comparator (DV TH,D ) and the comparator based on single threshold depletion type HEMT in comparative example 1 (SV TH,D ) when it is turned on, the rise time t rise , output low level V OL , Voltage comparison range V range Comparison chart; Fig.12 The GaN-based multi-threshold depletion-mode HEMT comparator (DV TH,D ) and the single-threshold depletion-mode HEMT-based comparator in the comparative example (SV TH,D )’s static characteristics comparison chart; Fig.13 The GaN-based multi-threshold depletion-mode HEMT comparator (DV TH,D ) and the single-threshold depletion-mode HEMT-based comparator in the comparative example (SV TH,D ) when it is turned on, the rise time t rise , output low level V OL , Voltage comparison range V range Comparison chart; Fig.14 The GaN-based multi-threshold depletion-mode HEMT comparator (DV TH,D ) and the single-threshold depletion-mode HEMT-based comparator in the comparative example (SV TH,D )’s static characteristics comparison chart; Fig.15 The GaN-based multi-threshold depletion-mode HEMT comparator (DV TH,D ) and the single-threshold depletion-mode HEMT-based comparator in the comparative example (SV TH,D ) when it is turned on, the rise time t rise , output low level V OL , Voltage comparison range V range Comparison chart; Fig.16 is a schematic structural diagram of depletion-mode transistors with different threshold voltages on the same epitaxial wafer in Embodiment 4 of the present invention; Fig.17 It is a schematic diagram of the structure of depletion-mode transistors with different threshold voltages on the same epitaxial wafer in Example 5 of the present invention. DETAILED DESCRIPTION

[0017] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0018] Term explanation: The gate region, also known as the gate area, is the orthographic projection area under the gate.

[0019] The gate dielectric layer in the gate region refers to the gate dielectric layer in the orthographic projection region below the gate.

[0020] The gate region barrier layer refers to the barrier layer located in the orthographic projection area below the gate.

[0021] It should be noted that, in the embodiment of the present invention, the gate dielectric layer may be regarded as a structure of the HEMT epitaxial structure itself, or the gate dielectric layer may be regarded as a structural layer independent of the HEMT epitaxial structure.

[0022] The present invention provides a high and low threshold depletion-mode HEMT solution for logic circuits, wherein the depletion-mode HEMT is compatible with the commercialized p-GaN HEMT process, thereby avoiding the problems of lattice damage and interface states caused by gate etching of enhancement-mode devices in circuit preparation.

[0023] The present invention proposes to use AlGaN barrier layers with or without gate dielectrics, with or without grooves, to graphically prepare different depletion-mode HEMT gates, so as to realize depletion-mode devices with different threshold voltages on the same wafer. Alternatively, a layer of silicon nitride dielectric is deposited on the barrier layer of the depletion-mode device, which will induce more 2DEG in the channel, while the gate dielectric weakens the gate control ability, the device saturation current increases and the 2DEG is more difficult to deplete, and the device threshold voltage shifts negatively; while the depletion-mode device without a dielectric layer has a high threshold voltage due to its relatively low 2DEG concentration.

[0024] In addition, methods to further increase the threshold voltage of depletion-mode devices include grooved AlGaN barrier layers to reduce the thickness of the barrier layers in the gate region, reduce the 2DEG concentration induced by the AlGaN / GaN heterojunction, or, because the comparator circuit integrates enhancement-mode and depletion-mode devices, retain a small portion of p-type GaN above the gate of the depletion-mode transistor under process compatibility to partially deplete the 2DEG below the gate, thereby increasing the threshold voltage of the depletion-mode device. By performing one more process step, depletion-mode transistors with different threshold voltages can be obtained to meet the different requirements of different nodes of the circuit for device characteristics and device working areas. For the comparator circuit, a high threshold voltage can make the tail current source D3 easy to work in the required saturation region, and a low threshold voltage can increase the operating current of the D2 transistor, taking into account both the voltage comparison range and the circuit opening speed.

[0025] A first aspect of an embodiment of the present invention provides a comparator circuit with high switching speed, high voltage comparison range and high precision, comprising: a first depletion-mode HEMT, a second depletion-mode HEMT, a third depletion-mode HEMT, a first enhancement-mode HEMT and a second enhancement-mode HEMT, The gates of the first depletion-mode HEMT and the second depletion-mode HEMT are short-connected, the source of the first depletion-mode HEMT is connected to the drain of the first enhancement-mode HEMT, the source and gate of the second depletion-mode HEMT are short-connected and connected to the drain of the second enhancement-mode HEMT, the source of the first enhancement-mode HEMT is connected to the drain of the third depletion-mode HEMT, and the source of the second enhancement-mode HEMT is connected to the drain of the third depletion-mode HEMT, The gate of the first enhancement-mode HEMT serves as a non-inverting input port, the gate of the second enhancement-mode HEMT serves as an inverting input port, the drain of the first depletion-mode HEMT and the drain of the second depletion-mode HEMT are connected to a supply voltage, the gate and source of the second depletion-mode HEMT serve as comparator output ports at the same time, and the gate of the third depletion-mode HEMT is connected to a DC voltage and the source is grounded; The threshold voltages of the first depletion-mode HEMT and the third depletion-mode HEMT are equal and greater than the threshold voltage of the second depletion-mode HEMT, and the threshold voltages of the first enhancement-mode HEMT and the second enhancement-mode HEMT are the same.

[0026] Furthermore, the threshold voltages of the first depletion-mode HEMT and the third depletion-mode HEMT are in the range of -3 V to 0.2 V, and the threshold voltage of the second depletion-mode HEMT is in the range of -10 V to -6 V.

[0027] Furthermore, the gate width W of the first depletion-mode HEMT is 401 = Gate width W of the second depletion-mode HEMT 402 , the gate width W of the first enhancement mode HEMT 403 = Gate width W of the second enhancement mode HEMT 404 , the gate width of the third depletion-mode HEMT is W 405 , where W 401 / W 403 / W 405 = 5 / 1000 / 50.

[0028] Furthermore, the first depletion-mode HEMT, the second depletion-mode HEMT, the third depletion-mode HEMT, the first enhancement-mode HEMT, and the second enhancement-mode HEMT are monolithically integrated on the same wafer.

[0029] Further, the epitaxial structures of the first depletion-mode HEMT, the second depletion-mode HEMT, and the third depletion-mode HEMT all include a stacked channel layer and a barrier layer, and the thickness of the gate barrier layer of the first depletion-mode HEMT is different from the thickness of the gate barrier layer of the second depletion-mode HEMT and is the same as the thickness of the gate barrier layer of the third depletion-mode HEMT; Alternatively, the epitaxial structures of the first depletion-mode HEMT, the second depletion-mode HEMT, and the third depletion-mode HEMT all include a stacked channel layer and a barrier layer, and a gate dielectric layer is disposed on the barrier layer, and the thickness of the gate dielectric layer in the gate region of the first depletion-mode HEMT is different from the thickness of the gate dielectric layer in the gate region of the second depletion-mode HEMT and is the same as the thickness of the gate dielectric layer in the gate region of the third depletion-mode HEMT; Alternatively, the epitaxial structures of the first depletion-mode HEMT, the second depletion-mode HEMT, and the third depletion-mode HEMT all include a stacked channel layer, a barrier layer, and a p-type semiconductor layer, the p-type semiconductor layer is passivated by being injected with H ions, and the concentration and distribution depth of H ions in the p-type semiconductor layer in the gate region of the first depletion-mode HEMT are different from the concentration and distribution depth of H ions in the p-type semiconductor layer in the gate region of the second depletion-mode HEMT, but are the same as the concentration and distribution depth of H ions in the p-type semiconductor layer in the gate region of the third depletion-mode HEMT; Alternatively, the epitaxial structures of the first depletion-mode HEMT, the second depletion-mode HEMT, and the third depletion-mode HEMT all include a channel layer, a barrier layer, and a p-type semiconductor layer that are stacked, and the thickness of the p-type semiconductor layer in the gate region of the first depletion-mode HEMT is different from the thickness of the p-type semiconductor layer in the gate region of the second depletion-mode HEMT and is the same as the thickness of the p-type semiconductor layer in the gate region of the third depletion-mode HEMT.

[0030] Further, the thickness of the p-type semiconductor layer in the gate region of the first depletion-mode HEMT and the third depletion-mode HEMT is greater than the thickness of the p-type semiconductor layer in the gate region of the second depletion-mode HEMT. Further, the thickness of the p-type semiconductor layer in the gate region of the first depletion-mode HEMT and the third depletion-mode HEMT is 10 nm to 20 nm, and the thickness of the p-type semiconductor layer in the gate region of the second depletion-mode HEMT is 0 nm to 5 nm.

[0031] A second aspect of an embodiment of the present invention provides a method for manufacturing the comparator circuit having high switching speed, high voltage comparison range and high precision, comprising: providing a HEMT epitaxial wafer, on which a first HEMT region, a second HEMT region, a third HEMT region, a fourth HEMT region and a fifth HEMT region are defined; Processing the epitaxial wafers of the first HEMT region, the second HEMT region, and the third HEMT region to form an electrically isolated depletion-type HEMT epitaxial structure, manufacturing electrodes matching the depletion-type HEMT epitaxial structure, forming a first depletion-type HEMT, a second depletion-type HEMT, and a third depletion-type HEMT in the first HEMT region, the second HEMT region, and the third HEMT region, respectively, and making the threshold voltages of the first depletion-type HEMT and the third depletion-type HEMT equal and greater than the threshold voltage of the second depletion-type HEMT by at least one of the following methods; Mode 1: The depletion-type HEMT epitaxial structure includes a stacked channel layer and a barrier layer, and the thickness of the gate barrier layer in the first HEMT region, the second HEMT region, and the third HEMT region is adjusted; Mode 2: The depletion-type HEMT epitaxial structure includes a stacked channel layer and a barrier layer, and a gate dielectric layer is provided on the surface of the depletion-type HEMT epitaxial structure, and the thickness of the gate dielectric layer in the gate region of the first HEMT region, the second HEMT region, and the third HEMT region is adjusted; Mode 3: The depletion-mode HEMT epitaxial structure includes a stacked channel layer, a barrier layer, and a p-type semiconductor layer, and H ions are injected into at least the gate region p-type semiconductor layer of the first HEMT region, the second HEMT region, and the third HEMT region to passivate the p-type semiconductor layer, and the conditions for H ion injection are adjusted; Mode 4: The depletion-mode HEMT epitaxial structure includes a stacked channel layer, a barrier layer, and a p-type semiconductor layer, and at least the thickness of the gate region p-type semiconductor layer of the first HEMT region, the second HEMT region, and the third HEMT region is adjusted. Preferably, the thickness of the p-type semiconductor layer in the first HEMT region and the third HEMT region is 10 nm to 20 nm, and the thickness of the p-type semiconductor layer in the second HEMT region is 0 nm to 5 nm; The epitaxial wafers of the fourth HEMT region and the fifth HEMT region are processed to form enhanced HEMT epitaxial structures with the same structure and electrical isolation, electrodes matching the enhanced HEMT epitaxial structures are manufactured, and a first enhanced HEMT and a second enhanced HEMT are formed in the fourth HEMT region and the fifth HEMT region respectively, and the threshold voltages of the first enhanced HEMT and the second enhanced HEMT are made to be the same.

[0032] Furthermore, the conditions for H ion implantation include energy, dosage, angle, etc. The specific conditions can be selected according to the needs and are not specifically limited here.

[0033] Furthermore, the HEMT epitaxial wafer includes a channel layer, a barrier layer and a p-type semiconductor layer stacked in sequence, and the manufacturing method specifically includes: removing the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer to form a depletion-mode HEMT epitaxial structure, and etching the gate barrier layer of at least one of the first HEMT region, the second HEMT region, and the third HEMT region, and adjusting the thickness of the gate barrier layer of the first HEMT region, the second HEMT region, and the third HEMT region so that the threshold voltages of the first depletion-mode HEMT and the third depletion-mode HEMT are equal and greater than the threshold voltage of the second depletion-mode HEMT; Alternatively, the p-type semiconductor layers in the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer are removed to form a depletion-mode HEMT epitaxial structure, a gate dielectric layer is formed at least in the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer, and the gate dielectric layer in the gate region of at least one of the first HEMT region, the second HEMT region, and the third HEMT region is etched, and the threshold voltages of the first depletion-mode HEMT and the third depletion-mode HEMT are made equal and greater than the threshold voltage of the second depletion-mode HEMT by adjusting the thickness of the gate dielectric layer in the gate region of the first HEMT region, the second HEMT region, and the third HEMT region; Alternatively, H ions are injected into the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer to passivate the p-type semiconductor layers to form a depletion-mode HEMT epitaxial structure, and the threshold voltages of the first depletion-mode HEMT and the third depletion-mode HEMT are made equal and greater than the threshold voltage of the second depletion-mode HEMT by adjusting the H ion injection conditions; Alternatively, the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer are thinned to form a depletion-type HEMT epitaxial structure, and the thickness of the p-type semiconductor layers in the gate regions of the first HEMT region, the second HEMT region, and the third HEMT region are adjusted so that the threshold voltages of the first depletion-type HEMT and the third depletion-type HEMT are equal and greater than the threshold voltage of the second depletion-type HEMT.

[0034] A third aspect of an embodiment of the present invention provides a method for implementing depletion-mode devices with different threshold voltages on the same wafer, comprising: Providing an epitaxial wafer of a HEMT, the HEMT epitaxial wafer comprising a channel layer, a barrier layer and a p-type semiconductor layer stacked in sequence, and defining x electrically isolated device regions on the epitaxial wafer, the x device regions comprising y depletion-type device regions; Perform at least one of the following operations on y depletion-mode device regions to form a depletion-mode HEMT epitaxial structure, where x≥y≥2: Removing the p-type semiconductor layers of y depletion-mode device regions, and etching the gate barrier layers of the depletion-mode device regions, so that the gate barrier layers of at least two depletion-mode device regions have different thicknesses, and the thickness of the gate barrier layers corresponds to the threshold voltage of the depletion-mode HEMT; forming a gate dielectric layer in y depletion-mode device regions of the HEMT epitaxial wafer, and etching the gate dielectric layers in the gate regions of the y depletion-mode device regions so that the gate dielectric layers in the gate regions of at least two depletion-mode device regions have different thicknesses, respectively, and the thickness of the gate dielectric layer in the gate region corresponds to the threshold voltage of the depletion-mode HEMT; Performing H ion implantation on p-type semiconductor layers of y depletion-mode device regions of the HEMT epitaxial wafer to passivate the p-type semiconductor layers, and adjusting H ion implantation conditions so that the p-type semiconductor layers of at least two depletion-mode device regions have different H ion concentrations and distribution depths, and the H ion concentration and distribution depth in the p-type semiconductor layer of the gate region correspond to the threshold voltage of the depletion-mode HEMT; Thinning the p-type semiconductor layers of y depletion-mode device regions of the HEMT epitaxial wafer so that the p-type semiconductor layers of the gate regions of at least two depletion-mode device regions have different thicknesses, and the thickness of the p-type semiconductor layers of the depletion-mode device regions corresponds to the threshold voltage of the depletion-mode HEMT; Electrodes are fabricated in y depletion-mode device regions respectively to form y depletion-mode HEMTs, wherein threshold voltages of at least two depletion-mode HEMTs are different.

[0035] Furthermore, the thickness of the p-type semiconductor layer in at least one depletion-mode device region is 10 nm to 20 nm, and the thickness of the p-type semiconductor layer in at least another depletion-mode device region is 0 nm to 5 nm.

[0036] It should be noted that the threshold voltage of the depletion-mode HEMT in the embodiment of the present invention is positively correlated with the thickness of the gate region / gate barrier layer, the thickness of the gate dielectric layer, the H ion concentration / depth in the passivated p-type semiconductor layer, and the thickness of the p-type semiconductor layer in the depletion-mode HEMT.

[0037] A fourth aspect of an embodiment of the present invention provides a device obtained by the method of realizing depletion-mode devices with different threshold voltages on the same wafer.

[0038] The technical solution, its implementation process and principles, etc. will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the epitaxial growth equipment and processes, metal deposition, annealing, ion implantation, photolithography / etching and other equipment and processes used in the embodiments of the present invention are all known to those skilled in the art and are not specifically limited or described herein.

[0039] See also Fig. 9 , a comparator circuit, comprising: a first depletion-mode HEMT 401, a second depletion-mode HEMT 402, a third depletion-mode HEMT 405, a first enhancement-mode HEMT 403 and a second enhancement-mode HEMT 404, The gates of the first depletion-mode HEMT 401 and the second depletion-mode HEMT 402 are short-circuited, the source of the first depletion-mode HEMT 401 is connected to the drain of the first enhancement-mode HEMT 403, the source and gate of the second depletion-mode HEMT 402 are short-circuited and connected to the drain of the second enhancement-mode HEMT 404, the source of the first enhancement-mode HEMT 403 is connected to the drain of the third depletion-mode HEMT 405, the source of the second enhancement-mode HEMT 404 is connected to the drain of the third depletion-mode HEMT 405, The gate of the first enhancement mode HEMT 403 serves as the non-inverting input port V in+ , the gate of the second enhancement mode HEMT404 serves as the inverting input terminal V in- , the drain of the first depletion-mode HEMT 401, the drain of the second depletion-mode HEMT 402 and the supply voltage V DD The gate and source of the second depletion-mode HEMT402 are connected together as the comparator output port V out The gate of the third depletion-mode HEMT405 is connected to a DC voltage V B , source grounded; The threshold voltages of the first depletion-mode HEMT 401 and the third depletion-mode HEMT 405 are equal and greater than the threshold voltage of the second depletion-mode HEMT 402, and the threshold voltages of the first enhancement-mode HEMT 403 and the second enhancement-mode HEMT 404 are the same; Specifically, the gate width W of the first depletion-mode HEMT 401 is 401 = Gate width W of the second depletion-mode HEMT 402 402 , the gate width W of the first enhancement mode HEMT 403 403 = Gate width W of the second enhancement mode HEMT 404 404 , the gate width of the third depletion-mode HEMT405 is W 405 Specifically, W 401 =5 μm, W 403 =1000 μm, W 405 =50 μm. Specifically, the threshold voltages of the first depletion-mode HEMT 401 and the third depletion-mode HEMT 405 are -3 V to 0.2 V, and the threshold voltage of the second depletion-mode HEMT 402 is -10 V to -6 V.

[0040] The following will further explain the manufacturing process of the comparator circuit and its principles, advantages, etc. in combination with the accompanying drawings and specific implementation examples.

[0041] Example 1 A method for manufacturing a comparator circuit comprises the following steps: 1) Using metal organic vapor deposition (MOCVD) method, on Si <111> A 300 nm AlN / AlGaN transition layer structure 102 is deposited on the substrate 101, followed by an epitaxial 4 μm C-doped Al 0.07 Ga 0.93 N high resistance layer 103, 150 nm high quality low electron concentration unintentionally doped GaN layer 104, 14.5 nm AlGaN barrier layer 105, 100 nm p-type GaN layer 106, thereby forming an epitaxial wafer of an enhanced HEMT, such as Figure 4 shown.

[0042] 2) Using photoresist as a mask, after photolithography patterning, the p-GaN layer 106 in the gate region of the non-enhancement device (including the depletion-mode device region) is removed by dry etching, so that the etching stops at the AlGaN barrier layer 105; after photolithography patterning again, the AlGaN barrier layer in the gate region (i.e., the gate region, the same below) of the depletion-mode device region A is dry-etched to remove about 4 nm of the AlGaN barrier layer to form a gate groove, and the gate region of the depletion-mode device region B is not etched.

[0043] 3) Use acetone or other organic cleaning methods to remove the photoresist, and then use hydrofluoric acid (HF) to remove the oxide layer on the surface of the AlGaN barrier layer in the gate groove of the depletion-mode device A region, and quickly anneal for a period of time at 550 ° C in N2 atmosphere to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction.

[0044] 4) Ni / Au is deposited in the gate regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first gate 107A and a second gate 107B of Schottky gate contact are prepared, such as Figure 5 As shown, Ti / Al / Ti / Au is deposited on the source and drain regions of the depletion-type device A region and the depletion-type device B region, respectively, and after annealing, a first source 108A, a second source 108B, a first drain 109A, and a second drain 109B are prepared into ohmic contacts, as shown in FIG. Figure 6 As shown, the first gate 107A, the first source 108A, the first drain 109A and the depletion-type device A region of the epitaxial wafer constitute a depletion-type transistor A with a high threshold voltage, and the second gate 107B, the second source 108B, the second drain 109B and the depletion-type device B region of the epitaxial wafer constitute a depletion-type transistor B with a low threshold voltage. The basic characteristics of the device are tested using a probe station and a semiconductor parameter analyzer. The threshold voltage of the depletion-type transistor A is -0.8 V, and the threshold voltage of the depletion-type transistor B is -3 V.

[0045] 5) Referring to the above process, other depletion-mode transistors are manufactured on the same epitaxial wafer, and enhancement-mode transistors are manufactured on the same epitaxial wafer using a process known in the art, and an enhancement-mode transistor with a single threshold voltage and a depletion-mode transistor with a dual threshold voltage are obtained. Specifically, two depletion-mode transistors A are used as the first depletion-mode HEMT 401 and the third depletion-mode HEMT 405, respectively, and the depletion-mode transistor B is used as the second depletion-mode HEMT 402. The first enhancement-mode HEMT 403 and the second enhancement-mode HEMT 404 adopt a conventional p-GaN HEMT structure, thereby obtaining the following Fig. 9 The comparator (DV TH,D ).

[0046] It should be noted that the device isolation and the manufacturing process of the enhancement mode transistor omitted in the above embodiments are all known in the art and are not limited here.

[0047] Example 2 A method for manufacturing a comparator circuit comprises the following steps: 1) Using metal organic vapor deposition (MOCVD) method, on Si <111> A 300 nm AlN / AlGaN transition layer structure 202 is deposited on the substrate 201, followed by an epitaxial 4 μm C-doped Al 0.07 Ga 0.93 N high resistance layer 203, 150 nm high quality and low electron concentration unintentionally doped GaN layer 204, 14.5 nm AlGaN barrier layer 205, 100 nm p-type GaN layer 206, thereby forming an epitaxial wafer of an enhanced HEMT.

[0048] 2) Using photoresist as a mask, after photolithography patterning, the p-GaN layer 206 in the gate region of the non-enhancement device (including the depletion-mode device region) is removed by dry etching, so that the etching stops at the AlGaN barrier layer 205; after photolithography patterning again, the AlGaN barrier layer in the gate region (i.e., the gate region, the same below) of the depletion-mode device region A is dry-etched to remove about 4 nm of the AlGaN barrier layer to form a gate groove, and the gate region of the depletion-mode device region B is not etched.

[0049] 3) Use acetone or other organic cleaning methods to remove the photoresist, and then use hydrofluoric acid (HF) to remove the oxide layer on the surface of the AlGaN barrier layer in the gate groove of the depletion-mode device A region, and quickly anneal for a period of time at 550 ° C in N2 atmosphere to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction.

[0050] 4) Use low pressure chemical vapor deposition (LPCVD) process to deposit 20 nm SiN on the surface of the epitaxial wafer xThe dielectric layer 207 is etched by reactive ion etching (RIE) and buffer (BOE) to remove the SiN in the gate region groove of the enhancement device region and the depletion device A region. x Dielectric layer 207 .

[0051] 5) Ni / Au is deposited on the gate region of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first gate 208A and a second gate 208B with Schottky gate contact are prepared; Ti / Al / Ti / Au is deposited on the source and drain regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first source 209A, a second source 209B, a first drain 210A, and a second drain 210B with ohmic contact are prepared, as shown in FIG. Figure 7 As shown, the first gate 208A, the first source 209A, the first drain 210A and the depletion-type device A region of the epitaxial wafer constitute a depletion-type transistor A with a high threshold voltage, and the second gate 208B, the second source 209B, the second drain 210B and the depletion-type device B region of the epitaxial wafer constitute a depletion-type transistor B with a low threshold voltage. The basic characteristics of the device are tested using a probe station and a semiconductor parameter analyzer. The threshold voltage of the depletion-type transistor A is -0.8 V, and the threshold voltage of the depletion-type transistor B is -6 V.

[0052] 6) Referring to the above process, other depletion-mode transistors are manufactured on the same epitaxial wafer, and enhancement-mode transistors are manufactured on the same epitaxial wafer using a process known in the art, and an enhancement-mode transistor with a single threshold voltage and a depletion-mode transistor with a dual threshold voltage are obtained. Specifically, two depletion-mode transistors A are used as the first depletion-mode HEMT 401 and the third depletion-mode HEMT 405, respectively, and the depletion-mode transistor B is used as the second depletion-mode HEMT 402. The first enhancement-mode HEMT 403 and the second enhancement-mode HEMT 404 adopt a conventional p-GaN HEMT structure, thereby obtaining the following Fig. 9 The comparator (DV TH,D ).

[0053] Example 3 A method for manufacturing a comparator circuit comprises the following steps: 1) Using metal organic vapor deposition (MOCVD) method, on Si <111> A 300 nm AlN / AlGaN transition layer structure 302 is deposited on the substrate 301, followed by an epitaxial 4 μm C-doped Al 0.07 Ga 0.93 N high resistance layer 303, 150 nm high quality and low electron concentration unintentionally doped GaN layer 304, 14.5 nm AlGaN barrier layer 305, 100 nm p-type GaN layer 306, thereby forming an epitaxial wafer of an enhanced HEMT.

[0054] 2) Using photoresist as a mask, after photolithography patterning, the p-GaN layer 306 in the gate region of the non-enhancement device (including the depletion mode device region) is removed by dry etching, so that the etching stops at the AlGaN barrier layer 305.

[0055] 3) The photoresist is removed by an organic cleaning method such as acetone, and then the oxide layer on the surface of the AlGaN barrier layer 305 is removed by using hydrofluoric acid (HF) or the like, and rapid annealing is performed at 550° C. in a N2 atmosphere for a period of time to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction.

[0056] 4) Then, a 20 nm SiNx dielectric layer 307 is deposited on the entire surface of the epitaxial wafer by a low pressure chemical vapor deposition (LPCVD) process, and the SiNx dielectric layer 307 in the enhancement mode device region and the depletion mode device A region is removed by reactive ion etching (RIE) and buffer solution (BOE) etching.

[0057] 5) Ni / Au is deposited on the gate region of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first gate 308A and a second gate 308B with Schottky gate contact are prepared; Ti / Al / Ti / Au is deposited on the source and drain regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first source 309A, a second source 309B, a first drain 310A, and a second drain 310B with ohmic contact are prepared, as shown in FIG. Figure 8 As shown, the first gate 308A, the first source 309A, the first drain 310A and the depletion-type device A region of the epitaxial wafer constitute a depletion-type transistor A with a high threshold voltage, and the second gate 308B, the second source 309B, the second drain 310B and the depletion-type device B region of the epitaxial wafer constitute a depletion-type transistor B with a low threshold voltage. The basic characteristics of the device are tested using a probe station and a semiconductor parameter analyzer. The threshold voltage of the depletion-type transistor A is -3 V, and the threshold voltage of the depletion-type transistor B is -6 V.

[0058] 6) Referring to the above process, other depletion-mode transistors are manufactured on the same epitaxial wafer, and enhancement-mode transistors are manufactured on the same epitaxial wafer using a process known in the art, and an enhancement-mode transistor with a single threshold voltage and a depletion-mode transistor with a dual threshold voltage are obtained. Specifically, two depletion-mode transistors A are used as the first depletion-mode HEMT 401 and the third depletion-mode HEMT 405, respectively, and the depletion-mode transistor B is used as the second depletion-mode HEMT 402. The first enhancement-mode HEMT 403 and the second enhancement-mode HEMT 404 adopt a conventional p-GaN HEMT structure, thereby obtaining the following Fig. 9 The comparator (DV TH,D ).

[0059] Comparative Example The comparator in the comparative example (SV TH,D ) has the same structure and device size as the comparators in Example 1, Example 2, and Example 3, except that the structures of the first depletion-mode HEMT 401, the second depletion-mode HEMT 402, and the third depletion-mode HEMT 405 in the comparative example are the same as those of the depletion-mode transistor B in Example 2, and the threshold voltage is -6V, which is recorded as the comparative example comparator.

[0060] The comparators in Example 1, Example 2, Example 3 and the comparative example were tested for static and dynamic electrical characteristics using a probe station, a voltage source meter, a signal generator and an oscilloscope. The test results are shown in Figure 1. Fig.10 and Fig.11 , Fig.12 and Fig.13 , Fig.14 and Fig.15 shown.

[0061] Depend on Fig.10 and Fig.11 It can be seen that the voltage comparison of the comparator using the dual-threshold depletion-type HEMT in Example 1 is more accurate, the voltage comparison range is increased by 69%, the output low level is reduced by 50%, the circuit output level is converted from low level to high level, the charging speed through the second depletion-type HEMT 402 is slightly reduced, and the rise time is slightly increased. This is because the third depletion-type HEMT 405 in Example 1 is easier to enter the saturation state when working, which increases the voltage comparison range. The second depletion-type HEMT 402 works in a larger current state to ensure the charging speed of the load.

[0062] By 12 and Fig.13 It can be seen that the voltage comparison of the dual-threshold depletion-type HEMT comparator in Example 2 is more accurate, the voltage comparison range is increased by 69%, and the output low level is reduced by 21%. The circuit output level is converted from low level to high level, and the charging speed through the second depletion-type HEMT 402 remains unchanged, and the rise time is the same.

[0063] Depend on Fig.14 and Fig.15 It can be seen that the voltage comparison of the comparator using the dual-threshold depletion-type HEMT in Example 3 is more accurate, the voltage comparison range is increased by 47%, and the output low level is reduced by 13%. The output level of the circuit is converted from a low level to a high level, and the charging speed through the second depletion-type HEMT remains unchanged, and the rise time is the same.

[0064] Example 4 The manufacturing method of a comparator circuit in this embodiment is basically the same as that in Embodiment 1, except that the method of forming a depletion-type transistor A and a depletion-type transistor B on the same epitaxial wafer in this embodiment is different. Only the main differences between this embodiment and Embodiment 1 will be described below, and the same parts between the two will not be repeated.

[0065] 1) Using metal organic vapor deposition (MOCVD) method, on Si <111> A 300 nm AlN / AlGaN transition layer structure 502 is deposited on the substrate 501, followed by an epitaxial 4 μm C-doped Al 0.07 Ga 0.93 N high resistance layer 503, 150 nm high quality and low electron concentration unintentionally doped GaN layer 504, 14.5 nm AlGaN barrier layer 505, 100 nm p-type GaN layer 506, thereby forming an epitaxial wafer of an enhancement mode HEMT.

[0066] 2) Using photoresist as a mask, after photolithography patterning, the p-type GaN layer 506 outside the gate region of the depletion-type device A region is removed by dry etching, and the etching stops at the AlGaN barrier layer 505. After photolithography is performed to pattern the gate region of the depletion-type device A region, H ions are implanted into the p-type GaN layer 506 by an ion implantation process, with an implantation energy of 20 KeV and an implantation dose of 1.5E13 cm -2 , to passivate the p-GaN layer 506, so that the p-GaN layer 506 loses or greatly reduces its ability to deplete 2DEG, and the H ion implantation conditions are controlled to obtain depletion-mode devices with different threshold voltages.

[0067] 3) Use acetone or other organic cleaning methods to remove the photoresist, and quickly anneal at 500 °C in N2 atmosphere for a period of time to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction.

[0068] 4) Then, a 20 nm thick SiNx dielectric layer 507 is deposited on the entire surface of the epitaxial wafer by a low pressure chemical vapor deposition (LPCVD) process, and the SiNx dielectric layer 507 covering the p-type GaN layer 506 is removed by reactive ion etching (RIE) and buffer (BOE) etching.

[0069] 5) Ni / Au is deposited on the gate regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first gate 508A and a second gate 508B are prepared to form Schottky gate contacts. The first gate 508A is arranged on the passivated p-type GaN layer 506, and the second gate 508B is arranged on the SiNx dielectric layer 507. Ti / Al / Ti / Au is deposited on the source and drain regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first source 509A, a second source 509B, a first drain 510A, and a second drain 510B are prepared to form ohmic contacts, as shown in FIG. Figure 8 As shown, the first gate 508A, the first source 509A, the first drain 510A and the depletion-type device A region of the epitaxial wafer constitute a depletion-type transistor A with a high threshold voltage, and the second gate 508B, the second source 509B, the second drain 510B and the depletion-type device B region of the epitaxial wafer constitute a depletion-type transistor B with a low threshold voltage, as shown in FIG. Fig.15 shown.

[0070] Example 5 The manufacturing method of a comparator circuit in this embodiment is basically the same as that in Embodiment 1, except that the method of forming a depletion-type transistor A and a depletion-type transistor B on the same epitaxial wafer in this embodiment is different. Only the main differences between this embodiment and Embodiment 1 will be described below, and the same parts between the two will not be repeated.

[0071] 1) Using metal organic vapor deposition (MOCVD) method, on Si <111> A 300 nm AlN / AlGaN transition layer structure 602 is deposited on the substrate 601, followed by an epitaxial 4 μm C-doped Al 0.07 Ga 0.93 N high resistance layer 603, 150 nm high quality and low electron concentration unintentionally doped GaN layer 604, 14.5 nm AlGaN barrier layer 605, 100 nm p-type GaN layer 606, thereby forming an epitaxial wafer of an enhanced HEMT.

[0072] 2) Using a photoresist as a mask, after photolithography patterning, the p-type GaN layer 606 outside the gate region of the depletion-mode device A region is removed by dry etching, so that the etching stops at the AlGaN barrier layer 605, and after photolithography is performed to pattern the gate region of the depletion-mode device A region, the p-type GaN layer 606 of the depletion-mode device A region is etched again, and only 10 nm to 20 nm of the p-type GaN layer 606 of the depletion-mode device A region remains. The remaining p-type GaN layer 606 cannot deplete the 2DEG under the gate. By further controlling the remaining thickness of the p-type GaN layer 606 (0 to 5 nm), depletion-mode transistors with different threshold voltages can be prepared.

[0073] 3) Use acetone or other organic cleaning methods to remove the photoresist, and quickly anneal at 500 °C in N2 atmosphere for a period of time to restore the two-dimensional electron gas at the AlGaN / GaN heterojunction.

[0074] 4) Then, a 20 nm SiNx dielectric layer 607 is deposited on the entire surface of the epitaxial wafer by a low pressure chemical vapor deposition (LPCVD) process, and the SiNx dielectric layer 607 covering the p-type GaN layer 606 is removed by reactive ion etching (RIE) and buffer (BOE) etching.

[0075] 6) Ni / Au is deposited on the gate regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first gate 608A and a second gate 608B are prepared to form Schottky gate contacts. The first gate 608A is disposed on the passivated p-type GaN layer 606, and the second gate 608B is disposed on the SiNx dielectric layer 607. Ti / Al / Ti / Au is deposited on the source and drain regions of the depletion-type device A region and the depletion-type device B region respectively, and after annealing, a first source 609A, a second source 609B, a first drain 610A, and a second drain 610B are prepared to form ohmic contacts, as shown in FIG. Figure 8 As shown, the first gate 608A, the first source 609A, the first drain 610A and the depletion-type device A region of the epitaxial wafer constitute a depletion-type transistor A with a high threshold voltage, and the second gate 608B, the second source 609B, the second drain 610B and the depletion-type device B region of the epitaxial wafer constitute a depletion-type transistor B with a low threshold voltage, as shown in FIG. Fig.16 shown.

[0076] It should be noted that the size of each transistor in the comparator of the above scheme is not limited to that shown above, and can be scaled in the same proportion without affecting the voltage comparison range of the comparator.

[0077] An embodiment of the present invention provides a novel comparator circuit based on a high and low threshold voltage depletion-mode HEMT, which provides a method for preparing depletion-mode devices with different threshold voltages and demonstrates its improvement on comparator performance.

[0078] The present invention realizes wafer-level preparation of high and low threshold voltage devices by changing the thickness of the barrier layer in the gate region of the device or whether to add a dielectric layer. The application of devices with different threshold voltages in a GaN monolithic integrated comparator circuit can significantly improve its performance. It should be pointed out that the implementation method of the present invention can be to control the thickness of the AlGaN barrier layer in the gate region to prepare a depletion-type HEMT; or it can be to not change the thickness of the AlGaN barrier layer in the gate region and deposit a dielectric layer such as silicon nitride to prepare a MIS gate HEMT.

[0079] It should also be pointed out that the comparator in the invention is only one type of integrated circuit, and the dual-threshold depletion-mode HEMT can also be used in various types of circuits.

[0080] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A comparator circuit having high switching speed, high voltage comparison range and high precision, characterized in that: include: a first depletion-mode HEMT (401), a second depletion-mode HEMT (402), a third depletion-mode HEMT (405), a first enhancement-mode HEMT (403) and a second enhancement-mode HEMT (404), The gates of the first depletion-mode HEMT (401) and the second depletion-mode HEMT (402) are short-connected, the source of the first depletion-mode HEMT (401) is connected to the drain of the first enhancement-mode HEMT (403), the source and gate of the second depletion-mode HEMT (402) are short-connected and connected to the drain of the second enhancement-mode HEMT (404), the source of the first enhancement-mode HEMT (403) is connected to the drain of the third depletion-mode HEMT (405), and the source of the second enhancement-mode HEMT (404) is connected to the drain of the third depletion-mode HEMT (405), The gate of the first enhancement-mode HEMT (403) serves as a non-inverting input port, the gate of the second enhancement-mode HEMT (404) serves as an inverting input port, the drain of the first depletion-mode HEMT (401) and the drain of the second depletion-mode HEMT (402) are connected to a supply voltage, the gate and source of the second depletion-mode HEMT (402) serve as comparator output ports at the same time, and the gate of the third depletion-mode HEMT (405) is connected to a DC voltage and the source is grounded; The threshold voltages of the first depletion-mode HEMT (401) and the third depletion-mode HEMT (405) are equal and greater than the threshold voltage of the second depletion-mode HEMT (402), and the threshold voltages of the first enhancement-mode HEMT (403) and the second enhancement-mode HEMT (404) are the same.

2. The comparator circuit with high switching speed, high voltage comparison range and high precision according to claim 1, characterized in that: The threshold voltages of the first depletion-mode HEMT (401) and the third depletion-mode HEMT (405) are between -3 V and 0.2 V, and the threshold voltage of the second depletion-mode HEMT (402) is between -10 V and -6 V.

3. The comparator circuit with high switching speed, high voltage comparison range and high precision according to claim 1, characterized in that: The gate width W of the first depletion-mode HEMT (401) 401 = Gate width W of the second depletion-mode HEMT (402) 402 , the gate width W of the first enhancement mode HEMT (403) 403 = Gate width W of the second enhancement mode HEMT (404) 404 , the gate width of the third depletion-mode HEMT (405) is W 405 , where W 401 / W 403 / W 405 = 5 / 1000 / 50.

4. The comparator circuit with high switching speed, high voltage comparison range and high precision according to claim 1, characterized in that: The first depletion-mode HEMT (401), the second depletion-mode HEMT (402), the third depletion-mode HEMT (405), the first enhancement-mode HEMT (403), and the second enhancement-mode HEMT (404) are monolithically integrated on the same wafer.

5. The comparator circuit with high switching speed, high voltage comparison range and high precision according to claim 1 or 4, characterized in that: The epitaxial structures of the first depletion-type HEMT (401), the second depletion-type HEMT (402), and the third depletion-type HEMT (405) all comprise a channel layer and a barrier layer which are stacked, the thickness of the gate barrier layer of the first depletion-type HEMT (401) being different from the thickness of the gate barrier layer of the second depletion-type HEMT (402) and being the same as the thickness of the gate barrier layer of the third depletion-type HEMT (405); Alternatively, the epitaxial structures of the first depletion-mode HEMT (401), the second depletion-mode HEMT (402), and the third depletion-mode HEMT (405) all comprise a stacked channel layer and a barrier layer, and a gate dielectric layer is provided on the barrier layer, and the thickness of the gate dielectric layer in the gate region of the first depletion-mode HEMT (401) is different from the thickness of the gate dielectric layer in the gate region of the second depletion-mode HEMT (402) and is the same as the thickness of the gate dielectric layer in the gate region of the third depletion-mode HEMT (405); Alternatively, the epitaxial structures of the first depletion-mode HEMT (401), the second depletion-mode HEMT (402), and the third depletion-mode HEMT (405) all comprise a stacked channel layer, a barrier layer, and a p-type semiconductor layer, the p-type semiconductor layer being passivated by injecting H ions, the concentration and distribution depth of H ions in the p-type semiconductor layer in the gate region of the first depletion-mode HEMT (401) being different from the concentration and distribution depth of H ions in the p-type semiconductor layer in the gate region of the second depletion-mode HEMT (402) and being the same as the concentration and distribution depth of H ions in the p-type semiconductor layer in the gate region of the third depletion-mode HEMT (405); Alternatively, the epitaxial structures of the first depletion-type HEMT (401), the second depletion-type HEMT (402), and the third depletion-type HEMT (405) include a channel layer, a barrier layer, and a p-type semiconductor layer that are stacked, the thickness of the p-type semiconductor layer in the gate region of the first depletion-type HEMT (401) being different from the thickness of the p-type semiconductor layer in the gate region of the second depletion-type HEMT (402) and being the same as the thickness of the p-type semiconductor layer in the gate region of the third depletion-type HEMT (405), Preferably, the thickness of the p-type semiconductor layer in the gate region of the first depletion-mode HEMT (401) and the third depletion-mode HEMT (405) is 10 nm to 20 nm, and the thickness of the p-type semiconductor layer in the gate region of the second depletion-mode HEMT (402) is 0 nm to 5 nm.

6. A method for manufacturing a comparator circuit having high switching speed, high voltage comparison range and high precision as claimed in any one of claims 1 to 5, characterized in that: include: providing a HEMT epitaxial wafer, on which a first HEMT region, a second HEMT region, a third HEMT region, a fourth HEMT region and a fifth HEMT region are defined; Processing the epitaxial wafers of the first HEMT region, the second HEMT region, and the third HEMT region to form an electrically isolated depletion-type HEMT epitaxial structure, manufacturing electrodes matching the depletion-type HEMT epitaxial structure, forming a first depletion-type HEMT (401), a second depletion-type HEMT (402), and a third depletion-type HEMT (405) in the first HEMT region, the second HEMT region, and the third HEMT region, respectively, and making the threshold voltages of the first depletion-type HEMT (401) and the third depletion-type HEMT (405) equal and greater than the threshold voltage of the second depletion-type HEMT (402) by at least one of the following methods; Mode 1: The depletion-type HEMT epitaxial structure includes a stacked channel layer and a barrier layer, and the thickness of the gate barrier layer in the first HEMT region, the second HEMT region, and the third HEMT region is adjusted; Mode 2: The depletion-type HEMT epitaxial structure includes a stacked channel layer and a barrier layer, and a gate dielectric layer is provided on the surface of the depletion-type HEMT epitaxial structure, and the thickness of the gate dielectric layer in the gate region of the first HEMT region, the second HEMT region, and the third HEMT region is adjusted; Mode 3: The depletion-mode HEMT epitaxial structure includes a stacked channel layer, a barrier layer, and a p-type semiconductor layer, and H ions are injected into at least the gate region p-type semiconductor layer of the first HEMT region, the second HEMT region, and the third HEMT region to passivate the p-type semiconductor layer, and the conditions for H ion injection are adjusted; Mode 4: The depletion-mode HEMT epitaxial structure includes a stacked channel layer, a barrier layer and a p-type semiconductor layer, and at least the thickness of the gate region p-type semiconductor layer of the first HEMT region, the second HEMT region and the third HEMT region is adjusted; Preferably, the thickness of the p-type semiconductor layer in the first HEMT region and the third HEMT region is 10 nm to 20 nm, and the thickness of the p-type semiconductor layer in the gate region of the second depletion-mode HEMT (402) is 0 nm to 5 nm; The epitaxial wafers of the fourth HEMT region and the fifth HEMT region are processed to form an enhanced HEMT epitaxial structure with the same structure and electrical isolation, and electrodes matching the enhanced HEMT epitaxial structure are manufactured to form a first enhanced HEMT (403) and a second enhanced HEMT (404) in the fourth HEMT region and the fifth HEMT region, respectively, and the threshold voltages of the first enhanced HEMT (403) and the second enhanced HEMT (404) are made the same.

7. The method for manufacturing a comparator circuit having high switching speed, high voltage comparison range and high precision according to claim 6, characterized in that: The HEMT epitaxial wafer includes a channel layer, a barrier layer and a p-type semiconductor layer stacked in sequence, and the manufacturing method specifically includes: Removing the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer to form a depletion-type HEMT epitaxial structure, and etching at least one of the gate barrier layer of the first HEMT region, the second HEMT region, and the third HEMT region, and adjusting the thickness of the gate barrier layer of the first HEMT region, the second HEMT region, and the third HEMT region so that the threshold voltages of the first depletion-type HEMT (401) and the third depletion-type HEMT (405) are equal and greater than the threshold voltage of the second depletion-type HEMT (402); Alternatively, the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer are removed to form a depletion-type HEMT epitaxial structure, a gate dielectric layer is formed at least in the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer, and at least the gate dielectric layer of the gate region of at least one of the first HEMT region, the second HEMT region, and the third HEMT region is etched, and the threshold voltages of the first depletion-type HEMT (401) and the third depletion-type HEMT (405) are made equal and greater than the threshold voltage of the second depletion-type HEMT (402) by adjusting the thickness of the gate dielectric layer of the gate region of the first HEMT region, the second HEMT region, and the third HEMT region; Alternatively, H ions are injected into the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer to passivate the p-type semiconductor layers to form a depletion-type HEMT epitaxial structure, and by adjusting the H ion injection conditions, the threshold voltages of the first depletion-type HEMT (401) and the third depletion-type HEMT (405) are equal and greater than the threshold voltage of the second depletion-type HEMT (402); Alternatively, the p-type semiconductor layers of the first HEMT region, the second HEMT region, and the third HEMT region of the HEMT epitaxial wafer are thinned to form a depletion-type HEMT epitaxial structure, and the thickness of the p-type semiconductor layers in the gate regions of the first HEMT region, the second HEMT region, and the third HEMT region are adjusted so that the threshold voltages of the first depletion-type HEMT (401) and the third depletion-type HEMT (405) are equal and greater than the threshold voltage of the second depletion-type HEMT (402).

8. A method for realizing depletion-mode devices with different threshold voltages on the same wafer, characterized in that: include: Providing an epitaxial wafer of a HEMT, the HEMT epitaxial wafer comprising a channel layer, a barrier layer and a p-type semiconductor layer stacked in sequence, and defining x electrically isolated device regions on the epitaxial wafer, the x device regions comprising y depletion-type device regions; Perform at least one of the following operations on y depletion-mode device regions to form a depletion-mode HEMT epitaxial structure, where x≥y≥2: Removing the p-type semiconductor layers of y depletion-mode device regions, and etching the gate barrier layers of the depletion-mode device regions, so that the gate barrier layers of at least two depletion-mode device regions have different thicknesses, and the thickness of the gate barrier layers corresponds to the threshold voltage of the depletion-mode HEMT; forming a gate dielectric layer in y depletion-mode device regions of the HEMT epitaxial wafer, and etching the gate dielectric layers in the gate regions of the y depletion-mode device regions so that the gate dielectric layers in the gate regions of at least two depletion-mode device regions have different thicknesses, respectively, and the thickness of the gate dielectric layer in the gate region corresponds to the threshold voltage of the depletion-mode HEMT; Performing H ion implantation on p-type semiconductor layers of y depletion-mode device regions of the HEMT epitaxial wafer to passivate the p-type semiconductor layers, and adjusting H ion implantation conditions so that the p-type semiconductor layers of at least two depletion-mode device regions have different H ion concentrations and distribution depths, and the H ion concentration and distribution depth in the p-type semiconductor layer of the gate region correspond to the threshold voltage of the depletion-mode HEMT; Thinning the p-type semiconductor layers of y depletion-mode device regions of the HEMT epitaxial wafer so that the p-type semiconductor layers of the gate regions of at least two depletion-mode device regions have different thicknesses, and the thickness of the p-type semiconductor layers of the depletion-mode device regions corresponds to the threshold voltage of the depletion-mode HEMT; Electrodes are fabricated in y depletion-mode device regions respectively to form y depletion-mode HEMTs, wherein threshold voltages of at least two depletion-mode HEMTs are different.

9. The method for realizing depletion-mode devices with different threshold voltages on the same wafer according to claim 8, characterized in that: The thickness of the p-type semiconductor layer in at least one depletion-type device region is 10 nm to 20 nm, and the thickness of the p-type semiconductor layer in at least another depletion-type device region is 0 nm to 5 nm.

10. A device obtained by the method of realizing depletion-mode devices with different threshold voltages on the same wafer as claimed in claim 8 or 9.

Images