Comparator and power supply tube-based negative single-particle transient reinforcing circuit and method
By designing a negative single-particle transient reinforcement circuit based on comparator and power supply tube in the bandgap reference circuit, the output voltage affected by the single-particle transient effect is adjusted in real time, the problem of unstable output voltage is solved, and the circuit reinforcement and stability of the output voltage are achieved.
Patent Information
- Application Number
- CN202411819565.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-04
AI Technical Summary
In the prior art, the bandgap reference circuit is susceptible to the single-particle transient effect, resulting in unstable output voltage.
A negative single-particle transient reinforcement circuit based on a comparator and power supply tube is designed. The comparator adjusts the BGR output voltage Vref after being affected by the single-particle transient effect to reinforcing the circuit and ensuring that the output voltage is stable within a certain range.
Effectively resist the single-particle transient effect, ensure the stability of the output voltage, and avoid circuit damage and performance degradation caused by the single-particle transient effect.
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Figure CN119766222A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of negative single particle transient reinforcement circuits, and in particular to a negative single particle transient reinforcement circuit and method based on a comparator and a power supply tube. Background Art
[0002] Particle transient effects are caused by the energy transfer of particles to electrons in the medium. When a particle (such as an electron or photon) passes through a medium, it interacts with atoms or molecules in the medium, causing electrons to be excited or stripped from their atomic orbitals. These excited or ionized states exist only for a moment and decay rapidly. In this process, holes are formed, which move in the surrounding medium until they recombine with other electrons. The time scale of this recombination process is shorter than the time scale of the interaction between the electron and the medium, so it can be considered that all electrons recombine simultaneously in a period of time. Single particle transient effects can be used to develop highly sensitive single particle sensors. By combining sensitive media with electronic detectors, when particles pass through the medium and cause transient effects, this signal can be captured by the electronic detector. This single particle sensor can be used in environmental monitoring, life science research and other fields; single particle transient effects can be used to evaluate the reliability of electronic devices. In electronic devices, single particle transient effects may cause misoperation or device damage, so it is very important for the reliability evaluation of electronic devices. Through simulation or experiment, the response of electronic devices under single particle transient effects can be studied, and the resistance of Apple devices to particle radiation can be studied, thereby guiding the design and manufacture of electronic devices.
[0003] Single Event Transient (SET) is caused by high-energy charged particles bombarding semiconductor devices, ionizing electron-hole pairs along the particle trajectory. These carriers are transported by charge diffusion and drift under the action of the electric field. The process of charge transport causes current transients in the device, resulting in sudden fluctuations in current and voltage. It is a single particle effect. When SET pulses propagate in the circuit, they will affect the performance of the circuit and may even damage the circuit and cause it to malfunction. With the development of semiconductor manufacturing technology, the reduction of process size has made the charge required for the device to SET less, making the circuit more sensitive to SET.
[0004] In analog circuits, the bandgap reference (BandGapReference, BGR) can provide the circuit with a stable reference voltage that is not affected by temperature. Due to its simple structure and low noise, it is widely used in application environments such as space exploration and high-energy physics experiments.
[0005] The BGR circuit uses the voltage proportional to the temperature coefficient and the voltage inversely proportional to the temperature coefficient in the semiconductor device to linearly superpose to obtain a reference voltage with an approximate zero temperature coefficient. The BGR circuit can provide a stable voltage or current output and reduce the influence of temperature on circuit performance. However, it can be seen from research literature and heavy ion experiments that the bandgap reference is very susceptible to SET, so it is necessary to design a negative single-particle transient reinforcement circuit based on a comparator and a power supply tube. Summary of the invention
[0006] The present application provides a negative single-particle transient reinforcement circuit and method based on a comparator and a power supply tube to solve the problem of unstable output voltage in the prior art, and realizes real-time adjustment of the Vref voltage output by the BGR after being SET, which can effectively reinforce the circuit and stabilize the output voltage within a certain range.
[0007] The present application provides a negative single-particle transient reinforcement circuit based on a comparator and a power supply tube, wherein the negative single-particle transient reinforcement circuit includes a comparator, a resistor network, a pass transistor, a power supply transistor and a capacitor;
[0008] The positive input terminal of the comparator is connected to the BGR output terminal, the negative input terminal of the comparator is connected to the resistor network, and the output terminal of the comparator is connected to the gate of the pass transistor and the gate of the power supply transistor;
[0009] The drain of the pass transistor is connected to the positive input terminal of the comparator, the source of the pass transistor is connected to one end of the capacitor, the source of the power supply transistor and the voltage output terminal, and the other end of the capacitor is grounded;
[0010] The drain of the power supply transistor is connected to the negative input terminal of the comparator.
[0011] Preferably, the resistor network is formed by a plurality of resistors connected in series, and the resistor network is grounded, and the plurality of resistors include a fifth resistor, a sixth resistor, and an Nth resistor RN (N is an integer greater than 5).
[0012] Preferably, the comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit, and the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.
[0013] Preferably, the first-stage differential amplifier circuit includes a second transistor, a first differential input transistor, a second differential input transistor, a first load tube, a second load tube, a first reset tube and a second reset tube. The source of the second transistor is grounded, and the gate is connected to the gate of the eighth transistor in the bias circuit. The drain of the second transistor is respectively connected to the source of the first differential input transistor and the source of the second differential input transistor. The drain of the first differential input transistor is respectively connected to the drain of the first load tube and the drain of the first reset tube; the drain of the second differential input transistor is respectively connected to the drain of the second reset tube and the drain of the second load tube.
[0014] Preferably, the second-stage differential-to-single-ended output circuit comprises a third transistor, a third differential input transistor, a fourth differential input transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a third load transistor, a fourth load transistor, a fifth load transistor, a sixth load transistor, a third reset transistor and a fourth reset transistor, the gate of the third transistor is connected to the gate of the eighth transistor, the source of the third transistor is grounded, and the drain of the third transistor is respectively connected to the source of the third differential input transistor and the source of the fourth differential input transistor;
[0015] The drain of the third differential input transistor is connected to the drain of the fifth load transistor, the drain of the fourth differential input transistor is connected to the drain of the fourth load transistor, the gate of the third differential input transistor is respectively connected to the drain of the third load transistor and the drain of the sixth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the drain of the fourth transistor;
[0016] The drain of the fourth differential input transistor is respectively connected to the drain of the fourth load transistor and the drain of the fourth reset transistor, the gate of the fourth differential input transistor is respectively connected to the drain of the fourth load transistor and the drain of the seventh transistor, the source of the seventh transistor is grounded, and the drain of the seventh transistor is also connected to the drain of the fifth transistor;
[0017] The gate electrode of the fifth load tube is connected to the gate electrode of the sixth load tube and to the drain electrode of the third reset tube.
[0018] Preferably, the output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor.
[0019] Preferably, the bias circuit includes a fifth reset tube, a first transistor and an eighth transistor, a fourth resistor, a first resistor, a second resistor and a third resistor connected in series are connected between the drain of the fifth reset tube and the drain of the eighth transistor, the source of the eighth transistor is grounded, the drain of the first transistor is connected to the drain of the eighth transistor, and the source of the first transistor is grounded.
[0020] Preferably, a method for reinforcing a negative single event transient reinforcement circuit based on a comparator and a power supply tube comprises the following steps:
[0021] A. After BGR is affected by the double exponential current source, its output voltage Vref will produce a positive voltage change;
[0022] B. Negative single-particle transient reinforcement circuit First, the comparator reference voltage value Vcmp is modified through the resistor network, and a pulse voltage value Vpilse is given so that the comparator is always in a real-time comparison state;
[0023] C. The output voltage Vcmp_op of the comparator is obtained according to the change of Vref and Vcmp, and Vcmp_op outputs the voltage through the transistor;
[0024] D. Vcmp_op controls the opening and closing of PassTransistor. When Vref is greater than Vcmp, the power supply transistor is turned off. At the same time, the power supply transistor is turned on. At this time, the output voltage of Final_op is Vcmp. When Vref is greater than Vcmp, the power supply transistor is turned on. The output voltage of Final_op is Vref. Capacitor C1 is used to reduce the influence of pulse voltage Vpulse on the output.
[0025] Beneficial effect: The negative single-particle transient reinforcement circuit based on the comparator and the power supply tube of the present invention adjusts the Vref voltage output by the BGR after SET in real time based on the comparator, and Vcmp_op controls the opening and closing of the PassTransistor. When Vref is greater than Vcmp, the PassTransistor is closed, and at the same time, the power supply transistor PumpTransistor is opened. At this time, the output voltage of Final_op is Vcmp. When Vref is greater than Vcmp, the PassTransistor is opened, and the output voltage of Final_op is Vref, which can effectively reinforce the circuit and stabilize the output voltage within a certain range.
[0026] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0028] Figure 1 This is a schematic diagram of the negative single particle transient reinforcement circuit of the present invention;
[0029] Figure 2 is a schematic diagram of a comparator of the present invention;
[0030] Figure 3 It is a BGR circuit diagram in the prior art;
[0031] Figure 4 Analyze the graph for unreinforced sensitive nodes;
[0032] Figure 5 This is the simulation result diagram of the reinforced circuit. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions.
[0035] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0036] In addition, the terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.
[0037] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, the "connection" or "connection" of a mechanical structure may refer to a physical connection. For example, the physical connection may be a fixed connection, such as a fixed connection through a fixing member, such as a fixed connection through a screw, bolt or other fixing member; the physical connection may also be a detachable connection, such as a mutual snap-on or snap-fit connection; the physical connection may also be an integral connection, such as a connection formed by welding, bonding or integral molding. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0038] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.
[0039] See also Figure 1-Figure 2 , the present application discloses a negative single particle transient reinforcement circuit based on a comparator and a power supply tube, the negative single particle transient reinforcement circuit includes a comparator CMP, a resistor network, a pass transistor P11, a power supply transistor P12 and a capacitor C1;
[0040] The positive input terminal of the comparator CMP is connected to the output terminal of BGR, the negative input terminal of the comparator CMP is connected to the resistor network, and the output terminal of the comparator CMP is connected to the gate of the pass transistor P11 and the gate of the power supply transistor P12;
[0041] The drain of the through transistor P11 is connected to the positive input terminal of the comparator CMP, the source of the through transistor P11 is connected to one end of the capacitor C1, the source of the power supply transistor P12 and the voltage output terminal, and the other end of the capacitor C1 is grounded;
[0042] The drain of the power supply transistor P12 is connected to the negative input terminal of the comparator CMP;
[0043] The resistor network is formed by a plurality of resistors connected in series, and the resistor network is grounded. The plurality of resistors include a fifth resistor, a sixth resistor, and an Nth resistor RN (N is an integer greater than 5).
[0044] In the present invention, the comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit, and the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.
[0045] The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load tube P1, a second load tube P4, a first reset tube P2 and a second reset tube P3. The source of the second transistor N2 is grounded, and the gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is respectively connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4. The drain of the first differential input transistor N3 is respectively connected to the drain of the first load tube P1 and the drain of the first reset tube P2; the drain of the second differential input transistor N4 is respectively connected to the drain of the second reset tube P3. 3 drain and the drain of the second load transistor P4; the second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7 and a fourth reset transistor P9, the gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is respectively connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7;
[0046] The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is respectively connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5;
[0047] The drain of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, the gate of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, the source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6;
[0048] The gate of the fifth load tube P8 is connected to the gate of the sixth load tube P10 and connected to the drain of the third reset tube P7;
[0049] The output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor N7;
[0050] The bias circuit includes a fifth reset tube P0, a first transistor N1 and an eighth transistor N0. A fourth resistor R0, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series are connected between the drain of the fifth reset tube P0 and the drain of the eighth transistor N0. The source of the eighth transistor N0 is grounded, the drain of the first transistor N1 is connected to the drain of the eighth transistor N0, and the source of the first transistor N1 is grounded.
[0051] When the control terminal voltage Vcmp_en is at a high level, the comparator enters a normal working state. The second transistor N2 copies the current on the bias circuit. At this time, the differential amplifier receives two input voltages Vin_m and Vin_p. The end with a higher voltage gets more current, so the voltage Vom1 or Vop1 on its drain is smaller. These two voltages control the conduction state of the fourth transistor P5 and the fifth transistor P6. The end with a smaller voltage in Vom1 and Vop1 produces a larger current, which pulls up Vop2 or Vom2. At the same time, since the sixth transistor N8 and the seventh transistor N11 form a positive feedback, the voltage difference between Vop2 and Vom2 is amplified as a differential input for differential to single-ended conversion. The fifth load tube P8 and the sixth load tube P10 convert the differential signal into a single-ended signal as an output.
[0052] like Figure 3-Figure 4 As shown, transistors Q1, Q2, P0, and P1 are used to obtain voltages with positive and negative temperature coefficients. AMP is an operational amplifier used to adjust the output voltage. Transistors P2, Q3, and resistor R1 are used to generate the output voltage. First, based on SPICE circuit simulation, with BGR output as the final indicator, sensitive node analysis is performed on different nodes in the BGR circuit. During the analysis, it is first determined that the BGR circuit is working properly and the circuit is in normal working state. Secondly, a double exponential current source is added, and the transient current direction is from level N to level P. The SET occurs when the circuit is working normally. Finally, the recovery time and change amplitude when SET occurs at different circuit nodes are statistically analyzed to obtain Figure 4 The sensitive node analysis diagram shown in Figure 2 is shown in Figure 2. Figure 4 It can be seen that the SET positive pulse voltage change caused by the double exponential current source bombarding the MP18 transistor is the largest, so the subsequent reinforcement and analysis are based on the bombardment of MP18.
[0053] Working principle: The reinforcement method of the negative single-particle transient reinforcement circuit based on the comparator and the power supply tube includes the following steps:
[0054] A. After BGR is affected by the double exponential current source, its output voltage Vref will produce a positive voltage change;
[0055] B. Negative single-particle transient reinforcement circuit First, the comparator reference voltage value Vcmp is modified through the resistor network, and a pulse voltage value Vpilse is given so that the comparator is always in a real-time comparison state;
[0056] C. The output voltage Vcmp_op of the comparator is obtained according to the change of Vref and Vcmp, and Vcmp_op outputs the voltage through the transistor;
[0057] D. Vcmp_op controls the opening and closing of PassTransistor. When Vref is greater than Vcmp, the power supply transistor is turned off. At the same time, the power supply transistor is turned on. At this time, the output voltage of Final_op is Vcmp. When Vref is greater than Vcmp, the power supply transistor is turned on. The output voltage of Final_op is Vref. Capacitor C1 is used to reduce the influence of pulse voltage Vpulse on the output.
[0058] like Figure 5 As shown, fastreg_vref is the voltage change of MP18 node in BGR before and after SET. During the simulation, the voltage of fastreg_vref is stable at 320mV before being affected by SET, Vcmp is set to 350mV, and final_op1, final_op2, and final_op3 are the voltage changes of the above three output circuits after adding reinforcement circuits. It can be seen that the third output circuit fails to stabilize the output voltage within a certain range, and the first and second output circuits can effectively reinforce the circuit.
[0059] In summary, the negative single-particle transient reinforcement circuit based on the comparator and the power supply tube of the present invention can effectively reinforce the circuit and stabilize the output voltage within a certain range by adjusting the Vref voltage output by the BGR after SET based on the comparator in real time.
[0060] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A negative single event transient reinforcement circuit based on a comparator and a power supply tube, characterized in that: The negative single event transient reinforcement circuit includes a comparator CMP, a resistor network, a pass transistor P11, a supply transistor P12 and a capacitor C1; The positive input terminal of the comparator CMP is connected to the output terminal of BGR, the negative input terminal of the comparator CMP is connected to the resistor network, and the output terminal of the comparator CMP is connected to the gate of the pass transistor P11 and the gate of the power supply transistor P12; The drain of the through transistor P11 is connected to the positive input terminal of the comparator CMP, the source of the through transistor P11 is connected to one end of the capacitor C1, the source of the power supply transistor P12 and the voltage output terminal, and the other end of the capacitor C1 is grounded; The drain of the power supply transistor P12 is connected to the negative input terminal of the comparator CMP.
2. The negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 1, characterized in that: The resistor network is formed by a plurality of resistors connected in series and grounded. The plurality of resistors include a fifth resistor R5, a sixth resistor R6, and an Nth resistor RN (N is an integer greater than 5).
3. The negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 1, characterized in that: The comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit. The bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.
4. The negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 3, characterized in that: The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load tube P1, a second load tube P4, a first reset tube P2 and a second reset tube P3. The source of the second transistor N2 is grounded, and the gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is respectively connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4. The drain of the first differential input transistor N3 is respectively connected to the drain of the first load tube P1 and the drain of the first reset tube P2; the drain of the second differential input transistor N4 is respectively connected to the drain of the second reset tube P3 and the drain of the second load tube P4.
5. The negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 3, characterized in that: The second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7 and a fourth reset transistor P9, the gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is respectively connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7; The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is respectively connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5; The drain of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, the gate of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, the source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6; The gate of the fifth load tube P8 is connected to the gate of the sixth load tube P10 and to the drain of the third reset tube P7.
6. The negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 3, characterized in that: The output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor N7.
7. The negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 3, characterized in that: The bias circuit includes a fifth reset tube P0, a first transistor N1 and an eighth transistor N0. A fourth resistor R0, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series are connected between the drain of the fifth reset tube P0 and the drain of the eighth transistor N0. The source of the eighth transistor N0 is grounded, the drain of the first transistor N1 is connected to the drain of the eighth transistor N0, and the source of the first transistor N1 is grounded.
8. A method for reinforcing a negative single event transient reinforcement circuit based on a comparator and a power supply tube according to claim 1, characterized in that: The reinforcement method includes the following steps: A. After BGR is affected by the double exponential current source, its output voltage Vref will produce a positive voltage change; B. Negative single-particle transient reinforcement circuit First, the comparator reference voltage value Vcmp is modified through the resistor network, and a pulse voltage value Vpilse is given so that the comparator is always in a real-time comparison state; C. The output voltage Vcmp_op of the comparator is obtained according to the change of Vref and Vcmp, and Vcmp_op outputs the voltage through the transistor; D. Vcmp_op controls the opening and closing of PassTransistor. When Vref is greater than Vcmp, the power supply transistor is turned off. At the same time, the power supply transistor is turned on. At this time, the output voltage of Final_op is Vcmp. When Vref is greater than Vcmp, the power supply transistor is turned on. The output voltage of Final_op is Vref. Capacitor C1 is used to reduce the influence of pulse voltage Vpulse on the output.