Bidirectional counter circuit applied to stepping motor driving chip

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a bidirectional counter circuit applied to a stepping motor driving chip. According to the circuit, the function of a three-bit counter is achieved, counting is triggered by the rising edge of a clock, counting is gradually carried out from 0 to 6, then counting is gradually carried out from 6 to 0, and by parity of reasoning, automatic increasing or decreasing is carried out in the range from 0 to 6, and the counting interval can be changed through the MODE pin. According to the invention, the output signal is expressed in a binary form and is realized through a small number of basic logic gates, data selectors, D triggers and T triggers, so that the chip pins and the area are reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a bidirectional counter circuit applied to a stepping motor drive chip. Background Art

[0002] In the stepper motor driver chip, there is a chopper circuit drive system, which requires a counter circuit to generate a control signal to control the different threshold values ​​of the chopper current, thereby realizing the step-changing operation. Since the threshold of the chopper current changes periodically, within one cycle, the chopper current threshold will gradually rise to a certain maximum value according to the clock signal, then gradually drop to the minimum value, and then gradually rise again in a cycle. In addition, there are multiple subdivision modes required in the stepper motor driver chip, and the counter is required to realize the counting of asynchronous step angles. Therefore, a bidirectional stepper that can change the step angle and automatically reverse at a fixed number is required. Summary of the invention

[0003] In view of the above problems, the present invention provides a bidirectional stepper which can change the step angle and automatically change direction at a fixed number, and can meet the needs of the chopper circuit driving system of the stepper motor driving chip.

[0004] The technical solution of the present invention is:

[0005] A bidirectional counter circuit applied to a stepping motor driving chip, comprising a bidirectional counter circuit capable of changing direction and a logic circuit for automatically controlling the counter commutation;

[0006] The bidirectional counter circuit capable of changing direction comprises a first T trigger, a second T trigger, a third T trigger, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first data selector, a second data selector, a third data selector, a first OR gate, a second OR gate, a first NOT gate, a second NOT gate, a third NOT gate, and a first NOR gate; wherein the input end of the second NOT gate inputs a mode signal, the output end of the second NOT gate is connected to the first input end of the first NOR gate and the data selection ends of the first data selector, the second data selector, and the third data selector, the input end of the third NOT gate inputs a reset signal, the output end of the third NOT gate is connected to the second input end of the first NOR gate, and the output end of the third NOT gate is connected to the second input end of the first NOR gate. The output terminal of an NOR gate is connected to the reset terminal of the first T flip-flop, the clock terminal of the first T flip-flop inputs a clock signal, the set terminal of the first T flip-flop inputs a set signal, the T input port of the first T flip-flop inputs a power signal, the positive phase output terminal of the first T flip-flop outputs a first signal and is connected to the second input terminal of the first AND gate, the negative phase output terminal of the first T flip-flop is connected to the first input terminal of the second AND gate, the input terminal of the first inverter inputs a commutation signal, the output of the first inverter is connected to the second input terminal of the second AND gate and the first input terminal of the third data selector, the first input terminal of the first AND gate inputs a commutation signal, the output terminal of the first AND gate is connected to the first input terminal of the first OR gate and the second data selector. The second input terminal of the selector is connected to the second input terminal of the second data selector, the first input terminal of the second data selector inputs a commutation signal, the output terminal of the second data selector is connected to the first input terminal of the third AND gate, the output terminal of the second AND gate is connected to the second input terminal of the first OR gate and the second input terminal of the third data selector, the output terminal of the third data selector is connected to the second input terminal of the fourth AND gate, the output terminal of the first OR gate is connected to the second input terminal of the first data selector, the first input terminal of the first data selector inputs a power supply signal, the output terminal of the first data selector is connected to the T input terminal of the second T flip-flop, the clock signal is input to the clock input terminal of the second T flip-flop, the reset signal is input to the reset terminal of the second T flip-flop, and the set terminal of the second T flip-flop is connected to the reset terminal of the second T flip-flop. Input a set signal, the positive phase output terminal of the second T flip-flop outputs a second signal, which is connected to the second input terminal of the third AND gate, the negative phase output terminal of the second T flip-flop is connected to the first input terminal of the fourth AND gate, the output terminal of the third AND gate is connected to the first input terminal of the second OR gate, the output terminal of the fourth AND gate is connected to the second input terminal of the second OR gate, the output terminal of the second OR gate is connected to the T input terminal of the third T flip-flop, the clock signal is input to the clock input terminal of the third T flip-flop, the set signal is input to the set terminal of the third T flip-flop, the reset signal is input to the reset terminal of the third T flip-flop, the positive phase output terminal of the third T flip-flop outputs the third signal, and the negative phase output terminal of the third T flip-flop outputs the negative phase output of the third signal;

[0007] The logic circuit for automatically controlling the commutation of the counter includes a fifth AND gate, a sixth AND gate, a third OR gate, and a first D flip-flop; wherein the first input end of the fifth AND gate inputs the inverted input signal of the first signal, the second input end of the fifth AND gate inputs the input signal of the second signal, the third input end of the fifth AND gate inputs the input signal of the third signal, the output end of the fifth AND gate is connected to the first input end of the third OR gate, the first input end of the sixth AND gate inputs the inverted input signal of the first signal, the second input end of the sixth AND gate inputs the inverted input signal of the second signal, the third input end of the sixth AND gate inputs the inverted input signal of the third signal, the output end of the sixth AND gate is connected to the second input end of the third OR gate, the output end of the third OR gate is connected to the clock input port of the first D flip-flop, the D input end of the first D flip-flop is connected to the inverted output end of the first D flip-flop, the reset end of the first D flip-flop inputs the reset signal, and the positive output end of the first D flip-flop outputs the commutation signal. .

[0008] The beneficial effects of the present invention are: the counter direction is changed by a commutation signal, the counter structure is simplified, the chip area is saved, the generation of erroneous signals during step change is reduced, and the counter direction can be changed at any fixed position. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The invention proposes a bidirectional counter circuit capable of changing direction.

[0010] Figure 2 The present invention proposes a logic circuit for automatically controlling the counter commutation.

[0011] Figure 3 It is a schematic diagram of the overall simulation results obtained by spectre simulation of a bidirectional counter circuit for a stepper motor driver chip proposed in the present invention. DETAILED DESCRIPTION

[0012] The present invention will be described in detail below with reference to the accompanying drawings.

[0013] The present invention proposes a bidirectional counter circuit applied to a stepper motor driver chip, which is mainly composed of two parts, one of which is a bidirectional counter circuit that can change direction. Figure 1As shown, it is characterized by a first T flip-flop T1, a second T flip-flop T2, a third T flip-flop T3, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a first data selector C1, a second data selector C2, a third data selector C3, a first OR gate OR1, a second OR gate OR2, a first NOT gate INV1, a second NOT gate INV2, a third NOT gate INV3, and a first NOR gate NOR1.The input end of the second invertor INV2 inputs the mode selection signal, the output end of the second invertor INV2 is connected to the first input end of the first NOR gate NOR1 and the data selection end of the first data selector C1, the second data selector C2, and the third data selector C3, the input end of the third invertor INV3 inputs the reset signal, the output end of the third invertor INV3 is connected to the second input end of the first NOR gate NOR1, the output end of the first NOR gate NOR2 is connected to the reset end of the first T flip-flop T1, the clock signal is input to the clock port of the first T flip-flop T1, the set signal is input to the set end of the first T flip-flop T1, the power signal is input to the T input port of the first T flip-flop T1, and the positive phase output end of the first T flip-flop T1 is connected to The second input terminal of the first AND gate AND1 and the output Q0 of the first bit, the inverting output terminal of the first T flip-flop T1 is connected to the first input terminal of the second AND gate AND2 and the inverting output NQ0 of the first bit, the input terminal of the first inverter INV1 inputs a commutation signal, the output of the first inverter INV1 is connected to the second input terminal of the second AND gate AND2 and the first input terminal of the third data selector C3, the first input terminal of the first AND gate AND1 inputs a commutation signal, the output terminal of the first AND gate AND1 is connected to the first input terminal of the first OR gate OR1 and the second input terminal of the second data selector C2, the first input terminal of the second data selector C2 inputs a commutation signal, and the output terminal of the second data selector C2 is connected to the first input terminal of the third AND gate AND3 An input terminal of the second AND gate AND2 is connected to a second input terminal of the first OR gate OR1 and a second input terminal of the third data selector C3, an output terminal of the third data selector C3 is connected to a second input terminal of the fourth AND gate AND4, an output terminal of the first OR gate OR1 is connected to a second input terminal of the first data selector C1, a power supply signal is input to the first input terminal of the first data selector C1, an output terminal of the first data selector is connected to a T input terminal of the second T flip-flop T2, a clock signal is input to a clock input terminal of the second T flip-flop T2, a reset signal is input to a reset terminal of the second T flip-flop T2, a set signal is input to a set terminal of the second T flip-flop T2, and a positive phase output terminal of the second T flip-flop T2 is connected to a second input terminal of the third AND gate AND3 and the output Q1 of the second bit, the inverting output port of the second T flip-flop T2 is connected to the first input terminal of the fourth AND gate AND4 and the inverting output NQ1 of the second bit, the output terminal of the third AND gate AND3 is connected to the first input terminal of the second OR gate OR2, the output terminal of the fourth AND gate AND4 is connected to the second input terminal of the second OR gate OR2, the output terminal of the second OR gate OR2 is connected to the T input terminal of the third T flip-flop T3, the clock input terminal of the third T flip-flop T3 inputs the clock signal, the set terminal of the third T flip-flop T3 inputs the set signal, the reset terminal of the third T flip-flop T3 inputs the reset signal, the positive output terminal of the third T flip-flop T3 is connected to the output Q2 of the third bit, and the inverting output terminal of the third output terminal is connected to the inverting output NQ2 of the third bit.

[0014] When the commutation signal is set to 1 and the MODE signal is set to 1, the outputs of the second AND gate AND2 and the fourth AND gate AND4 are set to 0, and the first data selector C1, the second data selector C2, and the third data selector C3 select the signal input to the second input terminal, so it is equivalent to the positive phase output terminal of the first T trigger T1 being directly connected to the T input terminal of the second T trigger T2, and the positive phase output terminals of the first T trigger T1 and the second T trigger T2 are respectively connected to the first input terminal and the second input terminal of the third AND gate AND3, and the output terminal of the third AND gate AND3 is connected to the T input terminal of the third T trigger T3. Therefore, when the first bit output is 0, the output of the second T trigger T2 and the output of the third T trigger T3 will be maintained when the next clock arrives, and when the first bit is 1, the output of the second T trigger T2 will flip once when the next clock arrives, and the output of the third T trigger T3 will flip only when the first bit and the second bit are set to 1 at the same time, and the counter will implement the operation of adding 1 when each clock arrives. Similarly, when the commutation signal is set to 0, the situation is just the opposite. The outputs of the first AND gate AND1 and the third AND gate AND3 are set to 0, which is equivalent to the inverting output of the first T trigger T1 being directly connected to the T input of the second T trigger T2. The inverting outputs of the first T trigger T1 and the second T trigger T2 are respectively connected to the first input and the second input of the fourth AND gate AND4, and the output of the fourth AND gate AND4 is connected to the T input of the third T trigger T3. The counter will perform a minus 1 operation when each clock arrives. When the MODE pin is set to 0, the reset pin of the first T trigger T1 inputs 0, the positive output of the first T trigger is always set to 0, and the first data selector C1, the second data selector C2, and the third data selector C3 select the signal input to the first input, so only the second T trigger T2 and the third T trigger T3 count normally, realizing the increase of the step spacing.

[0015] The other part is the logic circuit that automatically controls the counter commutation. Figure 2As shown, it is characterized by a fifth AND gate AND5, a sixth AND gate AND6, a third OR gate OR3, and a first D flip-flop D1. Among them, the first input terminal of the fifth AND gate AND5 inputs the inverted input signal of the first bit, the second input terminal of the fifth AND gate AND5 inputs the input signal of the second bit, the third input terminal of the fifth AND gate AND5 inputs the input signal of the third bit, the output terminal of the fifth AND gate AND5 is connected to the first input terminal of the third OR gate OR3, the first input terminal of the sixth AND gate AND6 inputs the inverted input signal of the first bit, the second input terminal of the sixth AND gate AND6 inputs the inverted input signal of the second bit, the third input terminal of the sixth AND gate AND6 inputs the inverted input signal of the third bit, the output terminal of the sixth AND gate AND6 is connected to the second input terminal of the third OR gate OR3, the output terminal of the third OR gate OR3 is connected to the clock input port of the first D flip-flop D1, the D input terminal of the first D flip-flop D1 is connected to the inverted output terminal of the first D flip-flop D1, the reset terminal of the first D flip-flop D1 inputs the reset signal, and the positive phase output terminal of the first D flip-flop D1 outputs the commutation signal.

[0016] Only when the first bit is 0 and the second and third bits are set to 1 at the same time, or the first, second and third bits are set to 0 at the same time, the clock port of the first D flip-flop D1 will be set to 1, and the output signal of the first D flip-flop D1 will be flipped. The output signal of the positive phase output end of the first flip-flop D1 is connected to the commutation signal input port of the counter circuit as a commutation signal, so that the counter can automatically commutate when the output is 000 and 110.

[0017] Based on the above method, a bidirectional counter circuit that can meet the needs of the chopper drive system of the stepper motor driver chip is realized. The circuit of the present invention realizes the function of a 3-bit counter, which is triggered by the rising edge of the clock, and gradually counts from 0 to 6, and then gradually counts from 6 to 0, and so on, and automatically increases or decreases within the range of 0 to 6, and the counting interval can be changed through the MODE pin. The output signal of the present invention is represented in binary form, and is realized by a small number of basic logic gates, data selectors, D flip-flops and T flip-flops, which reduces the chip pins and area.

Claims

1. A bidirectional counter circuit applied to a stepper motor driver chip, characterized in that: It includes a bidirectional counter circuit capable of changing direction and a logic circuit for automatically controlling the counter commutation; The bidirectional counter circuit capable of changing direction comprises a first T trigger, a second T trigger, a third T trigger, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first data selector, a second data selector, a third data selector, a first OR gate, a second OR gate, a first NOT gate, a second NOT gate, a third NOT gate, and a first NOR gate; wherein the input end of the second NOT gate inputs a mode signal, the output end of the second NOT gate is connected to the first input end of the first NOR gate and the data selection ends of the first data selector, the second data selector, and the third data selector, the input end of the third NOT gate inputs a reset signal, the output end of the third NOT gate is connected to the second input end of the first NOR gate, and the output end of the third NOT gate is connected to the second input end of the first NOR gate. The output terminal of an NOR gate is connected to the reset terminal of the first T flip-flop, the clock terminal of the first T flip-flop inputs a clock signal, the set terminal of the first T flip-flop inputs a set signal, the T input port of the first T flip-flop inputs a power signal, the positive phase output terminal of the first T flip-flop outputs a first signal and is connected to the second input terminal of the first AND gate, the negative phase output terminal of the first T flip-flop is connected to the first input terminal of the second AND gate, the input terminal of the first inverter inputs a commutation signal, the output of the first inverter is connected to the second input terminal of the second AND gate and the first input terminal of the third data selector, the first input terminal of the first AND gate inputs a commutation signal, the output terminal of the first AND gate is connected to the first input terminal of the first OR gate and the second data selector. The second input terminal of the selector is connected to the second input terminal of the second data selector, the first input terminal of the second data selector inputs a commutation signal, the output terminal of the second data selector is connected to the first input terminal of the third AND gate, the output terminal of the second AND gate is connected to the second input terminal of the first OR gate and the second input terminal of the third data selector, the output terminal of the third data selector is connected to the second input terminal of the fourth AND gate, the output terminal of the first OR gate is connected to the second input terminal of the first data selector, the first input terminal of the first data selector inputs a power supply signal, the output terminal of the first data selector is connected to the T input terminal of the second T flip-flop, the clock signal is input to the clock input terminal of the second T flip-flop, the reset signal is input to the reset terminal of the second T flip-flop, and the set terminal of the second T flip-flop is connected to the reset terminal of the second T flip-flop. Input a set signal, the positive phase output terminal of the second T flip-flop outputs a second signal, which is connected to the second input terminal of the third AND gate, the negative phase output terminal of the second T flip-flop is connected to the first input terminal of the fourth AND gate, the output terminal of the third AND gate is connected to the first input terminal of the second OR gate, the output terminal of the fourth AND gate is connected to the second input terminal of the second OR gate, the output terminal of the second OR gate is connected to the T input terminal of the third T flip-flop, the clock signal is input to the clock input terminal of the third T flip-flop, the set signal is input to the set terminal of the third T flip-flop, the reset signal is input to the reset terminal of the third T flip-flop, the positive phase output terminal of the third T flip-flop outputs the third signal, and the negative phase output terminal of the third T flip-flop outputs the negative phase output of the third signal; The logic circuit for automatically controlling the commutation of the counter comprises a fifth AND gate, a sixth AND gate, a third OR gate, and a first D flip-flop; wherein, the first input end of the fifth AND gate inputs the inverted input signal of the first signal, the second input end of the fifth AND gate inputs the input signal of the second signal, the third input end of the fifth AND gate inputs the input signal of the third signal, the output end of the fifth AND gate is connected to the first input end of the third OR gate, the first input end of the sixth AND gate inputs the inverted input signal of the first signal, the second input end of the sixth AND gate inputs the inverted input signal of the second signal, the third input end of the sixth AND gate inputs the inverted input signal of the third signal, the output end of the sixth AND gate is connected to the second input end of the third OR gate, the output end of the third OR gate is connected to the clock input port of the first D flip-flop, the D input end of the first D flip-flop is connected to the inverted output end of the first D flip-flop, the reset end of the first D flip-flop inputs the reset signal, and the positive phase output end of the first D flip-flop outputs the commutation signal.

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