Analog-to-digital converter circuit and method for analog-to-digital converter circuit

Abstract

An analog-to-digital converter circuit and a method for an analog-to-digital converter circuit are disclosed. Wherein an analog-to-digital converter (ADC) circuit is configured to receive a differential input signal or a single-ended (SE) input signal and to output a digital representation of the input signal with a full scale of the ADC output. The ADC circuitry of the present disclosure includes a true differential ADC configured to make two adjustments to ADC characteristics when receiving an SE input signal. One adjustment is to offset ADC characteristics from a reference voltage of the ADC, e.g., Varef. Another adjustment is to multiply the input signal by two, for example, to double the amplitude of the input signal.

Description

Technical Field

[0001] The present disclosure relates to analog-to-digital converter circuits and methods for analog-to-digital converter circuits. Background Art

[0002] The analog-to-digital conversion circuit system is configured to receive an analog signal and output a digital representation of the received signal. The resolution of the analog-to-digital conversion circuit system depends on the number of output bits, and the more output bits, the higher the resolution, e.g., the value is closer to the analog signal, compared to fewer output bits. Some example types of analog-to-digital converter (ADC) circuit systems may include flash or direct ADCs, delta-sigma, and successive approximation registers (SARs). Some examples of ADC circuit systems may be differential circuit systems in which the ADC output is based on the difference between two input signals. Other examples of ADC circuit systems may include single-ended (SE) circuit systems, also known as unipolar circuit systems, that compare an input voltage to a reference voltage (e.g., ground). Summary of the invention

[0003] In general, the present disclosure describes an analog-to-digital converter (ADC) circuit system that is configured to receive a differential input signal or a single-ended (SE) input signal and output a digital representation of the input signal using the full scale of the ADC output. The ADC circuit system of the present disclosure includes a true differential ADC that is configured to make two adjustments to ADC characteristics when receiving a SE input signal. One adjustment is to offset the ADC characteristics by a reference voltage of the ADC, e.g., Varef. The second adjustment is to multiply the input signal by 2, e.g., to double the input signal amplitude.

[0004] In one example, the present disclosure describes an ADC circuit comprising: a first input terminal and a second input terminal; and a circuit system: which is configured to receive an analog signal including voltages at the first input terminal and the second input terminal, offset the received analog signal by a reference voltage of the ADC circuit, double the received analog signal, and output a digital value approximating the voltage of the analog signal based on the offset and doubled received analog signal.

[0005] In another example, the present disclosure describes a method comprising: receiving an analog signal including voltage amplitudes at a first input terminal and a second input terminal of an ADC circuit; offsetting the received analog signal by a reference voltage of the ADC circuit; doubling the received analog signal and outputting a digital value approximating the voltage amplitude of the analog signal.

[0006] In another example, the present disclosure describes an ADC circuit comprising: a first input terminal and a second input terminal; and a circuit system configured to receive an analog signal including voltage amplitudes at the first input terminal and the second input terminal; in response to the received analog signal being a single-ended analog signal, sample the received analog signal and offset it by a reference voltage of the ADC circuit; double the received analog signal by halving the reference voltage during a conversion phase; and output a digital value that approximates the voltage amplitude of the analog signal.

[0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic diagram showing an ADC receiving a differential input analog signal.

[0009] Figure 1B is a schematic diagram showing an ADC receiving a single-ended input analog signal.

[0010] Figure 2 is a graph showing the voltage range and digital range of a true differential ADC receiving a differential input analog signal and receiving a single-ended input analog signal.

[0011] Figure 3 are diagrams illustrating example implementations of techniques of this disclosure.

[0012] Figure 4 is a schematic diagram illustrating an example circuit configured to implement a TD ADC of the present disclosure.

[0013] Figure 5A is a schematic diagram showing a TD ADC of the present disclosure during a sampling phase.

[0014] Figure 5B is a schematic diagram showing a TD ADC of the present disclosure during the hold and conversion phases.

[0015] Fig. 6A is a timing diagram showing an example SAR approximation for a single-ended input equal to ground without offsetting the ADC transfer function.

[0016] Figure 6B is a graph illustrating an example SAR approximation for a single-ended input equal to ground using an offset ADC transfer function in accordance with one or more techniques of the present disclosure.

[0017] Figure 6Cis a graph showing a shifted ADC conversion curve 612 and a non-shifted ADC conversion curve 610 .

[0018] Figure 7 is a flow chart describing an example operation of the TD ADC circuitry of the present disclosure. DETAILED DESCRIPTION

[0019] The present disclosure describes an analog-to-digital converter (ADC) circuit system that is configured to receive a differential input signal or a single-ended (SE) input signal and a digital representation of the full-scale output input signal using the ADC output. Some sensing applications may be beneficial in converting both single-ended (SE) analog voltage signals and differential (DIFF) analog voltage signals into digital. The SE ADC itself cannot correctly sense the DIFF signal. Similarly, the DIFF ADC cannot correctly sense the SE signal. However, a true differential (TD) ADC can enable sensing of the SE signal and the DIFF signal, but the SE signal will be limited to half of the ADC characteristics. The ADC circuit system of the present disclosure is configured to perform both DIFF sensing and full-scale SE sensing by using a modified version of the TD switched capacitor SAR ADC.

[0020] The ADC circuit system of the present disclosure includes a true differential ADC, which is configured to make two adjustments to the ADC characteristics when receiving the SE input signal. In some examples, the first adjustment is to offset the ADC characteristics by a reference voltage of the ADC, such as Varef. The second adjustment is to multiply the input signal by 2, for example, to double the amplitude of the input signal. In this way, the SE signal can be converted into a digital signal using the full scale of the TD ADC. Because the amplitude of the offset depends on the digital word set during sampling, in other examples, the offset can be programmed from zero to the reference voltage Varef.

[0021] Figure 1A and Figure 1B is a schematic diagram showing an example of a differential input TD-ADC and a single-ended input to the TD-ADC. Figure 1A In the example of , the TD-ADC 110 may receive a first input from Vip 102 at a first terminal and a second input from Vin 104 at a second terminal. A common mode voltage is modeled as Vcm 138 and is connected to both the first terminal and the second terminal.

[0022] exist Figure 1B In the example of , the same TD-ADC 110 can be configured to receive a single-ended input. Figure 1B In FIG. 1 , Vin 114 is connected to ground and Vip 112 is connected to Vinput 140 through resistor R1. Resistor R1 and resistor R2 form a voltage divider.

[0023] The TD ADC circuit system of the present disclosure can have advantages over other implementations of ADC. At present, in the case where the system should use SE and differential conversion at the same time, there are several ways to implement the TD ADC different from the present disclosure. For example, using two types of ADC, a SE ADC and a DIFF ADC, has the following disadvantages, for example: the system needs to develop two complete ADCs, thereby consuming more circuit area, additional power consumption and increasing the complexity of the entire system. In another example, the ADC circuit can convert the SE signal into DIFF and use the DIFF ADC, which has the following disadvantages: introducing additional errors to the sampled signal, potentially introducing additional power consumption and affecting the circuit area. In another example, the ADC circuit can convert the DIFF signal into SE and use the SE ADC, which has the following disadvantages: due to the SE operation, the power supply rejection (PSR) and common mode interference rejection of the ADC are lost, additional errors are introduced to the sampled signal, potentially introducing additional power consumption and affecting the circuit area. As described above, another technique may include using the TD ADC without adjusting the SE signal, which has the disadvantage of losing half of the dynamics of the ADC because the SE signal is unipolar.

[0024] Figure 2 is a graph showing the voltage range and digital range of a true differential ADC receiving a differential input analog signal and receiving a single-ended input analog signal. Figure 2 A differential input 202 is shown, which can vary between -Varef and +Varef. The reference voltage Varef is the voltage amplitude that produces the full-scale digital output of the ADC. The full scale depends on the number of bits of the ADC, for example, the full scale of an 8-bit ADC is 255, and the full scale of a 12-bit ADC is 4095. Therefore, for the differential input 202, a negative value -Varef will cause the output of the TDADC to be digital zero, for example, 0000 0000 for an 8-bit ADC. For an 8-bit ADC, the differential voltage +Varef received by the TD ADC will cause the digital output to be 255 or 1111 1111.

[0025] However, as mentioned above Figure 1B As depicted, the single-ended input 204 has a voltage range 210 from ground or Vin 208 to Vip 212. Thus, the range of the digital value 206 of the SE input is half of the full scale, e.g. Figure 2 In the example, from FS / 2 to FS.

[0026] Figure 3 TD ADC of the present disclosure helps to solve the above-mentioned Figure 1B and Figure 2 Describe the problem. Figure 3 In the example of FIG. 3 , the initial transfer function 304 of the SE input (e.g., unipolar input) can vary in the voltage range from ground (GND) to +Varef, and can output digital values ​​from FS / 2 to FS. The TD ADC is different from a fully differential or differential ADC because the TD ADC performs conversion of the input differential signal independently of the common mode of the input signal. This independent characteristic enables the TD ADC to also receive SE signals at the ADC differential input terminals. However, as described above with respect to Figure 2 As described, due to the unipolar nature of the SE signal, only the portion of the ADC dynamic range that effectively halves the number of quantization steps of full scale ( Figure 2 SE input 204 and Figure 3 An initial conversion function 304) may be used.

[0027] In order to make the ADC full-scale digital range suitable for single-ended measurement, the ADC circuit system may include the following equivalent transformations for the input: voltage offset and multiplication by 2. The successive approximation register (SAR) ADC of the present disclosure may include at least one capacitor digital to analog converter (CDAC) for feedback. The offset Varef may cause the input voltage range of the TD ADC to be from ground to twice Varef, and the digital conversion function uses the full scale of the TD-ADC. The offset Varef may be implemented by sampling under the following settings of the CDAC: the digital output of the positive SAR output terminal of the SAR is 0 and the digital output of the negative SAR output terminal of the SAR is FS. In other examples, the offset may be programmed from zero to the reference voltage Varef as described above for setting a specified amplitude for the offset.

[0028] The TD ADC circuitry of the present disclosure may multiply the input signal by 2, thus obtaining a final transfer function 306. The final transfer function 306 may output the full scale of the ADC digital value for a SE input voltage range from ground to +Varef. In some examples, the multiplication by 2 may be achieved by doubling the sampling capacitor. In other examples, the circuit may not include a dedicated sampling capacitor. The multiplication factor of 2 may also be given by different reference voltages used during sampling and redistribution. For example, the circuit may operate by halving the reference voltage (e.g., Varef) during the conversion phase rather than doubling the capacitance of the sampling capacitor.

[0029] In other examples, the TD ADC circuit can offset the received input voltage by an arbitrary value, for example, a value less than Varef. The relative capacitance values ​​of the components can be selected to work with any offset voltage value to implement the offset and multiplication features of the TD ADC circuit of the present disclosure. In other words, the example of the TD ADC circuit can be used to condition the input signal of any type of SC SAR ADC, where the sampling capacitor and CDAC are two different entities that allow offset gain adjustment.

[0030] Figure 4 is a schematic diagram illustrating an example circuit configured to implement a TD ADC of the present disclosure. Figure 4 The circuit in the example is configured to implement the above Figure 3 Describe the offset and multiplication steps.

[0031] exist Figure 4 In the example, the two inputs are connected to Vinp_ai 438 and ground in a single-ended configuration. Figure 1A and Figure 1B As described, in other examples, the TD ADC circuit may be connected to a differential input such that the ground connection at the input would instead be connected to another voltage.

[0032] Vinp_ai 438 is connected to the non-inverting input of the comparator 406 through the series arrangement of switch S2p 452 and sampling capacitor Cs1 435. The inverting input of the comparator 406 is connected to ground through the series connection of sampling capacitor Cs2 436 and switch S2n 430. Switch S3 450 connects capacitors Cs1 435 and Cs2 436 in series when closed.

[0033] The output of the comparator 406 is connected to a successive approximation register SAR 408. The SAR 408 includes a positive SAR output terminal and also includes a negative SAR output terminal. Figure 4 SARP 454 and SARN 450 shown in FIG. are digital outputs of the positive SAR output terminal and the negative SAR output terminal, respectively. The positive SAR output terminal is connected to DAC 421 and the negative SAR output terminal is connected to DAC 424. In some examples, DAC 421 and DAC 424 are implemented as CDACs. The output of DAC 421 is connected to the non-inverting input of comparator 406 through CDAC capacitor Cd1 431. The output of DAC 424 is connected to the inverting input of comparator 406 through CDAC capacitor Cd2 434. Figure 4In the example of FIG. 4 , the node connected to the non-inverting input of the comparator 406 is Cxxxp 428, and the node connected to the inverting input of the comparator 406 is Cxxxn 429. Cxxxp 428 and Cxxxn 429 may also be connected to the common mode voltage Vcm 464 when switches S1p 466 and S1n 468 are closed.

[0034] The above article targets Figure 4 The capacitors Cs1 435, Cs2 436, Cd1 431, and Cd2 434 and switches S2p ​​452, S2n 430, S3 450, S1p 466, and S1n 468 described in the TD ADC of FIG. 4 form a switched capacitor circuit connected to the Vinp_ai 438 input terminal and the ground input terminal. The capacitance value of the CDAC capacitor Cd1 431 is configured to match the capacitance value of Cd2 434. Similarly, the capacitance value of the sampling capacitor Cs1 435 is configured to match the capacitance value of Cs2 436. As described above with respect to Figure 3 As described, to achieve multiplication by 2, in some examples, the capacitance values ​​of Cs1 435 and Cs2 436 may be twice the capacitance values ​​of Cd1 431 and Cd2 434. In other examples, Figure 4 The TD ADC can be as described above about Figure 3 The multiplication is described as being achieved by adjusting the reference voltage.

[0035] In some examples, for example, if the offset and multiplication steps of the present disclosure are not followed, the conversion performed on the SE analog input at the input can be operated as follows. Vinp_ai 438 and ground can be sampled at the input of sampling capacitors Cs1 435 and Cs2 436, where the capacitance of the sampling capacitors is approximately equal to the capacitance of the CDAC capacitors Cd1 431 and Cd2 434 relative to Vcm464. At the same time, the digital output at the positive SAR output and the digital output at the negative SAR output can be set to mid-scale, which will be equivalent to sampling half of the reference voltage to all CDAC capacitors on both sides of the comparator relative to Vcm. The reference voltage ( Figure 4 ) is the voltage that the ADC uses to compare with its analog input, for example, Figure 2 and Figure 3 The source of the reference voltage may be external to the ADC, external to the integrated circuit (IC) on which the TD ADC is implemented, or the reference voltage may be generated internally, such as a bandgap voltage reference.

[0036] The sampling phase ends once the S1 and S2 switches are opened, where the S1 switches include S1p 466 and S1n 468, and the S2 switches include S2p 452 and S2n 430. The conversion phase begins by closing switch S3 450 and running the SAR algorithm through the CDACs (e.g., DAC 421 and DAC 424) based on the output of comparator 406 at each decision cycle.

[0037] In this manner, if Vinp_ai 438 is equal to reference ground, e.g., zero volts, the first decision of the comparator will be either 1 or 0, depending on any noise in the circuit. When Vinp_ai 438 is equal to reference ground, the voltages at the inputs are approximately equal. If the first decision of comparator 406 is 1, the SAR loop will work to cancel out the effect of that decision, producing a digital output of FS / 2 at the output of the ADC, and if the first decision is 0, the opposite occurs. This is expected, as can be seen by the above description of Figure 3 The initial transfer function line 304 is described as understood.

[0038] Figure 5A and Figure 5B is a schematic diagram showing the operation of a TD ADC implementing the offset and multiplication steps of the present disclosure. Component names, reference numerals, characteristics and functions are the same as those described above with respect to Figure 4 Same as described. Figure 4 Similar to the description, Figure 5A is a schematic diagram showing a TD ADC of the present disclosure during the sampling phase. The application of the circuit operation of the present disclosure affects two aspects of analog to digital conversion. In some examples, the sampling capacitor is twice the CDAC capacitor to achieve gain doubling. In addition, as described above with respect to Figure 3 As described, during the sampling phase, the DAC settings are modified to achieve a received analog signal relative to a reference voltage (e.g., Figure 2 and Figure 3 The characteristic offset of Varef).

[0039] In some examples, SE conversion according to the steps of the present disclosure may sample Vinp_ai 438 and ground at the input relative to Vcm 464 on sampling capacitors Cs1 435 and Cs2 436, where the capacitance of the sampling capacitors is approximately twice the capacitance of the CDAC capacitors Cd1 431 and Cd2 434, thereby doubling the analog signal received at the input. At the same time, SARP 454 may be set to digital zero and SARN 450 may be set to FS. This imbalance of DAC 421 and DAC 424 is equivalent to sampling digital zero to DAC 421 (e.g., CDAC) on the positive side of comparator 406, and ground at V DACpThe digital zero at 460 is converted to approximately zero volts relative to Vcm 464. The DAC imbalance also samples the digital FS on the negative side of the comparator 406, and the DAC 424 converts the digital FS to an equivalent voltage of Varef, such as V DACn 462. As mentioned above Figure 4 As described, the sampling event ends when the S1 and S2 switches are opened.

[0040] Figure 5B 4 is a schematic diagram showing the TD ADC of the present disclosure during the hold and conversion phase. The conversion phase begins by closing switch S3 450, resetting the digital output of the positive SAR output terminal and the digital output of the negative SAR output terminal to digital mid-scale, and running the SAR algorithm through DAC 421 and DAC 424 based on the output of comparator 406 at each decision cycle. Therefore, compared to other techniques, such as those described above with respect to Figure 4 According to the described technique, if Vinp_ai 438 is equal to reference ground at the input, then at the beginning of the conversion phase, node cxxxp 428 is "pushed up 470" (e.g., DAC 421 changes from 0 to FS / 2), and node cxxxn 429 is "pushed down 472" (e.g., DAC 424 drops from FS to FS / 2). The SAR algorithm executed by SAR 408 will attempt to compensate for this by setting all bits of SARN 450 to digital ones and making all bits of SARP 454 digital zeros during the SAR search process. The result is as described above with respect to Figure 3 The converted zero word described for the final conversion function 306 .

[0041] in other words, Figure 5A and Figure 5B The TD ADC depicted in FIG. 304 can output a digital value approximating the voltage amplitude of the analog signal based on the offset and doubled received analog signal. The above specific example describes an input analog signal of approximately zero volts, for example, where Vinp_ai 438 is approximately equal to ground. In other examples, when Vinp_ai 438 is a non-zero voltage value, the TD ADC can output a digital value approximating the voltage amplitude of the analog signal according to the final transfer function 306.

[0042] Fig. 6A 6 is a timing diagram showing an example SAR approximation for a single-ended input equal to ground without offsetting the ADC transfer function. The dashed curve 602 and the solid curve 604 represent the positive and negative inputs of the comparator during the conversion phase, respectively, when the sampled positive ADC input voltage is equal to ground. Figure 4As described, during the conversion phase, the switch S3 450 is closed, the digital output at the positive SAR output terminal and the digital output at the negative SAR output terminal are reset to digital mid-scale, and the word is kept at mid-scale during sampling and the first decision period of the SAR search, and then as shown in FIG. Fig. 6A As shown, the SAR algorithm is run through DAC 421 and DAC 424 based on the output of comparator 406 in each decision cycle. When the first decision of comparator 406 is 1, as shown in FIG. Fig. 6A As shown, the SAR loop will work to counteract the effect of this decision, resulting in a digital output of FS / 2 at the output of the ADC.

[0043] Figure 6B is a graph illustrating an example SAR approximation for a single-ended input equal to ground using an offset ADC transfer function in accordance with one or more techniques of the present disclosure. Figure 6B The dashed curve 606 and the solid curve 608 in FIG. 5 represent the positive and negative inputs of the comparator during the conversion phase, respectively, when the sampled positive ADC input voltage is equal to ground and the proposed method is applied. Figure 5B As described, with Vinp_ai 438 at the input equal to the reference ground, at the beginning of the conversion phase, DAC 421 changes from zero to FS / 2 and DAC 424 changes from FS to FS / 2. The SAR algorithm can set SARN 450 to digital full scale and keep SARP 454 at digital zero during the SAR search process. The result is Figure 6B The converted zero word is shown.

[0044] Figure 6C is a graph showing a shifted ADC conversion curve 612 and a non-shifted ADC conversion curve 610 . Fig. 6A The solid line portion 604 and the dashed line portion 602 may correspond to Figure 6C The conversion function indicated by 610 in FIG. Figure 6B The solid line portion 606 and the dashed line portion 608 may correspond to Figure 6C The conversion function indicated by 612 in FIG.

[0045] Figure 7 is a flow chart describing an example operation of the TD ADC circuit system of the present disclosure. Unless otherwise specified, the Figure 4 Description by Figure 7 The boxes depict the steps.

[0046] exist Figure 7 In the example, Figure 4 The TD ADC circuit can receive an analog signal (90) including a voltage at a first input terminal and a second input terminal. Figure 4In the example of , the analog signal is a SE signal which has Vinp_ai 438 at a first input and circuit ground (eg, a reference voltage) at a second input.

[0047] like Figure 3 As shown, the TD ADC circuit can offset the received analog signal by a reference voltage (92) of the ADC circuit. The reference voltage of the ADC circuit, for example, is as described above with respect to Figure 2 and Figure 3 The voltage Varef that the described ADC uses to compare its analog input is a reference voltage different from the circuit ground voltage connected to the second input terminal. The TD ADC circuit can also double the received analog signal (94), which can be achieved by any of several implementations described above, such as making the values ​​of sampling capacitors Cs1 435 and Cs2 436 twice the capacitance of CDAC capacitors Cd1 431 and Cd2 434, or by adjusting the value of Varef. The TD ADC can perform a successive approximation register search routine to determine and output a digital value that approximates the voltage amplitude of the analog signal received at the input terminal (96).

[0048] The technology of the present disclosure may also be described in the following clauses.

[0049] Item 1. An ADC circuit, the circuit comprising: a first input terminal and a second input terminal; and a circuit system configured to: receive an analog signal including a voltage at the first input terminal and the second input terminal; offset the received analog signal by a reference voltage of the ADC circuit; double the received analog signal; and output a digital value of the voltage approximating the analog signal based on the offset and doubled received analog signal.

[0050] Item 2. The circuit of Item 1 further comprises a switched capacitor circuit connected to the first input terminal and the second input terminal, wherein the switched capacitor circuit comprises a sampling capacitor and a capacitor digital-to-analog converter (CDAC) capacitor, and wherein, in order to double the received analog signal, the capacitance of the sampling capacitor is twice the capacitance of the CDAC capacitor.

[0051] Item 3. The circuit of Item 1 or 2 further comprises a successive approximation register (SAR), the SAR comprising a positive SAR output terminal and a negative SAR output terminal, wherein, in order to offset the analog signal by a reference voltage of the ADC circuit, the circuit system is configured to set the digital output of the positive SAR output terminal and the digital output of the negative SAR output terminal to a value between zero and a full-scale (FS) digital value of the ADC circuit.

[0052] Clause 4. The circuit of any one of clauses 1 to 3, further comprising a successive approximation register (SAR), the SAR comprising a positive SAR output terminal and a negative SAR output terminal, wherein, in order to offset the analog signal by a reference voltage of the ADC circuit, the circuit is configured to: set the digital output of the positive SAR output terminal to digital zero; and set the digital output of the negative SAR output terminal to a full-scale (FS) value of the ADC circuit.

[0053] Clause 5. The circuit of any of clauses 1 to 4, wherein the circuitry is configured to offset the analog signal by a reference voltage of the ADC circuit during a sampling phase.

[0054] Clause 6. The circuit of any of Clauses 1 to 5, wherein during the sampling phase, the circuitry is configured to sample the received analog signal relative to a common mode voltage of the analog signal.

[0055] Clause 7. The circuit of any of clauses 1 to 6, further comprising a comparator comprising a non-inverting input and an inverting input, wherein the SAR is configured to receive an output of the comparator.

[0056] Clause 8. A circuit according to any one of clauses 1 to 7, wherein: the first CDAC is connected to the non-inverting input terminal through a first CDAC capacitor of the CDAC capacitors, and the first CDAC is configured to receive the digital output from the positive SAR output terminal; and the second CDAC is connected to the inverting input terminal through a second CDAC capacitor of the CDAC capacitors, and the second CDAC is configured to receive the digital output from the negative SAR output terminal.

[0057] Clause 9. A circuit according to any one of clauses 1 to 8, wherein during the hold and conversion phase, the circuit is configured to: reset the digital output at the positive SAR output terminal and the digital output at the negative SAR output terminal to mid-scale, and perform a SAR algorithm through each of the first CDAC and the second CDAC based on the output of the comparator at each decision cycle.

[0058] Clause 10. The circuit of any one of clauses 1 to 9, wherein the circuit is configured to convert a received analog signal, the received analog signal being a differential analog signal or a single-ended analog signal.

[0059] Item 11. A method comprising: receiving an analog signal including a voltage amplitude at a first input terminal and a second input terminal of an ADC circuit; offsetting the received analog signal by a reference voltage of the ADC circuit; doubling the received analog signal; and outputting a digital value approximating the voltage amplitude of the analog signal.

[0060] Clause 12. A method according to clause 11, wherein the ADC circuit includes a switched capacitor circuit connected to a first input terminal and a second input terminal, wherein the switched capacitor circuit includes a sampling capacitor and a capacitor digital-to-analog converter (CDAC) capacitor, and wherein doubling the received analog signal includes sampling the received analog signal using the sampling capacitor, and wherein the capacitance of the sampling capacitor is twice the capacitance of the CDAC capacitor.

[0061] Clause 13. A method according to clause 11 or 12, wherein the ADC circuit includes a successive approximation register (SAR), the SAR including a positive SAR output terminal and a negative SAR output terminal, wherein, in order to offset the analog signal by a reference voltage of the ADC circuit, the method includes: setting the digital output of the positive SAR output terminal to digital zero; and setting the digital output of the negative SAR output terminal to a full-scale (FS) value of the ADC circuit.

[0062] Clause 14. The method of any one of clauses 11 to 13, further comprising: during the sampling phase, offsetting the analog signal by a reference voltage of the ADC circuit.

[0063] Clause 15. The method of any one of clauses 11 to 14, further comprising: during a sampling phase, sampling the received analog signal relative to a common mode voltage of the analog signal.

[0064] Clause 16. The method of any one of clauses 11 to 15, wherein the ADC circuit further comprises a comparator comprising a non-inverting input and an inverting input, the method further comprising receiving an output of the comparator via the SAR.

[0065] Clause 17. A method according to any one of clauses 11 to 16, wherein the ADC circuit further comprises: a first CDAC connected to the non-inverting input terminal via a first CDAC capacitor of the CDAC capacitors, the method further comprising receiving, by the first CDAC, a digital output from a positive SAR output terminal; and a second CDAC connected to the non-inverting input terminal via a second CDAC capacitor of the CDAC capacitors, the method further comprising receiving, by the second CDAC, a digital output from a negative SAR output terminal.

[0066] Clause 18. A method according to any one of clauses 11 to 17, further comprising: during the hold and conversion phase: resetting the digital output at the positive SAR output terminal and the digital output at the negative SAR output terminal to a mid-scale, and executing a SAR algorithm through each of the first CDAC and the second CDAC based on the output of the comparator in each decision cycle.

[0067] Clause 19. The method of any one of clauses 11 to 18, wherein the received analog signal comprises a differential analog signal or a single-ended analog signal.

[0068] Item 20. An ADC circuit comprising: a first input terminal and a second input terminal; and a circuit system configured to: receive an analog signal including a voltage amplitude at the first input terminal and the second input terminal; in response to the received analog signal being a single-ended analog signal, sample the received analog signal and offset the received analog signal by a reference voltage of the ADC circuit; double the received analog signal by halving the reference voltage during a conversion phase and output a digital value that approximates the voltage amplitude of the analog signal.

[0069] In one or more examples, the functions described above can be implemented in hardware, software, firmware, or any combination thereof. Figure 4 , Figure 5A and Figure 5B The various components of the EMBODIMENTS 2000 may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions may be stored on a tangible computer-readable storage medium and executed by a processor or a hardware-based processing unit.

[0070] Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuit systems. Therefore, the terms "processor" and "processing circuit system" as used herein may refer to any of the above structures or any other structures suitable for implementing the techniques described herein, for example. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0071] The technology of the present disclosure can be implemented in a variety of devices or apparatuses including wireless handheld devices, integrated circuits (ICs) or IC sets (e.g., chipsets). The present disclosure describes various components, modules, or units to emphasize the functional aspects of the devices configured to perform the disclosed technology, but these functional aspects do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units can be combined in a hardware unit or provided by a set of interoperable hardware units, including the one or more processors described.

[0072] Various examples of the disclosure have been described. These and other examples are within the scope of the following claims.

Claims

1. An analog-to-digital converter (ADC) circuit, the ADC circuit comprising: a first input terminal and a second input terminal; as well as A circuit system configured to: receiving an analog signal including a voltage at the first input terminal and the second input terminal; offsetting the received analog signal by a reference voltage of the ADC circuit; doubling the received analog signal; as well as Based on the offset and doubled received analog signal, a digital value approximating a voltage of the analog signal is output.

2. The ADC circuit according to claim 1, further comprising a switched capacitor circuit connected to the first input terminal and the second input terminal, in, The switched capacitor circuit includes a sampling capacitor and a capacitive digital-to-analog converter CDAC capacitor, and In order to double the received analog signal, the capacitance of the sampling capacitor is twice the capacitance of the CDAC capacitor.

3. The ADC circuit according to claim 1, further comprising a successive approximation register (SAR), wherein the SAR comprises a positive SAR output terminal and a negative SAR output terminal, wherein: To offset the analog signal by a reference voltage of the ADC circuit, the circuitry is configured to set the digital output of the positive SAR output terminal and the digital output of the negative SAR output terminal to values ​​between zero and a full-scale digital value of the ADC circuit.

4. The ADC circuit according to claim 1, further comprising a successive approximation register (SAR), the SAR comprising a positive SAR output terminal and a negative SAR output terminal, wherein in order to offset the analog signal by a reference voltage of the ADC circuit, the circuit system is configured to: setting the digital output of the positive SAR output terminal to digital zero; and The digital output of the negative SAR output terminal is set to a full-scale digital value of the ADC circuit.

5. The ADC circuit according to claim 3 or 4, wherein: The circuitry is configured to offset the analog signal by a reference voltage of the ADC circuit during a sampling phase.

6. The ADC circuit according to claim 5, wherein: During the sampling phase, the circuitry is configured to sample the received analog signal relative to a common mode voltage of the analog signal.

7. The ADC circuit according to claim 3 or 4, further comprising a comparator, the comparator comprising a non-inverting input terminal and an inverting input terminal, wherein the SAR is configured to receive an output of the comparator.

8. The ADC circuit according to claim 7, wherein: a first CDAC connected to the non-inverting input terminal through a first CDAC capacitor in the ADC circuit, the first CDAC configured to receive a digital output from the positive SAR output terminal; and A second CDAC is connected to the inverting input terminal through a second CDAC capacitor in the ADC circuit, and the second CDAC is configured to receive the digital output from the negative SAR output terminal.

9. The ADC circuit according to claim 8, wherein: During the hold and transfer phases, the circuit system is configured to: resetting the digital output of the positive SAR output terminal and the digital output of the negative SAR output terminal to a mid-scale digital value of the ADC circuit, and A SAR algorithm is performed by each of the first CDAC and the second CDAC based on the output of the comparator in each decision cycle.

10. The ADC circuit according to claim 1, wherein: The circuit system is configured to convert the received analog signal, where the received analog signal is a differential analog signal or a single-ended analog signal.

11. A method for an analog-to-digital converter (ADC) circuit, comprising: receiving an analog signal including a voltage amplitude at a first input terminal and a second input terminal of the ADC circuit; offsetting the received analog signal by a reference voltage of the ADC circuit; doubling the received analog signal; as well as A digital value approximating the voltage amplitude of the analog signal is output.

12. The method according to claim 11, in, The ADC circuit includes a switched capacitor circuit connected to the first input terminal and the second input terminal, Wherein, the switched capacitor circuit includes a sampling capacitor and a capacitance digital-to-analog converter CDAC capacitor, and wherein doubling the received analog signal comprises sampling the received analog signal using the sampling capacitor, and The capacitance of the sampling capacitor is twice the capacitance of the CDAC capacitor.

13. The method according to claim 11, in, The ADC circuit comprises a successive approximation register SAR, wherein the SAR comprises a positive SAR output terminal and a negative SAR output terminal, In order to offset the analog signal by a reference voltage of the ADC circuit, the method includes: setting the digital output at the positive SAR output terminal to digital zero; and The digital output at the negative SAR output terminal is set to a full-scale value of the ADC circuit.

14. The method according to claim 13, further comprising: During the sampling phase, the analog signal is offset by a reference voltage of the ADC circuit.

15. The method according to claim 14, further comprising: During the sampling phase, the received analog signal is sampled relative to a common mode voltage of the analog signal.

16. The method according to claim 13, in, The ADC circuit further includes a comparator, wherein the comparator includes a non-inverting input terminal and an inverting input terminal. The method also includes receiving, by the SAR, an output of the comparator.

17. The method according to claim 16, wherein: The ADC circuit further includes: a first CDAC connected to the non-inverting input terminal through a first CDAC capacitor in the ADC circuit, the method further comprising receiving, by the first CDAC, a digital output from the positive SAR output terminal; and A second CDAC is connected to the inverting input terminal through a second CDAC capacitor in the ADC circuit, and the method further includes receiving, by the second CDAC, a digital output from the negative SAR output terminal.

18. The method according to claim 17, further comprising: During the hold and transfer phases: resetting the digital output of the positive SAR output terminal and the digital output of the negative SAR output terminal to a mid-scale value of the ADC circuit, and A SAR algorithm is performed by each of the first CDAC and the second CDAC based on the output of the comparator in each decision cycle.

19. The method according to claim 11, wherein: The received analog signal includes a differential analog signal or a single-ended analog signal.

20. An analog-to-digital converter (ADC) circuit, the ADC circuit comprising: a first input terminal and a second input terminal; as well as A circuit system configured to: receiving an analog signal including a voltage amplitude at the first input terminal and the second input terminal; In response to the received analog signal being a single-ended analog signal, sampling the received analog signal and shifting the received analog signal by a reference voltage of the ADC circuit; doubling the received analog signal by halving the reference voltage during a conversion phase; as well as A digital value approximating the voltage amplitude of the analog signal is output.

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