Cyclic analog-to-digital converter and signal processing method thereof, readout circuit and image sensor
By designing a cyclic analog-to-digital converter including sampling and amplification circuit, analog-to-digital conversion circuit and encoding circuit, the problem of fast quantization and fixed-mode noise cancellation in high-speed image sensors is solved, and efficient noise removal and rapid quantization are achieved.
Patent Information
- Application Number
- CN202411870678.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-04-04
AI Technical Summary
The prior art is difficult to achieve rapid quantization and cancellation of fixed mode noise without increasing chip area and power consumption in high-speed image sensors.
A cyclic analog-to-digital converter is designed, including a sampling and amplification circuit, an analog-to-digital conversion circuit and a coding circuit. By sampling, amplifying, summing and comparing the input signal under the control of the control signal, the relevant dual sampling function is realized and the fixed mode noise is eliminated.
It realizes high-speed quantization and eliminates fixed mode noise without increasing chip area and power consumption, improves pixel signal quality, and is suitable for high-speed image sensors.
Smart Images
Figure CN119766243A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of circuit design, and in particular to a cyclic analog-to-digital converter and a signal processing method thereof, a readout circuit and an image sensor. Background Art
[0002] As a core component of modern imaging devices, CMOS Image Sensor (CIS) has important applications in consumer electronics, medical imaging, security monitoring, etc. CMOS image sensors generally include pixel units and readout circuits. Pixel units have fixed pattern noise due to transistor mismatch and other reasons. Usually, the Correlated Double Sampling (CDS) structure in the readout circuit is needed to eliminate this noise.
[0003] At present, the analog-to-digital converter used in the readout circuit of the image sensor is usually a ramp-type ADC (Analog to Digital Converter), which has the advantages of simple structure and small area, and can complete the CDS action during the quantization process without the need for an additional CDS module. However, the conversion speed of the ramp-type ADC is slow and requires 2 N It takes 1 clock cycle to complete N-bit data conversion, which also limits its application in high-speed CIS.
[0004] For high frame rate CIS, a cyclic analog-to-digital converter (Cyclic ADC) can be used. It only takes N clock cycles to complete N-bit data conversion, which is fast. However, the existing cyclic analog-to-digital converter circuit structure usually only has the analog-to-digital conversion function and does not have the CDS function. In order to achieve CDS to reduce noise, a separate CDS module is usually added in front of the cyclic analog-to-digital converter to perform differential processing on the pixel output signal before inputting it into the cyclic analog-to-digital converter, but this method will increase the chip area and power consumption; or, the cyclic analog-to-digital converter can quantize the pixel reset voltage and exposure voltage separately, and then perform differential processing on the two digital outputs, but this method will reduce the readout speed. Summary of the invention
[0005] The object of the present invention is to provide a cyclic analog-to-digital converter and its signal processing method, readout circuit and image sensor to solve the problem of how to eliminate fixed pattern noise while not increasing chip area and power consumption and high-speed quantization.
[0006] In order to solve the above technical problems, the present invention provides a cyclic analog-to-digital converter, comprising: The sampling and amplifying circuit is used to sample the input signal to obtain a sampling signal under the control of the control signal, and to amplify and sum the sampling signal; an analog-to-digital conversion circuit, used for comparing the sampling signal with the reference signal under the control of the control signal, so as to output a comparison signal to the sampling and amplifying circuit, so that the sampling and amplifying circuit performs a difference between the amplified pixel signal and the comparison signal; The encoding circuit is used to perform analog-to-digital conversion encoding on the comparison signal obtained by N cycles to output an N-bit digital signal, wherein N is a positive integer greater than or equal to 1.
[0007] Optionally, in the cyclic analog-to-digital converter, the sampling and amplification circuit includes a control unit, a sampling unit and an operational amplifier unit; the control unit is used to enable the sampling unit to sample the input signal and enable the operational amplifier unit to amplify and sum the sampled signal under the control of multiple control signals; wherein the input signal includes a pixel signal and a comparison signal, and the pixel signal is divided into a pixel reset signal and a pixel exposure signal.
[0008] Optionally, in the cyclic analog-to-digital converter, the control unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first sub-switch, a second sub-switch, a third sub-switch and a fourth sub-switch; the sampling unit includes a first capacitor, a second capacitor and a third capacitor; the operational amplifier unit includes an operational amplifier; One end of the first switch is connected to the pixel reset signal, and the other end is connected to one end of the second switch and the upper plate of the first capacitor; the other end of the second switch is connected to the output end of the operational amplifier; the lower plate of the first capacitor is connected to the negative input end of the operational amplifier; one end of the third switch is connected to the negative input end of the operational amplifier, and the other end is connected to the output end of the operational amplifier; one end of the fourth switch is connected to the pixel exposure signal, and the other end is connected to the output end of the operational amplifier through the first sub-switch; one end of the fifth switch is connected to the comparison signal, and the other end is connected to the upper plate of the second capacitor, and the other end is connected to The first sub-switch is connected to the output end of the operational amplifier; one end of the sixth switch is connected to the lower plate of the second capacitor and is connected to the common mode voltage through the third sub-switch, and the other end is connected to the negative input end of the operational amplifier; one end of the seventh switch is connected to the comparison signal, the other end is connected to the upper plate of the third capacitor, and the other end is connected to the output end of the operational amplifier through the second sub-switch; one end of the eighth switch is connected to the lower plate of the third capacitor and is connected to the common mode voltage through the fourth sub-switch, and the other end is connected to the negative input end of the operational amplifier; the positive input end of the operational amplifier is connected to the common mode voltage.
[0009] Optionally, in the cyclic analog-to-digital converter, the sampling and amplification circuit is configured as: When the control unit receives a first control signal, the first switch, the third switch, the fifth switch, the sixth switch, the second sub-switch, the third sub-switch, and the fourth sub-switch are closed, the second switch, the fourth switch, the seventh switch, the eighth switch, and the first sub-switch are opened, the first capacitor samples the pixel reset signal, and the second capacitor samples the comparison signal; When the control unit receives a second control signal, the first switch, the third switch, the fifth switch, the seventh switch, the eighth switch, the first sub-switch, and the third sub-switch are opened, and the second switch, the fourth switch, the sixth switch, the second sub-switch, and the fourth sub-switch are closed, and the second capacitor samples the pixel exposure signal; When the control unit receives a third control signal, the first switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the second sub-switch, and the fourth sub-switch are opened, and the second switch, the seventh switch, the eighth switch, the first sub-switch, and the third sub-switch are closed, and the third capacitor samples the comparison signal; When the control unit receives a fourth control signal, the first switch, the third switch, the fourth switch, the seventh switch, the eighth switch, the first sub-switch, and the third sub-switch are opened, the second switch, the fifth switch, the sixth switch, the second sub-switch, and the fourth sub-switch are closed, and the second capacitor samples the comparison signal.
[0010] Optionally, in the cyclic analog-to-digital converter, the analog-to-digital conversion circuit includes an analog-to-digital conversion unit and a digital-to-analog conversion unit; the analog-to-digital conversion unit is used to compare the sampling signal with the reference signal to output a conversion signal; the digital-to-analog conversion unit is used to output a comparison signal to the sampling and amplifying circuit according to the conversion signal under the control of a control signal, so that the sampling and amplifying circuit can perform a difference between the amplified pixel signal and the comparison signal.
[0011] Optionally, in the cyclic analog-to-digital converter, the analog-to-digital conversion unit includes a first comparator, a second comparator and a logic circuit; the positive input terminals of the first comparator and the second comparator are connected to a sampling signal, the negative input terminal of the first comparator is connected to a first reference signal, the negative input terminal of the second comparator is connected to a second reference signal, the output terminals of the first comparator and the second comparator are connected to a logic circuit, and the logic circuit outputs a conversion signal; wherein the first reference signal value is less than the second reference signal value.
[0012] Optionally, in the cyclic analog-to-digital converter, the analog-to-digital conversion circuit is configured as: When the digital-to-analog conversion unit receives the first control signal or the second control signal, the digital-to-analog conversion unit outputs a first comparison signal with a fixed value; When the digital-to-analog conversion unit receives a third control signal or a fourth control signal, if the sampling signal is less than the first reference signal value, the digital-to-analog conversion unit outputs a second comparison signal; if the sampling signal is greater than the first reference signal value and less than the second reference signal value, the digital-to-analog conversion unit outputs a third comparison signal; if the sampling signal is greater than the second reference signal value, the digital-to-analog conversion unit outputs a fourth comparison signal.
[0013] Optionally, in the cyclic analog-to-digital converter, the first comparison signal is the minimum value of the quantization range of the cyclic analog-to-digital converter; the second comparison signal is the minimum value of the quantization range of the cyclic analog-to-digital converter; the third comparison signal is the common mode voltage value; and the fourth comparison signal is the maximum value of the quantization range of the cyclic analog-to-digital converter.
[0014] In order to solve the above technical problems, the present invention further provides a signal processing method, which is applied to the cyclic analog-to-digital converter as described in any one of the above items, and the signal processing method comprises: Reset voltage sampling stage: In the first clock cycle, the pixel reset signal is sampled; Correlated double sampling stage: In the second clock cycle, the pixel exposure signal is sampled, and the pixel reset signal and the pixel exposure signal are compared and subtracted to obtain a comparison signal; Signal quantization stage: In the following N clock cycles, the comparison signal is cyclically summed and analog-to-digital conversion is performed to obtain a quantized pixel digital signal.
[0015] In order to solve the above technical problem, the present invention further provides a readout circuit, comprising the cyclic analog-to-digital converter as described in any one of the above items.
[0016] In order to solve the above technical problem, the present invention further provides an image sensor, comprising the readout circuit as described above.
[0017] The cyclic analog-to-digital converter and its signal processing method, readout circuit and image sensor provided by the present invention include: a sampling amplifier circuit, which is used to sample the input signal under the control of a control signal to obtain a sampling signal, and amplify and sum the sampling signal; an analog-to-digital conversion circuit, which is used to compare the sampling signal with the reference signal under the control of the control signal to output a comparison signal to the sampling amplifier circuit, so that the sampling amplifier circuit makes a difference between the amplified pixel signal and the comparison signal; and an encoding circuit, which is used to perform analog-to-digital conversion encoding on the comparison signal obtained by N cycles to output an N-bit digital signal, wherein N is a positive integer greater than or equal to 1. The input signal is amplified and summed by the sampling amplifier circuit and the analog-to-digital conversion circuit, and the correlated double sampling function is realized, so that fixed pattern noise can be eliminated without separately setting up a correlated double sampling module, and at the same time, a faster conversion speed can be maintained without increasing the chip area and power consumption, solving the problem of how to eliminate fixed pattern noise while not increasing the chip area and power consumption and high-speed quantization. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 A structural block diagram of a cyclic analog-to-digital converter provided in this embodiment; Figure 2 A circuit schematic diagram of the sampling and amplifying circuit provided in this embodiment; Figure 3 A timing control diagram of the sampling and amplifying circuit provided in this embodiment; Figure 4 A circuit schematic diagram of the analog-to-digital conversion unit provided in this embodiment; Figure 5 This is a flowchart of the signal processing method provided in this embodiment. DETAILED DESCRIPTION
[0019] The cyclic analog-to-digital converter and its signal processing method and readout circuit proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.
[0020] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0021] This embodiment provides a cyclic analog-to-digital converter, such as Figure 1 As shown, including: The sampling and amplifying circuit is used to sample the input signal to obtain a sampling signal under the control of the control signal, and to amplify and sum the sampling signal; an analog-to-digital conversion circuit, used for comparing the sampling signal with the reference signal under the control of the control signal, so as to output a comparison signal to the sampling and amplifying circuit, so that the sampling and amplifying circuit performs a difference between the amplified pixel signal and the comparison signal; The encoding circuit is used to perform analog-to-digital conversion encoding on the comparison signal obtained by N cycles to output an N-bit digital signal, wherein N is a positive integer greater than or equal to 1.
[0022] The cyclic analog-to-digital converter provided in this embodiment implements amplification and summation of the input signal through a sampling amplifier circuit and an analog-to-digital conversion circuit, thereby realizing a correlated double sampling function, thereby eliminating fixed pattern noise without having to set up a separate correlated double sampling module, and maintaining a relatively fast conversion speed without increasing the chip area and power consumption, thereby solving the problem of how to eliminate fixed pattern noise while not increasing the chip area and power consumption and achieving high-speed quantization.
[0023] Furthermore, in this embodiment, the sampling and amplification circuit includes a control unit, a sampling unit and an operational amplifier unit; the control unit is used to enable the sampling unit to sample the input signal and enable the operational amplifier unit to amplify and sum the sampled signal under the control of multiple control signals; wherein the input signal includes a pixel signal and a comparison signal, and the pixel signal is divided into a pixel reset signal and a pixel exposure signal.
[0024] Specifically, in this embodiment, if Figure 2As shown, the control unit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first sub-switch Ss1, a second sub-switch Ss2, a third sub-switch Ss3 and a fourth sub-switch Ss4; the sampling unit includes a first capacitor C1, a second capacitor C2 and a third capacitor C3; and the operational amplifier unit includes an operational amplifier AMP.
[0025] One end of the first switch S1 is connected to the pixel reset signal Vrst, and the other end is connected to one end of the second switch S2 and the upper plate of the first capacitor C1; the other end of the second switch S2 is connected to the output end of the operational amplifier AMP; the lower plate of the first capacitor C1 is connected to the negative input end of the operational amplifier AMP; one end of the third switch S3 is connected to the negative input end of the operational amplifier AMP, and the other end is connected to the output end of the operational amplifier AMP; one end of the fourth switch S4 is connected to the pixel exposure signal Vsig, and the other end is connected to the output end of the operational amplifier AMP through the first sub-switch Ss1; one end of the fifth switch S5 is connected to the comparison signal V DAC , the other end is connected to the upper plate of the second capacitor C2, and the other end is connected to the output end of the operational amplifier AMP through the first sub-switch Ss1; one end of the sixth switch S6 is connected to the lower plate of the second capacitor C2, and is connected to the common mode voltage Vcom through the third sub-switch Ss3, and the other end is connected to the negative input end of the operational amplifier AMP; one end of the seventh switch S7 is connected to the comparison signal V DAC , the other end is connected to the upper plate of the third capacitor C3, and the other end is connected to the output end of the operational amplifier AMP through the second sub-switch Ss2; one end of the eighth switch S8 is connected to the lower plate of the third capacitor C3, and is connected to the common mode voltage Vcom through the fourth sub-switch Ss4, and the other end is connected to the negative input terminal of the operational amplifier AMP; the positive input terminal of the operational amplifier AMP is connected to the common mode voltage Vcom.
[0026] Combination Figure 2 and Figure 3 The working state of the sampling and amplifying circuit provided in this embodiment is described as follows. Figure 3 In to Respectively represent seven sub-control signals, which are used to control the on-off state of each switch and sub-switch. In this embodiment, to When it is at a high level, the switch it controls is closed and turned on; to When it is low, the switch it controls is off. And, Control the on / off state of the first switch S1 and the third switch S3, Control the on / off state of the second switch S2, Control the on / off state of the fourth switch S4, Control the on / off states of the seventh switch S7, the eighth switch S8 and the first sub-switch Ss1, Control the on / off states of the sixth switch S6, the second sub-switch Ss2 and the fourth sub-switch Ss4, Control the on / off state of the third sub-switch Ss3, Control the on / off state of the fifth switch S5.
[0027] (1) When the control unit receives the first control signal, that is, when the sub-control signal to for Figure 3 In the middle a state, this is the first stage of the correlated double sampling, the first switch S1, the third switch S3, the fifth switch S5, the sixth switch S6, the second sub-switch Ss2, the third sub-switch Ss3, and the fourth sub-switch Ss4 are closed, the second switch S2, the fourth switch S4, the seventh switch S7, the eighth switch S8, and the first sub-switch Ss1 are opened, the first capacitor C1 samples the pixel reset signal Vrst, and the second capacitor C2 samples the comparison signal V DAC Sampling is performed, and the third capacitor C3 is in a reset state. The charge stored in each capacitor in state a is expressed as:
[0028]
[0029]
[0030] in, represents the amount of charge stored in the first capacitor C1 in state a, represents the amount of charge stored in the second capacitor C2 in state a, represents the amount of charge stored in the third capacitor C3 when in state a; Represents the comparison signal input in state a; Represents common mode voltage; Represents pixel reset signal; represents the capacitance value of the first capacitor C1, represents the capacitance value of the third capacitor C3.
[0031] (2) When the control unit receives the second control signal, that is, when the sub-control signal to for Figure 3In the b state, which is the second stage of correlated double sampling, the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the eighth switch S8, the first sub-switch Ss1, and the third sub-switch Ss3 are disconnected, the second switch S2, the fourth switch S4, the sixth switch S6, the second sub-switch Ss2, and the fourth sub-switch Ss4 are closed, and the second capacitor C2 samples the pixel exposure signal Vsig.
[0032] At this time, the first capacitor C1 will be connected between the input and output terminals of the operational amplifier AMP. Since the seventh switch S7 changes from closed to open, the upper plate voltage of the second capacitor C2 jumps, and the charge will be redistributed between the first capacitor C1 and the second capacitor C2. The positive input terminal of the operational amplifier AMP is connected to the common mode voltage Vcom, so when the node voltage between the first capacitor C1 and the second capacitor C2 reaches the common mode voltage Vcom, the sampling amplifier circuit as a whole reaches a stable state. In addition, the third capacitor C3 is connected to the output terminal of the sampling amplifier circuit (the output terminal of the operational amplifier AMP). After the charge transfer is completed and the sampling amplifier circuit reaches a stable state, the charge stored in each capacitor is expressed as:
[0033]
[0034]
[0035] in, represents the amount of charge stored in the first capacitor C1 in state b, represents the amount of charge stored in the second capacitor C2 in state b, represents the amount of charge stored in the third capacitor C3 when in state b; represents the low-frequency gain of the operational amplifier; Represents the voltage signal output by the operational amplifier in state b.
[0036] The first capacitor C1 and the second capacitor C2 are regarded as a whole, which follows the law of charge conservation between state a and state b, that is, , so the output voltage at the end of state b is:
[0037] In an ideal situation, assuming that the capacitance C1=C2=C3=C, the operational amplifier gain is infinite, that is, Av=+∞, the formula can be simplified to:
[0038] (3) When the control unit receives the third control signal, that is, when the sub-control signal to for Figure 3 In the middle c state, which is the first stage of signal quantization, the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the second sub-switch Ss2, and the fourth sub-switch Ss4 are disconnected, the second switch S2, the seventh switch S7, the eighth switch S8, the first sub-switch Ss1, and the third sub-switch Ss3 are closed, and the third capacitor C3 is connected to the comparison signal V DAC Take samples.
[0039] At this time, after changing from state b to state c, the connection states of the second capacitor C2 and the third capacitor C3 are interchanged, and the third capacitor C3 is connected to the comparison voltage V DAC(c) , V DAC Determined by the input voltage of the clock cycle, in this embodiment, V DAC(c) Less than Vout(b) is used as an example to illustrate the charge transfer process in this state: due to the decrease in the voltage of the upper plate of the third capacitor C3, the voltage of the negative input terminal of the operational amplifier AMP will jump downward. Due to the negative feedback effect, the output current of the operational amplifier AMP will charge the negative input terminal of the operational amplifier AMP. In this process, the electrons from the lower plate of the third capacitor C3 flow to the lower plate of the first capacitor C1, and the electrons flow into the upper plate of the third capacitor C3. Therefore, the charge of the third capacitor C3 continues to decrease, and the voltage difference across the third capacitor C3 also continues to decrease, so that the potential of the negative input terminal of the operational amplifier AMP continues to increase and gradually returns to Vcom. At the same time, the charge of the first capacitor C1 increases, and the voltage difference across the first capacitor C1 increases. That is, the charge in the third capacitor C3 will be transferred to the first capacitor C1, and when the potential of the negative input terminal of the operational amplifier AMP is Vcom, the charge transfer ends. The second capacitor C2 is connected to the output terminal of the sampling amplifier circuit (the output terminal of the operational amplifier AMP). After the charge transfer is completed, the charge stored in each capacitor is expressed as:
[0040]
[0041]
[0042] The third capacitor C3 and the first capacitor C1 are regarded as a whole, which follows the charge conservation law between state b and state c, that is, , so the output voltage at the end of state c is:
[0043] Similar to process (2), this formula can be simplified to:
[0044] (4) When the control unit receives the fourth control signal, that is, when the sub-control signal to for Figure 3 In the middle d state, this is the second stage of signal quantization, the first switch S1, the third switch S3, the fourth switch S4, the seventh switch S7, the eighth switch S8, the first sub-switch Ss1, and the third sub-switch Ss3 are disconnected, the second switch S2, the fifth switch S5, the sixth switch S6, the second sub-switch Ss2, and the fourth sub-switch Ss4 are closed, and the second capacitor C2 is connected to the comparison signal V DAC Take samples.
[0045] At this time, after changing from state c to state d, the connection states of the second capacitor C2 and the third capacitor C3 are exchanged again, and the second capacitor C2 is connected to the comparison voltage V DAC(d) , the charge in the second capacitor C2 will be transferred to the first capacitor C1, and the third capacitor C3 is connected to the output end of the sampling amplifier circuit (the output end of the operational amplifier AMP). At this time, the connection method of the second capacitor C2 and the first capacitor C1 is the same as the connection method of the third capacitor C3 and the first capacitor C1 in state c. The charge transfer process of this state is also similar to that of state c, so it will not be repeated here, and you can refer to each other. The output voltage at the end of state d is expressed as:
[0046] This formula can be simplified to:
[0047] The sampling and amplifying circuit provided in this embodiment completes the sampling and subtraction of the pixel reset signal and the pixel exposure signal in states a and b; then it works cyclically between states c and d, and in each state, it amplifies the output voltage signal of the previous cycle and compares it with the comparison signal V DAC In practical applications, the operational amplifier can achieve a 2-fold amplification of the sampled signal. In this way, in each state of state c and state d, the output voltage of the previous cycle is amplified by two and combined with V DAC The difference is made, and in each cycle, the analog-to-digital conversion circuit outputs a 2-bit code value, and finally the encoding circuit performs staggered addition on the code value output in each cycle to obtain an N-bit digital output. Each state c is called a cycle, and then after N cycles, the cyclic analog-to-digital converter can complete the analog-to-digital conversion of N bits. Therefore, the cyclic analog-to-digital converter proposed in the present invention performs correlated double sampling on the pixel output signal and completes the analog-to-digital conversion of N bits, which requires a total of N+2 clock cycles.
[0048] Furthermore, in this embodiment, if Figure 1 As shown, the analog-to-digital conversion circuit includes an analog-to-digital conversion unit and a digital-to-analog conversion unit; the analog-to-digital conversion unit is used to compare the sampling signal with the reference signal to output a conversion signal; the digital-to-analog conversion unit is used to output a comparison signal to the sampling and amplifying circuit according to the conversion signal under the control of a control signal, so that the sampling and amplifying circuit can perform a difference between the amplified pixel signal and the comparison signal.
[0049] Specifically, in this embodiment, if Figure 4 As shown, taking a cyclic analog-to-digital converter with a 1.5 bit / cycle architecture as an example, the analog-to-digital conversion unit includes a first comparator comp1, a second comparator comp2 and a logic circuit; the positive input terminals of the first comparator comp1 and the second comparator comp2 are connected to sampling signals, the negative input terminals of the first comparator comp1 are connected to a first reference signal, the negative input terminals of the second comparator comp2 are connected to a second reference signal, the output terminals of the first comparator comp1 and the second comparator comp2 are connected to the logic circuit, and the logic circuit outputs a conversion signal; wherein the first reference signal value is less than the second reference signal value.
[0050] In practical applications, if the quantization range of the cyclic analog-to-digital converter is [Vcom-Vref, Vcom+Vref], then the thresholds of the two comparators are Vcom-Vref / 4 and Vcom+Vref / 4, respectively, thus ensuring the consistency of the output results of the comparators.
[0051] The analog-to-digital conversion unit works in state c and state d. The input voltage of each cycle will be sent to the analog-to-digital conversion unit for comparison. The comparison result will output a 2-bit code value (conversion signal) through the logic circuit. The code value will control the digital-to-analog conversion unit to output the correct V in this cycle. DAC At the same time, the code value will be sent to the encoding circuit to generate the final digital signal.
[0052] In this embodiment, the digital-to-analog conversion unit may adopt a simple switch structure, so as to reduce the area and power consumption of the cyclic analog-to-digital converter as much as possible.
[0053] In this embodiment, the analog-to-digital conversion circuit is configured as follows: (1) When the digital-to-analog conversion unit receives the first control signal or the second control signal, the digital-to-analog conversion unit outputs a first comparison signal with a fixed value.
[0054] The first control signal and the second control signal are the first control signal and the second control signal received by the control unit. Since the first control signal and the second control signal correspond to the correlated double sampling stage, the digital-to-analog conversion unit is controlled to output a fixed first comparison signal (Vcom-Vref) at this time, so as to ensure that the signal output by the sampling amplifier circuit is within the quantization range of the cyclic analog-to-digital converter in state b.
[0055] (2) When the digital-to-analog conversion unit receives the third control signal or the fourth control signal, if the sampling signal is less than the first reference signal value, the digital-to-analog conversion unit outputs a second comparison signal; if the sampling signal is greater than the first reference signal value and less than the second reference signal value, the digital-to-analog conversion unit outputs a third comparison signal; if the sampling signal is greater than the second reference signal value, the digital-to-analog conversion unit outputs a fourth comparison signal.
[0056] The third control signal and the fourth control signal are the third control signal and the fourth control signal received by the control unit. Since the third control signal and the fourth control signal correspond to the signal quantization stage (state c and state d), the digital-to-analog conversion unit is controlled to output a comparison signal corresponding to the conversion signal output by the analog-to-digital conversion unit, thereby ensuring that the signal finally output by the sampling and amplification circuit is accurate.
[0057] This embodiment provides a comparison table of the output code value (conversion signal) of the analog-to-digital conversion unit and the output voltage (comparison signal) of the digital-to-analog conversion unit in the signal quantization stage, as shown in Table 1:
[0058] Table 1. Analog-to-digital conversion unit output code value = and digital-to-analog conversion unit output voltage comparison table It can be seen from Table 1 that in the signal quantization stage (state c and state d), if the sampling signal Vin is less than the first reference signal value, that is, Vin<Vcom-Vref / 4, the code value output by the analog-to-digital conversion unit is 00, and the digital-to-analog conversion unit correspondingly outputs the second comparison signal Vcom-Vref; if the sampling signal is greater than the first reference signal value and less than the second reference signal value, that is, Vcom-Vref / 4<Vin<Vcom+Vref / 4, the code value output by the analog-to-digital conversion unit is 01, and the digital-to-analog conversion unit correspondingly outputs the third comparison signal Vcom; if the sampling signal is greater than the second reference signal value, that is, Vcom+Vref / 4<Vin, the code value output by the analog-to-digital conversion unit is 10, and the digital-to-analog conversion unit correspondingly outputs the fourth comparison signal.
[0059] Of course, in other embodiments, the code value output by the analog-to-digital conversion unit can be set by itself, as long as different code values correspond to different comparison signals output by the digital-to-analog conversion unit. And, in other embodiments, the conversion signal output by the analog-to-digital conversion unit can also be an analog signal. This application does not limit this.
[0060] In addition, in this embodiment, by setting the first comparison signal to the minimum value of the quantization range of the cyclic analog-to-digital converter; setting the second comparison signal to the minimum value of the quantization range of the cyclic analog-to-digital converter; setting the third comparison signal to the common-mode voltage value; and setting the fourth comparison signal to the maximum value of the quantization range of the cyclic analog-to-digital converter, it is possible to ensure that after N cycles, the signal output by the sampling and amplification circuit is within the quantization range of the cyclic analog-to-digital converter, thereby ensuring that the cyclic analog-to-digital converter can normally perform correlated double sampling and analog-to-digital conversion.
[0061] The cyclic analog-to-digital converter provided in this embodiment works as follows in the correlated double sampling stage: first, a pixel reset signal is connected, and the sampling unit completes sampling of the pixel reset signal and uses the pixel reset signal as a reference signal; then, a pixel exposure signal is connected, and the sampling unit completes sampling of the pixel exposure signal, and the sampled pixel exposure signal is sent to the analog-to-digital conversion unit for comparison with the pixel reset signal to obtain a comparison signal; thereafter, the pixel exposure signal is amplified by the operational amplifier unit and subtracted from the comparison signal, thereby removing the fixed pattern noise in the pixel exposure signal.
[0062] The cyclic analog-to-digital converter provided in this embodiment works as follows in the signal quantization stage: first, the input signal is connected, the sampling unit completes the sampling of the input signal, and the sampled signal obtained after sampling is sent to the analog-to-digital conversion unit for comparison with the reference voltage. The comparison result controls the digital-to-analog conversion unit to output different comparison signals, and the sampling signal is amplified by the operational amplifier unit and subtracted from the comparison signal to obtain the output signal of the cycle; then, the input signal path is disconnected, so that the output signal is used as the input signal of the next cycle to repeat the above-mentioned amplification and summation operation; after N cycles, an N-bit digital output can be obtained. In this way, the analog-to-digital conversion function of the cyclic analog-to-digital converter is realized.
[0063] The cyclic analog-to-digital converter provided in this embodiment only adds a few switches in the sampling and amplifying circuit. Through the circuit structure design of the sampling and amplifying circuit and by controlling the on-off state of the switch, not only can correlated double sampling be implemented to remove fixed pattern noise and improve the quality of pixel signals, but also only N+2 clock cycles are required to implement correlated double sampling of pixel output signals and complete N-bit analog-to-digital conversion, which greatly saves data conversion time and improves quantization efficiency. The converter is suitable for high-speed image sensors.
[0064] This embodiment also provides a signal processing method, which is applied to the cyclic analog-to-digital converter as described above. Figure 5 As shown, the signal processing method includes: Reset voltage sampling stage: In the first clock cycle, the pixel reset signal is sampled; Correlated double sampling stage: In the second clock cycle, the pixel exposure signal is sampled, and the pixel reset signal and the pixel exposure signal are compared and subtracted to obtain a comparison signal; Signal quantization stage: In the following N clock cycles, the comparison signal is cyclically summed and analog-to-digital conversion is performed to obtain a quantized pixel digital signal.
[0065] The signal processing method provided in this embodiment can not only implement correlated double sampling in the first two clock cycles to remove fixed pattern noise and improve the pixel signal quality, but also can implement correlated double sampling of the pixel output signal and complete N-bit analog-to-digital conversion in only N+2 clock cycles, which greatly saves data conversion time and improves quantization efficiency. It is suitable for high-speed image sensors.
[0066] Furthermore, this embodiment further provides a readout circuit, comprising the cyclic analog-to-digital converter as described above.
[0067] In practical applications, the readout circuit can be applied to an image sensor. Also, the cyclic analog-to-digital converter of the readout circuit can be implemented using a 1.5 bit / cycle architecture, a 2.5 bit / cycle architecture, or a multi-stage cyclic ADC structure, which is not limited in this application.
[0068] The use of a 1.5 bit / cycle architecture, a 2.5 bit / cycle architecture or a multi-stage Cyclic ADC structure can utilize a redundant bit correction algorithm to eliminate non-ideal effects caused by comparator threshold offset. As in the above example, when a 1.5 bit / cycle architecture is used, the analog-to-digital conversion unit includes 2 comparators, and each cycle outputs a 2-bit code value; when a 2.5 bit / cycle architecture is used, those skilled in the art can refer to the above example and know that the analog-to-digital conversion unit includes 6 comparators, each cycle outputs a 3-bit code value, and the thresholds of the 6 comparators are Vcom-5Vref / 8, Vcom-3Vref / 8, Vcom-1Vref / 8, Vcom+1Vref / 8, Vcom+3Vref / 8 and Vcom+5Vref / 8, respectively, so as to ensure the consistency of the output results of the comparators.
[0069] Furthermore, this embodiment further provides an image sensor, comprising the readout circuit as described above.
[0070] In practical applications, the readout circuit in the image sensor may also include other circuit structures such as a pixel array, a ramp signal generator, and a row selection decoder. The present application does not limit other circuit structures of the readout circuit.
[0071] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.
[0072] The cyclic analog-to-digital converter and its signal processing method, readout circuit and image sensor provided in this embodiment include: a sampling amplifier circuit, which is used to sample the input signal under the control of a control signal to obtain a sampling signal, and amplify and sum the sampling signal; an analog-to-digital conversion circuit, which is used to compare the sampling signal with the reference signal under the control of the control signal to output a comparison signal to the sampling amplifier circuit, so that the sampling amplifier circuit makes a difference between the amplified pixel signal and the comparison signal; an encoding circuit, which is used to perform analog-to-digital conversion encoding on the comparison signal obtained by N cycles to output an N-bit digital signal, wherein N is a positive integer greater than or equal to 1. The input signal is amplified and summed by the sampling amplifier circuit and the analog-to-digital conversion circuit, and the correlated double sampling function is realized, so that fixed pattern noise can be eliminated without separately setting up a correlated double sampling module, and at the same time, a faster conversion speed can be maintained without increasing the chip area and power consumption, solving the problem of how to eliminate fixed pattern noise while not increasing the chip area and power consumption and high-speed quantization.
[0073] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A cyclic analog-to-digital converter, characterized in that include: The sampling and amplifying circuit is used to sample the input signal to obtain a sampling signal under the control of the control signal, and to amplify and sum the sampling signal; an analog-to-digital conversion circuit, used for comparing the sampling signal with the reference signal under the control of the control signal, so as to output a comparison signal to the sampling and amplifying circuit, so that the sampling and amplifying circuit performs a difference between the amplified pixel signal and the comparison signal; The encoding circuit is used to perform analog-to-digital conversion encoding on the comparison signal obtained by N cycles to output an N-bit digital signal, wherein N is a positive integer greater than or equal to 1.
2. The cyclic analog-to-digital converter according to claim 1, characterized in that The sampling and amplification circuit includes a control unit, a sampling unit and an operational amplifier unit; the control unit is used to enable the sampling unit to sample the input signal under the control of multiple control signals, and enable the operational amplifier unit to amplify and sum the sampled signal; wherein the input signal includes a pixel signal and a comparison signal, and the pixel signal is divided into a pixel reset signal and a pixel exposure signal.
3. The cyclic analog-to-digital converter according to claim 2, characterized in that The control unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first sub-switch, a second sub-switch, a third sub-switch and a fourth sub-switch; the sampling unit includes a first capacitor, a second capacitor and a third capacitor; the operational amplifier unit includes an operational amplifier; One end of the first switch is connected to the pixel reset signal, and the other end is connected to one end of the second switch and the upper plate of the first capacitor; the other end of the second switch is connected to the output end of the operational amplifier; the lower plate of the first capacitor is connected to the negative input end of the operational amplifier; one end of the third switch is connected to the negative input end of the operational amplifier, and the other end is connected to the output end of the operational amplifier; one end of the fourth switch is connected to the pixel exposure signal, and the other end is connected to the output end of the operational amplifier through the first sub-switch; one end of the fifth switch is connected to the comparison signal, and the other end is connected to the upper plate of the second capacitor, and the other end is connected to The first sub-switch is connected to the output end of the operational amplifier; one end of the sixth switch is connected to the lower plate of the second capacitor and is connected to the common mode voltage through the third sub-switch, and the other end is connected to the negative input end of the operational amplifier; one end of the seventh switch is connected to the comparison signal, the other end is connected to the upper plate of the third capacitor, and the other end is connected to the output end of the operational amplifier through the second sub-switch; one end of the eighth switch is connected to the lower plate of the third capacitor and is connected to the common mode voltage through the fourth sub-switch, and the other end is connected to the negative input end of the operational amplifier; the positive input end of the operational amplifier is connected to the common mode voltage.
4. The cyclic analog-to-digital converter according to claim 3, characterized in that The sampling and amplifying circuit is configured as follows: When the control unit receives a first control signal, the first switch, the third switch, the fifth switch, the sixth switch, the second sub-switch, the third sub-switch, and the fourth sub-switch are closed, the second switch, the fourth switch, the seventh switch, the eighth switch, and the first sub-switch are opened, the first capacitor samples the pixel reset signal, and the second capacitor samples the comparison signal; When the control unit receives a second control signal, the first switch, the third switch, the fifth switch, the seventh switch, the eighth switch, the first sub-switch, and the third sub-switch are opened, and the second switch, the fourth switch, the sixth switch, the second sub-switch, and the fourth sub-switch are closed, and the second capacitor samples the pixel exposure signal; When the control unit receives a third control signal, the first switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the second sub-switch, and the fourth sub-switch are opened, and the second switch, the seventh switch, the eighth switch, the first sub-switch, and the third sub-switch are closed, and the third capacitor samples the comparison signal; When the control unit receives a fourth control signal, the first switch, the third switch, the fourth switch, the seventh switch, the eighth switch, the first sub-switch, and the third sub-switch are opened, the second switch, the fifth switch, the sixth switch, the second sub-switch, and the fourth sub-switch are closed, and the second capacitor samples the comparison signal.
5. The cyclic analog-to-digital converter according to claim 1, characterized in that The analog-to-digital conversion circuit includes an analog-to-digital conversion unit and a digital-to-analog conversion unit; the analog-to-digital conversion unit is used to compare the sampling signal with the reference signal to output a conversion signal; the digital-to-analog conversion unit is used to output a comparison signal to the sampling and amplifying circuit according to the conversion signal under the control of a control signal, so that the sampling and amplifying circuit can perform a difference between the amplified pixel signal and the comparison signal.
6. The cyclic analog-to-digital converter according to claim 5, characterized in that The analog-to-digital conversion unit includes a first comparator, a second comparator and a logic circuit; the positive input terminals of the first comparator and the second comparator are connected to a sampling signal, the negative input terminal of the first comparator is connected to a first reference signal, the negative input terminal of the second comparator is connected to a second reference signal, the output terminals of the first comparator and the second comparator are connected to a logic circuit, and the logic circuit outputs a conversion signal; wherein the value of the first reference signal is less than the value of the second reference signal.
7. The cyclic analog-to-digital converter according to claim 6, characterized in that The analog-to-digital conversion circuit is configured as follows: When the digital-to-analog conversion unit receives the first control signal or the second control signal, the digital-to-analog conversion unit outputs a first comparison signal with a fixed value; When the digital-to-analog conversion unit receives the third control signal or the fourth control signal, if the sampling signal is less than the first reference signal value, the digital-to-analog conversion unit outputs a second comparison signal; If the sampling signal is greater than the first reference signal value and less than the second reference signal value, the digital-to-analog conversion unit outputs a third comparison signal; if the sampling signal is greater than the second reference signal value, the digital-to-analog conversion unit outputs a fourth comparison signal.
8. The cyclic analog-to-digital converter according to claim 7, characterized in that The first comparison signal is the minimum value of the quantization range of the cyclic analog-to-digital converter; the second comparison signal is the minimum value of the quantization range of the cyclic analog-to-digital converter; the third comparison signal is the common mode voltage value; and the fourth comparison signal is the maximum value of the quantization range of the cyclic analog-to-digital converter.
9. A signal processing method, applied to the cyclic analog-to-digital converter according to any one of claims 1 to 8, characterized in that: The signal processing method comprises: Reset voltage sampling stage: In the first clock cycle, the pixel reset signal is sampled; Correlated double sampling stage: In the second clock cycle, the pixel exposure signal is sampled, and the pixel reset signal and the pixel exposure signal are compared and subtracted to obtain a comparison signal; Signal quantization stage: In the following N clock cycles, the comparison signal is cyclically summed and analog-to-digital conversion is performed to obtain a quantized pixel digital signal.
10. A readout circuit, characterized in that: Comprising a cyclic analog-to-digital converter as described in any one of claims 1 to 8.
11. An image sensor, characterized in that: Comprising the readout circuit as claimed in claim 10.