Satellite communication system gateway side transmitting link based on DVB-RCS2

Abstract

The invention discloses a satellite communication system gateway side transmitting link based on DVB-RCS2. The satellite communication system gateway side transmitting link comprises an embedded module, a configuration control module, a data processing module, a data storage module, a transmitting channelizer, a data transmitting module, an asynchronous clock synchronization module and a GPS / BD synchronization module. The data storage module alternately caches and the data processing module adopts the time division multiplexing design, so that the data stream processing time is effectively shortened, and the system complexity and the hardware resource consumption are reduced. Besides, in the design of the transmitting channelizer, a time division multiplexing mechanism of a parallel link is introduced, a multi-phase filtering structure is combined, time division processing is carried out on signals of all channels in the bandwidth, and high calculation efficiency and real-time processing capacity are achieved. According to the invention, the problems of high hardware resource consumption and long processing delay in the multi-path signal transmitting link at the gateway side of the satellite communication system are effectively solved, and support is provided for efficient and reliable satellite communication.

Description

Technical Field

[0001] The invention relates to satellite communication technology, in particular to a satellite communication system gateway side transmission link based on DVB-RCS2. Background Art

[0002] In satellite communication systems, the implementation of the transmission link on the gateway side mainly relies on software control and processing. Although it is highly flexible, the processing speed and real-time performance are restricted. Especially in the scenario of high data rate transmission, the link implemented by software is prone to bottlenecks and is difficult to meet the actual application requirements. As a parallel processing device, FPGA (field programmable gate array) has gradually become an ideal choice for high-performance data processing due to its high speed and flexibility.

[0003] The transmission links on the gateway side of existing satellite communication systems are mostly based on software processing or ASIC (application-specific integrated circuit) DVB-S2(X) modulators. These two solutions are insufficient in flexibility and cost. The FPGA-based implementation method can not only improve the link processing speed through hardware acceleration, but also has flexible programmability to adapt to future standard upgrades and functional expansions. The combination of embedded modules based on dual-core processors and FPGAs can achieve efficient allocation of complex signal processing tasks in the link, ensuring the real-time performance of the system while reducing power consumption.

[0004] In practical applications, the transmission link on the gateway side of the satellite communication system includes multiple processing modules, and each module needs to work closely together to ensure seamless processing and efficient transmission of data streams. At present, there is still a lack of efficient hardware implementation solutions for how to better achieve efficient interconnection and control of these modules, especially in high-speed data transmission scenarios. Therefore, designing an efficient gateway-side transmission link hardware implementation method based on FPGA configuration to meet the high performance requirements of satellite communication systems has become the key to current technological development. Summary of the invention

[0005] In view of the problems existing in the prior art, the object of the present invention is to provide an efficient DVB-RCS2 satellite communication system gateway side transmission link implemented by FPGA hardware.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0007] A satellite communication system gateway side transmission link based on DVB-RCS2, comprising:

[0008] The embedded module is used to receive the superframe data and payload data including the configuration information sent by the protocol layer, and when receiving the configuration enable signal of the configuration control module, send the configuration instruction including the superframe data to the configuration control module, and perform absolute time synchronization according to the time base signal of the GPS / BD synchronization module;

[0009] A configuration control module is used to receive configuration instructions from the embedded module, parse the superframe data in the configuration instructions, configure the superframe parameter registers, and generate a configuration enable signal, a superframe enable signal, and a data storage timing control signal, and send them to the embedded module, the data processing module, and the data storage module respectively;

[0010] The data processing module is used to obtain the payload data from the embedded module and read the superframe parameters from the configuration control module when receiving the superframe enable signal, and perform data movement, scrambling, forward check, Turbo coding, adding known symbols, data mapping, symbol modulation and matched filtering on the payload data in accordance with the DVB-RCS2 signal processing standard based on the superframe parameters to generate a complex signal;

[0011] A data storage module is used to store the coded data after Turbo coding in the data processing module, and after receiving the data storage timing control signal from the configuration control module, sequentially release the stored coded data to the data processing module, so that the data processing module performs adding known symbols, data mapping, symbol modulation and matched filtering operations;

[0012] A transmission channelizer, used to synthesize narrowband sub-signals of the same bandwidth or different bandwidths into a wideband signal, receive the complex signal generated by the data processing module, and synthesize the complex signal into a baseband digital signal to send to the data transmission module;

[0013] The data transmission module is used to perform up-conversion processing on the baseband digital signal output from the transmission channelizer, generate an upper sideband RF signal in combination with the local oscillator signal, and convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link through digital-to-analog conversion;

[0014] Asynchronous clock synchronization module, used to connect embedded modules and external hardware modules using bus logic under the control of different clock domains, to achieve timing alignment between different clock domains;

[0015] The GPS / BD synchronization module is used to provide a unified time base reference for the entire system by receiving high-precision time signals from GPS / BD satellites.

[0016] Furthermore, the configuration control module specifically includes:

[0017] A register configuration unit is connected to the embedded module, and is used to receive and parse the configuration instructions sent by the embedded module, parse the configuration instructions, obtain superframe parameters including burst data length and payload waveform, and configure register space through timing control, wherein the register space is divided into a common register and a superframe register, the common register configures common data, and the superframe register configures superframe parameters;

[0018] Timing control unit, used to generate configuration enable signal I config (t), superframe enable signal I frame (t), data storage timing control signal h(t), configure enable signal I config (t) is sent to the embedded module, and the superframe enable signal I is set when the read / write flag signal F of the data storage module is 1. frame (t) is sent to the data processing module. When the read / write flag signal F of the data storage module is 0 and the working state flag tready of the data processing module is 1, the data storage timing control signal h(t) is sent to the data storage module. tready=1 indicates that the back end of the data processing module is in the read state.

[0019]

[0020] Where M represents the superframe update time interval, S represents the time in which the superframe configuration time is ahead of the superframe time, and N sym Indicates the number of symbols read from the data storage module, S sym represents the symbol rate, δ(t) represents the unit pulse sequence, and T[] represents the periodic correlation function;

[0021] The signal reading unit is used to obtain the read / write flag signal F from the data storage module, read the working status flag tready from the data processing module, and send it to the timing control unit.

[0022] Furthermore, the data processing module specifically includes:

[0023] The data moving unit obtains the payload data from the embedded module upon receiving the superframe enable signal;

[0024] A scrambling unit, used for scrambling the data output by the data moving unit;

[0025] A forward verification unit, used for forward verification of data output by the scrambling unit;

[0026] A Turbo coding unit, used for performing Turbo coding on the data output by the forward check unit according to the burst data length in the superframe parameter, and outputting the coded data to the data storage module after coding;

[0027] Adding a known symbol unit, used to add a preamble, a postamble and pilot data in the corresponding position of the coded data output by the data storage module according to the load waveform data in the superframe parameter;

[0028] A data mapping unit, used for mapping the data output by the adding known symbol unit to a corresponding point on the constellation diagram according to the load waveform data in the superframe parameters;

[0029] A symbol modulation unit, configured to modulate the data output from the data mapping unit into symbols according to the load waveform data in the superframe parameters;

[0030] The matched filter unit filters the symbols output by the symbol modulation unit according to the entire link information.

[0031] Furthermore, the matched filtering unit includes:

[0032] Memory, cache depth is The symbol output from the receiving symbol modulation unit is used to After the length, all symbols are released to the raised cosine filter, L span represents the cutoff length of the matched filter;

[0033] The matched filter is connected behind the memory and is used to perform matched filtering on the symbols. The time domain impulse response of the matched filter is:

[0034]

[0035] Where g(t) is the time domain impulse response, β is the roll-off factor, T is the symbol period, and T L for The length of the cache period.

[0036] Furthermore, the data storage module includes a first memory block and a second memory block, which are used to alternately store the encoded data output by the Turbo encoding unit.

[0037] Furthermore, the first memory block and the second memory block are both stored in burst data units, and an empty and full flag signal empty is set. When the first memory block or the second memory block stores a burst data, the empty and full flag signal empty of the memory block is 0, otherwise it is 1.

[0038] Further, the data storage module is provided with a write selector SEL1 and a read selector SEL2, SEL1 defaults to 0, SEL2 defaults to 0, when the empty in the first memory block is 1, SEL1 is switched to 1, SEL2 is switched to 0, so as to write data to the first memory block and read data from the second memory block; when the empty in the second memory block is 1, SEL1 is switched to 0, SEL2 is switched to 1, so as to write data to the second memory block and read data from the first memory block;

[0039] The data storage module generates a read-write flag signal F according to the empty and full flag signals of the first memory block and the second memory block, and sends it to the configuration control module. When the empty and full flag signal of the first memory block or the second memory block is empty=1, F=1, indicating a write state, otherwise F=0, indicating a read state; when the data storage module receives the data storage timing control signal h(t)=1, data is read from the corresponding memory block.

[0040] Furthermore, the transmit channelizer is based on a multiphase filtering structure and adopts a time division multiplexing mechanism, including an IDFT unit, a complex multiplication unit, a channel filtering unit, a symbol conversion unit, an interpolation unit and a storage addition unit connected in sequence, for realizing the integration and spectrum allocation of multi-channel data. The output signal of the transmit channelizer is:

[0041]

[0042] Where Y(n) represents the output signal of the transmit channelizer, X i (n) represents the complex data output by the data processing module after the i-th transmission channel is processed, IDFT[] represents the inverse discrete Fourier transform, K represents the number of channels, and h i (n) represents the channel filter, z K-1-i Represents the delay of the i-th transmission channel data.

[0043] Furthermore, the data transmission module includes:

[0044] An up-conversion unit, used to perform up-conversion processing on the baseband digital signal output from the transmit channelizer, and generate an upper sideband radio frequency signal in combination with a local oscillator signal;

[0045] The digital-to-analog conversion unit is used to convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link.

[0046] Furthermore, the GPS / BD synchronization module uses an adaptive product difference algorithm to perform clock convergence based on the second pulse generated by the GPS / BD receiving module.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] Aiming at the application requirements of the satellite communication system gateway side, the present invention designs an efficient transmission link hardware implementation scheme, which has the remarkable characteristics of resource saving and performance optimization. By configuring the control module and the data storage module, and adopting the working mode of alternating cache and alternating configuration, the time of parameter configuration and analysis is significantly shortened, and the overall operation efficiency of the system is greatly improved;

[0049] At the same time, the data processing module and the transmission channelizer work together through time division multiplexing, realizing the maximum sharing and reuse of hardware resources. This design effectively reduces the complexity and production cost of hardware implementation, showing excellent engineering adaptability and economy.

[0050] In addition, the present invention designs a matched filtering mechanism for caching header data based on comprehensive consideration of time slot scheduling and resource allocation. This mechanism not only improves the accuracy and efficiency of signal processing, but also enhances the robustness of the system under complex channel conditions, providing an important guarantee for the stable operation of the link.

[0051] The overall design scheme combines flexibility and reliability, reflecting innovative advantages in efficient use of hardware resources, optimization of data processing performance, and improvement of system stability. It provides an efficient and economical solution for the hardware implementation of the transmission link on the gateway side of the satellite system and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A partial structural block diagram of a transmission link on the satellite communication system gateway side based on DVB-RCS2 provided by the present invention;

[0053] Figure 2 It is a structural block diagram of the data storage module;

[0054] Figure 3 The figure is a comparison between the block diagram of the traditional transmit channelizer based on a polyphase filter structure (a) and the block diagram of the transmit channelizer based on a polyphase filter structure using a time division multiplexing mechanism (b);

[0055] Figure 4 Comparison of time flows with and without advance configuration;

[0056] Figure 5 Comparison of the burst processing time with and without the storage structure. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0058] The present invention provides a satellite communication system gateway side transmission link based on DVB-RCS2, such as Figure 1 As shown, including:

[0059] The embedded module 1 is used to receive the superframe data and the payload data including the payload data sent by the protocol layer, and when receiving the configuration enable signal of the configuration control module 2, send the configuration instruction including the superframe data to the configuration control module 2, and perform absolute time synchronization according to the time base signal of the GPS / BD synchronization module;

[0060] Configuration control module 2, used for receiving configuration instructions of embedded module 1, parsing superframe data in the configuration instructions, configuring superframe parameters in registers, and generating configuration enable signal, superframe enable signal and data storage timing control signal, and sending them to embedded module 1, data processing module and data storage module respectively;

[0061] The data processing module 3 is used to obtain the payload data from the embedded module 1 when receiving the superframe enable signal, read the superframe parameters from the configuration control module 2, and perform data movement, scrambling, forward check, Turbo coding, adding known symbols, data mapping, symbol modulation and matched filtering on the payload data in accordance with the DVB-RCS2 signal processing standard based on the superframe parameters to generate a complex signal;

[0062] The data storage module 4 is used to store the coded data after Turbo coding in the data processing module 3, and after receiving the data storage timing control signal from the configuration control module 2, sequentially release the stored coded data to the data processing module, so that the data processing module 3 performs the operations of adding known symbols, data mapping, symbol modulation and matched filtering;

[0063] The transmission channelizer 5 is used to synthesize narrowband sub-signals of the same bandwidth or different bandwidths into a broadband signal, receive the complex signal generated by the data processing module 3, and synthesize the complex signal into a baseband digital signal to send to the data transmission module;

[0064] The data transmission module is used to perform up-conversion processing on the baseband digital signal output from the transmission channelizer, generate an upper sideband RF signal in combination with the local oscillator signal, and convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link through digital-to-analog conversion;

[0065] An asynchronous clock synchronization module, used to connect the embedded module 1 and the external hardware module using bus logic under the control of different clock domains, so as to achieve timing alignment between different clock domains;

[0066] The GPS / BD synchronization module is used to provide a unified time base reference for the entire system by receiving high-precision time signals from GPS / BD satellites.

[0067] Each module is described in detail below.

[0068] The embedded module 1 adopts the microprocessor core (such as ARM Cortex series or MicroBlaze core) in the Xilinx SoC chip, which has efficient computing power and flexible task processing capabilities. The embedded module 1 not only supports complex logical operations and data processing, but also can efficiently run embedded operating systems (such as Linux or FreeRTOS) and other high-level control programs.

[0069] The embedded module 1 realizes seamless information and data interaction with the programmable logic part through the standardized AXI bus protocol. Through the AXI bus interface, the embedded module 1 can efficiently read or write data, complete tasks such as instruction distribution and parameter configuration, and receive data feedback from the programmable logic part. This design ensures high-speed communication and task collaboration between modules in the system, while reducing the coupling degree of the system.

[0070] In addition, the embedded module 1 achieves fast access to control signals through the AXI4-Lite interface and real-time transmission of high-speed data streams through the AXI4-Stream interface. This architecture not only meets the needs of low-bandwidth control tasks, but also is competent for high-bandwidth data processing tasks, further improving the operating efficiency and reliability of the overall system.

[0071] Wherein, the configuration control module 2 specifically includes:

[0072] The register configuration unit 201 is connected to the embedded module through bus timing, writes to the register space through timing control, and is used to receive and parse the configuration instructions sent by the embedded module 1, parse the configuration instructions, obtain the superframe parameters including the burst data length and the load waveform, and configure the register space through timing control. The register space is divided into a common register and a superframe register. The common register configures common data, and the superframe register configures superframe parameters. Specifically, the common register and the superframe register have 512 groups of registers respectively, and each register occupies 32 bits. Among them, the common register mainly includes registers such as version number, rate, number of channels, and status; the superframe register mainly includes superframe parameters, and the update time interval is 40ms. In order to save the time loss caused by superframe configuration and parameter parsing and allocation, the superframe registers are divided into two groups, and the configuration is switched in turn. The switching time is 40ms, so the data retention time in one group of superframe registers is 80ms, that is, the superframe update time interval M = 80ms; at the same time, the superframe parameter configuration needs to be performed S = 5ms in advance to perform parameter parsing and transmission; in addition, since the number of bursts is not fixed, the number of superframe registers that need to be configured needs to change accordingly. Therefore, after each configuration is completed, it is necessary to write an update register at the end to notify the completion of the superframe configuration;

[0073] The timing control unit 202 is used to generate a configuration enable signal I config (t), superframe enable signal I frame (t), data storage timing control signal h(t), configure enable signal I config (t) is sent to the embedded module 1, and the superframe enable signal I is set when the read / write flag signal F of the data storage module is 1. frame (t) is sent to the data processing module. When the read / write flag signal F of the data storage module is 0 and the working state flag tready of the data processing module is 1, the data storage timing control signal h(t) is sent to the data storage module. tready=1 indicates that the back end of the data processing module is in the read state.

[0074]

[0075] Where M represents the superframe update time interval, S represents the time in which the superframe configuration time is ahead of the superframe time, and N sym Indicates the number of symbols read from the data storage module, S symrepresents the symbol rate, δ(t) represents the unit pulse sequence, and T[] represents the periodic correlation function; the configuration enable signal is used to notify the embedded module to configure the superframe register, and is triggered cyclically at a fixed time, and is t=S ahead of the superframe enable signal, so as to configure and parse the superframe information in advance and prepare for data processing; the superframe enable signal is triggered after the configuration is completed, and is triggered cyclically at a fixed time, and is stably triggered at an interval of t=M, and is used to notify the payload data processing module to work; S <M。

[0076] The signal reading unit 203 is used to obtain the read / write flag signal F from the data storage module, read the working state flag tready from the data processing module, and send it to the timing control unit.

[0077] The data processing module 3 specifically includes:

[0078] The data transfer unit 301, upon receiving the superframe enable signal, obtains the payload data from the embedded module 1; realizes the communication bridge function between the data processing module 3 and the embedded module 1, not only supports the two-way transmission of data, but also can flexibly adjust the direction and priority of the data flow, so as to realize the efficient collaboration between the modules. Through the data transfer function, the system can quickly respond to the upper layer instructions, ensure the real-time requirements, and improve the operation efficiency of the overall link;

[0079] The scrambling unit 302 is used to scramble the data output by the moving unit 301;

[0080] A forward check unit 303, used for forward checking the data output by the scrambling unit 302;

[0081] A Turbo coding unit 304 is used to perform Turbo coding on the data output by the forward check unit 303 according to the burst data length in the superframe parameter, and output the coded data to the data storage module 4 after coding;

[0082] The known symbol adding unit 305 is used to add the preamble, postamble and pilot data in the corresponding position of the coded data output by the data storage module 4 according to the load waveform data in the superframe parameters;

[0083] The data mapping unit 306 is used to map the data output by the adding known symbol unit 305 to the corresponding point on the constellation diagram according to the load waveform data in the superframe parameters;

[0084] A symbol modulation unit 307, configured to modulate the data output from the data mapping unit 306 into symbols according to the payload waveform data in the superframe parameters;

[0085] The matched filtering unit 308 filters the symbols output by the symbol modulation unit 307 according to the entire link information.

[0086] The matched filter unit 308 includes:

[0087] Memory, cache depth is The symbol output from the receiving symbol modulation unit is used to After the length, all symbols are released to the raised cosine filter, L span represents the cutoff length of the matched filter;

[0088] The matched filter is connected behind the memory and is used to perform matched filtering on the symbols. The time domain impulse response of the matched filter is:

[0089]

[0090] Where g(t) is the time domain impulse response, β is the roll-off factor, T is the symbol period, and T L for The length of the cache period.

[0091] The matched filter unit 308 uses a root raised cosine filter to process the modulated data signal, so that the signal waveform matches the receiving filter characteristics of the receiving end, maximizes the signal-to-noise ratio (SNR), and effectively suppresses inter-symbol interference (ISI). The transmission quality of the signal is optimized and the accuracy of demodulation at the receiving end is improved. At the same time, the input and output interfaces of the raised cosine filter use symbol rate. In order to save data processing time and remove invalid symbols generated by filtering, the input port is connected The input signal of the filter is input in two parts. The first part is directly input into the memory. Data, the second part of the pipeline inputs symbol data.

[0092] In order to optimize the efficiency of hardware resource utilization, the entire data processing module adopts a time-division multiplexing operation mode. This design method can significantly reduce the required hardware resource investment while ensuring system performance. By accurately scheduling the data processing process and dividing the module functions in time, each processing unit runs in sequence in different time periods, thereby realizing resource sharing and maximizing utilization. Specifically, the time-division multiplexing method executes all processing links in the data processing module step by step in chronological order. This operating mode does not require an independent hardware logic unit for each processing link, but instead shares the same set of hardware resources, significantly reducing the amount of logic gates and memory occupied. In addition, through precise scheduling algorithms and pipeline design, the execution order of each processing link can be seamlessly connected, avoiding resource vacancy and task conflicts, and further improving the utilization efficiency of hardware.

[0093] Among them, Figure 2As shown, the data storage module 4 includes a first memory block FIFO1 and a second memory block FIFO2, which are used to alternately store the encoded data output by the Turbo encoding unit. The first memory block and the second memory block are both stored in burst data units, and an empty and full flag signal empty is set. When the first memory block or the second memory block stores a burst data, the empty and full flag signal empty of the memory block is 0, otherwise it is 1.

[0094] The data storage module is provided with a write selector SEL1 and a read selector SEL2, SEL1 defaults to 0, SEL2 defaults to 0, when the empty in the first memory block is 1, SEL1 is switched to 1, and SEL2 is switched to 0, so as to write data to the first memory block and read data from the second memory block; when the empty in the second memory block is 1, SEL1 is switched to 0, and SEL2 is switched to 1, so as to write data to the second memory block and read data from the first memory block.

[0095] The data storage module generates a read-write flag signal F according to the empty and full flag signals of the first memory block and the second memory block, and sends it to the configuration control module. When the empty and full flag signal of the first memory block or the second memory block is empty=1, F=1, indicating a write state, otherwise F=0, indicating a read state; when the data storage module receives the data storage timing control signal h(t)=1, data is read from the corresponding memory block.

[0096] The transmit channelizer 5 is based on a multiphase filtering structure, and includes an IDFT unit 501, a complex multiplication unit 502, a channel filtering unit 503, a symbol conversion unit 504, an interpolation unit 505 and a storage addition unit 506 connected in sequence, and is used to realize the integration and spectrum allocation of multi-channel data. The output signal of the transmit channelizer is:

[0097]

[0098] Where Y(n) represents the output signal of the transmit channelizer, X i (n) represents the complex data output by the data processing module after the i-th transmission channel is processed, IDFT[] represents the inverse discrete Fourier transform, K represents the number of channels, and h i (n) represents the channel filter, z K-1-i Indicates the delay of the data of the i-th transmission channel, i increases from 0 to K-1, and the first transmission channel has the maximum data delay, thereby realizing time division multiplexing and finally accumulating at the same time. i (n) is the data sequence after passing through the interpolation unit 505.

[0099] Traditional transmit channelizers such as Figure 3As shown, it can be seen that the transmit channelizer 5 of the present invention realizes the integration and spectrum allocation of multi-channel data, ensuring the efficient transmission of signals and the correct decoding at the receiving end; in order to improve resource utilization, each branch signal adopts a time division multiplexing mode to share the same set of channelizers, and multi-phase interpolation is used to improve the operational efficiency of subsequent filtering and Fourier transform.

[0100] The data transmission module includes an up-conversion unit and a digital-to-analog conversion unit. The up-conversion unit is used to up-convert the baseband digital signal output from the transmission channelizer and generate an upper sideband radio frequency signal in combination with a local oscillator signal; the digital-to-analog conversion unit is used to convert the upper sideband radio frequency signal into an analog signal that can be processed by a subsequent radio frequency link.

[0101] The asynchronous clock synchronization module uses bus logic under the control of different clock domains to link embedded modules and external hardware modules to achieve stable data transmission and precise timing alignment between different clock domains.

[0102] The GPS / BD synchronization module uses the high-precision clock signal provided by GPS to achieve system synchronization. By receiving time information from GPS / BD satellites, parsing and extracting UTC time and high-stability pulse signals, it provides an accurate reference clock to calibrate the local clock and unify the time of other modules, ensuring the system's timing is accurate and consistent, thereby meeting the needs of high-precision time synchronization.

[0103] Finally, the present invention is subjected to comparative experiments, and the experimental results are as follows Figure 4 and Figure 5 As shown, Figure 4 By comparing the time flow with and without the advance configuration, it can be seen that the present invention significantly reduces the waiting time and improves the efficiency; Figure 5 Comparison of the burst processing time after adopting the data storage module of the present invention and the burst processing time without adopting the present invention shows that the processing time of the present invention is faster and more efficient.

[0104] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0105] It should be understood that the above embodiments and descriptions only describe the principles, main features and advantages of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, and these changes and improvements all fall within the scope of protection of the present invention.

Claims

1. A satellite communication system gateway side transmission link based on DVB-RCS2, characterized in that: include: The embedded module is used to receive the superframe data and payload data including the configuration information sent by the protocol layer, and when receiving the configuration enable signal of the configuration control module, send the configuration instruction including the superframe data to the configuration control module, and perform absolute time synchronization according to the time base signal of the GPS / BD synchronization module; A configuration control module is used to receive configuration instructions from the embedded module, parse the superframe data in the configuration instructions, configure the superframe parameter registers, and generate a configuration enable signal, a superframe enable signal, and a data storage timing control signal, and send them to the embedded module, the data processing module, and the data storage module respectively; The data processing module is used to obtain the payload data from the embedded module and read the superframe parameters from the configuration control module when receiving the superframe enable signal, and perform data movement, scrambling, forward check, Turbo coding, adding known symbols, data mapping, symbol modulation and matched filtering on the payload data in accordance with the DVB-RCS2 signal processing standard based on the superframe parameters to generate a complex signal; A data storage module is used to store the coded data after Turbo coding in the data processing module, and after receiving the data storage timing control signal from the configuration control module, sequentially release the stored coded data to the data processing module, so that the data processing module performs adding known symbols, data mapping, symbol modulation and matched filtering operations; A transmission channelizer is used to synthesize narrowband sub-signals of the same bandwidth or different bandwidths into a wideband signal, receive the complex signal generated by the data processing module, and synthesize the complex signal into a baseband digital signal to pass to the data transmission module; The data transmission module is used to perform up-conversion processing on the baseband digital signal output from the transmission channelizer, generate an upper sideband RF signal in combination with the local oscillator signal, and convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link through digital-to-analog conversion; Asynchronous clock synchronization module, used to connect embedded modules and external hardware modules using bus logic under the control of different clock domains, to achieve timing alignment between different clock domains; The GPS / BD synchronization module is used to provide a unified time base reference for the entire system by receiving high-precision time signals from GPS / BD satellites.

2. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The configuration control module specifically includes: A register configuration unit is connected to the embedded module, and is used to receive and parse the configuration instructions sent by the embedded module, parse the configuration instructions, obtain superframe parameters including burst data length and payload waveform, and configure register space through timing control, wherein the register space is divided into a common register and a superframe register, the common register configures common data, and the superframe register configures superframe parameters; Timing control unit, used to generate configuration enable signal I config (t), superframe enable signal I frame (t), data storage timing control signal h(t), configure enable signal I config (t) is sent to the embedded module, and the superframe enable signal I is set when the read / write flag signal F of the data storage module is 1. frame (t) is sent to the data processing module. When the read / write flag signal F of the data storage module is 0 and the working state flag tready of the data processing module is 1, the data storage timing control signal h(t) is sent to the data storage module. tready=1 indicates that the back end of the data processing module is in the read state. Where M represents the superframe update time interval, S represents the time in which the superframe configuration time is ahead of the superframe time, and N sym Indicates the number of symbols read from the data storage module, S sym represents the symbol rate, δ(t) represents the unit pulse sequence, and T[] represents the periodic correlation function; The signal reading unit is used to obtain the read / write flag signal F from the data storage module, read the working status flag tready from the data processing module, and send it to the timing control unit.

3. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The data processing module specifically includes: The data moving unit obtains the payload data from the embedded module upon receiving the superframe enable signal; A scrambling unit, used for scrambling the data output by the data moving unit; A forward verification unit, used for forward verification of data output by the scrambling unit; A Turbo coding unit, used for performing Turbo coding on the data output by the forward check unit according to the burst data length in the superframe parameter, and outputting the coded data to the data storage module after coding; Adding a known symbol unit, used to add a preamble, a postamble and pilot data in the corresponding position of the coded data output by the data storage module according to the load waveform data in the superframe parameter; A data mapping unit, used for mapping the data output by the adding known symbol unit to a corresponding point on the constellation diagram according to the load waveform data in the superframe parameters; A symbol modulation unit, configured to modulate the data output from the data mapping unit into symbols according to the load waveform data in the superframe parameters; The matched filter unit filters the symbols output by the symbol modulation unit according to the entire link information.

4. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 3, characterized in that: The matched filtering unit comprises: Memory, cache depth is The symbol output from the receiving symbol modulation unit is used to After the length, all symbols are released to the raised cosine filter, L span represents the cutoff length of the matched filter; The matched filter is connected behind the memory and is used to match the symbols. The time domain impulse response of the matched filter is: Where g(t) is the time domain impulse response, β is the roll-off factor, T is the symbol period, and T L for The length of the cache period.

5. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 2, characterized in that: The data storage module comprises a first memory block and a second memory block, which are used to alternately store the coded data output by the Turbo coding unit.

6. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 5, characterized in that: The first memory block and the second memory block are both stored in burst data units, and an empty and full flag signal empty is set. When the first memory block or the second memory block stores a burst data, the empty and full flag signal empty of the memory block is 0, otherwise it is 1.

7. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 6, characterized in that: The data storage module is provided with a write selector SEL1 and a read selector SEL2, SEL1 defaults to 0, SEL2 defaults to 0, when the empty in the first memory block is 1, SEL1 is switched to 1, SEL2 is switched to 0, so as to write data to the first memory block and read data from the second memory block; when the empty in the second memory block is 1, SEL1 is switched to 0, SEL2 is switched to 1, so as to write data to the second memory block and read data from the first memory block; The data storage module generates a read-write flag signal F according to the empty and full flag signals of the first memory block and the second memory block, and sends it to the configuration control module. When the empty and full flag signal of the first memory block or the second memory block is empty=1, F=1, indicating a write state, otherwise F=0, indicating a read state; when the data storage module receives the data storage timing control signal h(t)=1, data is read from the corresponding memory block.

8. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The transmit channelizer is based on a multiphase filtering structure and adopts a time division multiplexing mechanism, including an IDFT unit, a complex multiplication unit, a channel filtering unit, a symbol conversion unit, an interpolation unit and a storage addition unit connected in sequence, for realizing the integration and spectrum allocation of multi-channel data. The output signal of the transmit channelizer is: Where Y(n) represents the output signal of the transmit channelizer, X i (n) represents the complex data output by the data processing module after the i-th transmission channel is processed, IDFT[] represents the inverse discrete Fourier transform, K represents the number of channels, and h i (n) represents the channel filter, z K-1-i Represents the delay of the i-th transmission channel data.

9. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The data transmission module comprises: An up-conversion unit, used to perform up-conversion processing on the baseband digital signal output from the transmit channelizer, and generate an upper sideband radio frequency signal in combination with a local oscillator signal; The digital-to-analog conversion unit is used to convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link.

10. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The GPS / BD synchronization module uses an adaptive product difference algorithm to perform clock convergence based on the second pulse generated by the GPS / BD receiving module.

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