State switching method and device and electronic equipment

Abstract

The embodiment of the invention provides a state switching method and device and electronic equipment, and the method comprises the steps: generating and maintaining a state switching signal under the condition that a preset state switching condition is satisfied; performing state switching on the target object by adopting the state switching signal; counting the time interval between the current moment and the ending moment of the synchronous alignment signal; the synchronous alignment signal is a signal which is applied to the target object and is earlier than the state switching signal; under the condition that the time interval meets the preset condition, the state switching signal is ended, and state switching of the target object is completed; the preset condition comprises that the time interval is even times of the first clock period. According to the scheme of the embodiment, the output signal after state switching of the target object is synchronized with the synchronous alignment signal, the problem of time sequence chaos is solved, and the circuit performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a state switching method, device and electronic device. Background Art

[0002] In recent years, 5G (5th generation mobile networks) communications have developed rapidly, and the power consumption indicators of the system have become increasingly higher. As an important part of the RF transceiver system, the power consumption of the high-speed and high-precision DAC (Digital to analog converter) is very important to the power consumption of the entire system. When the communication system works in TDD (Time Division Duplexing) mode, the transceiver shares a RF frequency, and the uplink and downlink use different time slots for communication. Therefore, in the time slot when the DAC does not send data (called sleep mode), some circuits can be turned off to reduce power consumption. Summary of the invention

[0003] Embodiments of the present disclosure provide a state switching method, device, and electronic device.

[0004] In a first aspect, an embodiment of the present disclosure provides a state switching method, the method comprising:

[0005] When a preset state switching condition is met, generating and maintaining a state switching signal;

[0006] Using the state switching signal to switch the state of the target object;

[0007] Counting the time interval between the current moment and the end moment of the synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal;

[0008] When the time interval meets a preset condition, the state switching signal is terminated to complete the state switching of the target object; the preset condition includes: the time interval is an even multiple of the first clock cycle.

[0009] In a second aspect, an embodiment of the present disclosure provides a state switching device, including: a state switching unit; the state switching unit is configured to implement the state switching method.

[0010] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising the state switching device.

[0011] When applying a state switching signal to a target object, the state switching method of the disclosed embodiment makes the time interval between the end moment of the state switching signal and the end moment of the synchronization alignment signal an even multiple of the first clock cycle of the target object output signal, so that after the target object performs state switching, the target object output signal is synchronized with the synchronization alignment signal, thereby solving the problem of output signal phase change and timing confusion caused by directly switching the state of the target object in the current solution, thereby improving circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the accompanying drawings of the embodiments of the present disclosure:

[0013] Figure 1 It is a block diagram of a digital-to-analog converter in the related art;

[0014] Figure 2 A clock path block diagram in the related art;

[0015] Figure 3 A flow chart of a state switching method provided by an embodiment of the present disclosure;

[0016] Figure 4 A schematic diagram of the structure of a four-phase two-frequency divider provided in an embodiment of the present disclosure;

[0017] Figure 5 The embodiments of the present disclosure provide Figure 4 The timing diagram of the divider is shown;

[0018] Figure 6 A block diagram of the state switching device provided in the embodiment of the present disclosure;

[0019] Figure 7 The target object provided for the embodiment of the present disclosure is a frequency divider, and a state switching device is a state switching device connection diagram for synchronizing multiple frequency division signals;

[0020] Figure 8 The target object provided for the embodiment of the present disclosure is a frequency divider, and a state switching device is a state switching device connection diagram for synchronization of a frequency division signal;

[0021] Fig. 9 A timing diagram of automatic resetting of a two-frequency divider based on a state switching device in a time division duplex mode provided by an embodiment of the present disclosure;

[0022] Fig.10 A schematic diagram of the connection of a state switching device after adding a synchronous alignment signal generating circuit provided in an embodiment of the present disclosure;

[0023] Fig.11 A block diagram of the electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the communication perception data processing method and computer-readable storage medium provided by the embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0025] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0026] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0027] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0028] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0029] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0031] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0032] Attached Figure 1 It is a system block diagram of DAC (Digital to analog converter), including data path, clock path and DAC core circuit; Data path includes interface circuit, digital data path, decoder, serializer and switch driver, clock path includes clock and synchronization signal receiver, divider and some clock drivers, and DAC core includes multiple DAC core slices. In the clock path, the CLK (clock signal) transmitted from PLL (Phase Locked Loop) is driven and transmitted to the divider, and the divided clock is transmitted to the decoder (X1 division), serializer (X2 division) and switch driver (X3 division). In TDD mode, if the clock path is turned off, the power consumption of the clock path itself and its application circuit can be greatly reduced.

[0033] Attached Figure 2This is a traditional clock path block diagram. The PLL (Phase Locked Loops) sends a reference synchronization signal and a clock signal. After the clock and synchronization signal receiver Clock & Sync Receiver, the initial synchronization pulse generator module Initial Sync Pulse Gen generates a reset pulse signal reset pulse to reset the divider Divider to ensure that the clock phases in different frequency domains are in a certain relationship. Therefore, the data and sampling clock phase relationship of the decoder Decoder, serializer Serializer and switch driver Switch Driver is fixed. The problem with the traditional clock path is that when the system works in TDD mode, when the transmitter switches from the sleep time slot to the normal working time slot, the clock of the divider Divider also switches from off to restored, but the start time of the transmitter switching to the normal working time slot is uncertain, resulting in a change in the phase of the divided clock, making the data and clock phase relationship of the decoder Decoder, serializer Serializer and switch driver Switch Driver uncertain, causing timing problems and deteriorating DAC performance.

[0034] When a state switching signal (for example, a first reset signal for waking up the divider) is applied to a target object (for example, a divider Divider) in the state switching method of the disclosed embodiment, the time interval between the end moment of the state switching signal and the end moment of the synchronization alignment signal (for example, a reset pulse signal reset pulse) is made an even multiple of the first clock cycle (for example, a two-division clock cycle, a four-division clock cycle, a six-division clock cycle, etc.) of the target object output signal. This allows the phase of the target object output signal to be aligned with the phase of the synchronization alignment signal after the target object is switched in state, thereby solving the problem of timing confusion caused by the current scheme that the output signal phase changes after the target object is directly switched in state, thereby improving circuit performance (for example, while effectively reducing the DAC power consumption in the TDD mode, it can ensure that no phase offset occurs).

[0035] The state switching method of the embodiment of the present disclosure can be executed by any electronic device such as a terminal device or a server that needs to achieve signal synchronization (i.e., phase alignment) after the state switching. The terminal device may include but is not limited to: vehicle-mounted equipment, user equipment (UE), mobile equipment, computing equipment, wearable devices, etc., for example, including but not limited to cellular phones, cordless phones, personal digital assistants (PDA), portable computers, etc. The state switching method can be implemented by a processor calling a computer-readable program instruction stored in a memory, or it can be implemented by a server.

[0036] The embodiments of the present disclosure may be applicable to, but not limited to, a multi-clock domain low-power circuit system.

[0037] The following is a detailed introduction to the embodiments of the present disclosure.

[0038] The disclosed embodiment overcomes the problem in the related art that the phase of the frequency division clock is uncertain in the time division duplex mode, and the frequency division clock cannot be turned off to further reduce power consumption, and provides a method of automatically sending a reset signal to the clock frequency division circuit for reset in the TDD mode to ensure that the frequency division clocks of different working time slots will not have phase shift in the TDD mode. The invention mainly includes the following invention points: In order to solve the contradiction between the uncertainty of the start time of the normal working time slot in the TDD mode and the certainty of the phase of the frequency division clock required after clock recovery, it is necessary to save the phase information of the reset signal when the DAC is initialized. The present invention resets the frequency division circuit by using the reset signal at the time of initialization, so that the reset signal is saved in the phase of the output clock of the frequency divider; then the frequency division clock of a specific phase is used to sample the start signal of the working time slot of the transmitter to obtain a time slot start signal of a determined phase, and finally the signal is used to generate a reset signal, and the reset signal transmission path is multiplexed to reset the frequency division circuit to obtain a frequency division clock with the same phase as when the DAC is initialized. Through the above method, when the system works in TDD mode, the divided clock can be turned off in the time slot when the receiver works. After switching to the time slot when the transmitter works, the reset signal is automatically sent to the divider, so that the clock and data phase relationship of the switch driver, serializer and decoder does not change, while effectively reducing the DAC power consumption in TDD mode and ensuring that no phase shift problem occurs.

[0039] The present disclosure provides a state switching method, such as Figure 3 As shown, the method may include steps S11-S14:

[0040] S11, generating and maintaining a state switching signal when a preset state switching condition is met;

[0041] S12, using a state switching signal to switch the state of the target object;

[0042] S13, counting the time interval between the current moment and the end moment of the synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal;

[0043] S14. When the time interval meets the preset conditions, terminate the state switching signal and complete the state switching of the target object; the preset conditions include: the time interval is an even multiple of the first clock cycle, and the first clock cycle is the clock cycle of the target object output signal.

[0044] In the embodiment of the present disclosure, the output signal of the target object may be a frequency-divided signal of a reference clock synchronization signal.

[0045] In the embodiments of the present disclosure, the above-mentioned state switching may include but is not limited to resetting the circuit and / or device, changing the circuit and / or device from sleep mode to working mode (i.e., waking up the circuit and / or device in sleep mode), etc. In different application scenarios, the state switching operation may be different, and the detailed operation of the state switching is not limited here.

[0046] In the embodiment of the present disclosure, the state switching condition may include but is not limited to: receiving state switching indication information of the target object, and / or reaching a preset state switching period.

[0047] In the embodiments of the present disclosure, the state switching condition may be a certain indication information received, for example, the state switching indication information sent by the control system for switching the state of the target object is received; it may also be the clock information set for automatic state switching, for example, the set state switching cycle, which automatically generates and maintains the state switching signal when the state switching cycle is reached.

[0048] In the embodiments of the present disclosure, in different application scenarios, the state switching condition, the state switching indication information, the state switching cycle, etc. may be different, and the detailed conditions are not limited here. For example, in the scenario of automatically waking up the frequency divider from the sleep mode in the TDD mode of the DAC, the state switching indication information may include: the wake-up indication information of the target object (such as the frequency divider); the state switching cycle may include: the sleep mode wake-up cycle.

[0049] In the embodiment of the present disclosure, the synchronization alignment signal can be a synchronization signal implemented on the target object at any time for phase alignment of the target object. For example, it can include but is not limited to a synchronization signal when the target object is first powered on (i.e., initialized), or a synchronization signal implemented on the target object according to any preset synchronization period.

[0050] In the embodiment of the present disclosure, the target object may be any electronic device that requires signal synchronization (ie, phase alignment), for example, including but not limited to: a frequency divider.

[0051] In the embodiment of the present disclosure, the first clock cycle is the clock cycle of the target object output signal. When the target object is a divider, the target object output signal is a divided signal of the reference clock synchronization signal. The first clock cycle may include but is not limited to a two-divided clock cycle, a four-divided clock cycle, a six-divided clock cycle, ... The first clock cycle can be the clock cycle of any divided signal.

[0052] In the embodiments of the present disclosure, the target object, the state switching signal, the synchronization alignment signal, etc. can be used as different signals according to different application scenarios, and the detailed signals are not limited here. For example, in the scenario of automatically waking up the frequency divider from the sleep mode in the TDD mode of the DAC, the target object includes the frequency divider, the state switching signal may include: a first reset signal for waking up the frequency divider; the synchronization alignment signal may include: a second reset signal for performing phase alignment on the frequency division signal output by the frequency divider.

[0053] In the embodiment of the present disclosure, the embodiment of the present disclosure is introduced below by taking the target object as a frequency divider Divider, and the first clock cycle of the output signal of the frequency divider Divider as a two-frequency clock cycle as an example.

[0054] In the embodiments of the present disclosure, Figure 4 As shown in FIG. 1 , it is a schematic diagram of the structure of a four-phase two-frequency divider; wherein the four-phase two-frequency divider Divider includes four high-level triggered latches (for example, latch1, latch2, latch3 and latch4) and two inverters (for example, F1 and F2), as shown in FIG. Figure 5 As shown, Figure 4 The following is based on the timing diagram of the divider. Figure 4 and Figure 5 The problems raised by the embodiments of the present disclosure are analyzed.

[0055] In the disclosed embodiment, it is assumed that the frequency divider Divider is in a state of being awakened from the sleep mode by a reset signal. At this time, a reset signal reset_0 (high level) is applied to the frequency divider Divider, and the corresponding latches 1, latch 2, latch 3 and latch 4 can be marked as reset1, reset2, reset3 and reset4 respectively. The reset signal reset1 of latch1 and the reset signal reset2 of latch2 are both high levels. At this time, when latch1 and latch2 are reset by the reset signals reset1 and reset2 (for example, when awakened from the sleep mode), the output signals of latch1 and latch2 are also reset to high levels respectively, that is, the output signal clk_div1_0 of latch1 and the output signal clk_div2_0 of latch2 are both high levels. The reset signal reset3 of latch3 and the reset signal reset4 of latch4 are both low level. When latch3 and latch4 are reset by the reset signals reset3 and reset4, the output signals of latch3 and latch4 are also reset to low level respectively, that is, the output signal clk_div3_0 of latch3 and the output signal clk_div4_0 of latch4 are both low level.

[0056] In the embodiments of the present disclosure, Figure 5As shown, during the existence of the reset signal reset_0, the outputs of each latch (latch1, latch2, latch3 and latch4) are reset to the above-mentioned level values ​​(clk_div1_0 and clk_div2_0 are high levels, clk_div3_0 and clk_div4_0 are low levels). At the moment a when the reset signal reset_0 ends, latch1 and latch3 are just in the high level period of the clock signal clk (as shown in the period t1). Based on the principle of the latch, when latch1 and latch3 input the high level clock signal clk, the input ports D1 and D2 of latch1 and latch3 will sample the output ports Q4 and Q2 of the connected latches latch4 and latch2 respectively, and the output ports Q1 and Q3 of latch1 and latch3 will output the sampling results. At this time, based on the reset signal reset4 being at a low level, the output signal clk_div4_0 of latch4 is at a low level, that is, clk_div4_0=0, and the sampling value D1 obtained by latch1 sampling Q4 is 0, which makes the output signal clk_div1_0 of Q1=0; similarly, based on the reset signal reset2 being at a high level, the output signal clk_div2_0 of latch2 is at a high level, that is, clk_div2_0=1, and the sampling value D3 obtained by latch3 sampling Q2 is 1, which makes the output signal clk_div3_0 of Q3=1. Since the clock signals clk of latch2 and latch4 are in antiphase with the clock signals clk of latch1 and latch3, based on the principle of latch, the clock signals clk of latch2 and latch4 are low level, then latch2 and latch4 are in latched state, then latch2 and latch4 latch the last output signal (that is, the level value of reset signals reset2 and reset4), that is, clk_div2_0=1, clk_div4_0=0), the output level value remains the same as the level value of reset signals reset2 and reset4, so after the reset signal reset_0 (high level) ends, the output signal level values ​​of clk_div1_0 and clk_div3_0 are flipped to low level (clk_div1_0=0) and high level (clk_div3_0=1), respectively, as shown in FIG. Figure 5 The corresponding timing of clk_div1_0 and clk_div3_0 in the t1 segment is shown as follows.

[0057] In the embodiment of the present disclosure, the clock signal clk then enters a low level (as shown in time period t2). Due to the presence of inverters F1 and F2, latch2 and latch4 input a high level clock signal clk at this time. Based on the principle of the latch, the input ports D2 and D4 of latch2 and latch4 will respectively sample the output ports Q1 and Q3 of the connected latches latch1 and latch3, and the output ports Q2 and Q4 of latch2 and latch4 will output the sampling results. It is known that based on the principle of latches, latch1 and latch3 input the low-level clock signal clk at this time and are in the latched state, then latch1 and latch3 latch the last output signal, that is, Q1=clk_div1_0=0, Q3=clk_div3_0=1, then the input port D2 of latch2 samples D2=Q1=clk_div1_0=0, the input port D4 of latch4 samples D4=Q3=clk_div3_0=1, then the output ports Q2 and Q4 of latch2 and latch4 output the sampling results Q2=D2=Q1=clk_div1_0=0, Q4=D4=Q3=clk_div3_0=1 respectively. Therefore, the output level values ​​of latch2 and latch4 are also reversed. So far, the output level values ​​of all latches (latch1, latch2, latch3 and latch4) are reversed, and through Figure 5 It can be seen that the first clock cycle of the output signal of each latch is twice the clock signal clk, and the output signal of each latch is inverted in phase with the output signal of the previous latch, realizing the function of four-phase two-division.

[0058] In the embodiment of the present disclosure, based on the above analysis, it can be assumed that the following two reset signals are input to the divider Divider (assuming that both are high level, but with different phases): the falling edge of the input clock signal clk of the divider Divider is used as the boundary (such as Figure 5 The reset signal can be divided into two phases. The period on the left side of the dotted line b and not exceeding the next falling edge can be used as the reset signal phase zero (Reset phase0), and the period on the right side of the dotted line and not exceeding the next falling edge can be used as the reset signal phase one (Reset phase1). The reset signal phase zero (Reset phase0) has ended during the high level of the clock signal clk, and the level values ​​of the output signals of latches latch1 (clk_div1_0) and latch3 (clk_div3_0) have both flipped (corresponding to the attached Figure 5As shown in the middle curve ①, as shown in the period t1), latch1 (clk_div1_0) flips from the high level given by the initial reset signal to the low level, that is, clk_div1_0=0, latch3 (clk_div3_0) flips from the low level given by the initial reset signal to the high level, that is, clk_div3_0=1, and latch2 and latch4 both output the reset level value. Here, only the output signal of latch latch1 is taken as an example for comparison, and the output clk_div1_0=0 of latch1 is recorded when the reset signal phase zero (Reset phase0) is applied to the divider Divider.

[0059] In the embodiment of the present disclosure, when the reset signal phase 1 (Reset phase 1) is applied to the divider Divider, the reset signal phase 1 (Reset phase 1) starts from the low level of the clock signal clk and continues until the high level ends (i.e., at position c), latch1 and latch3 will also flip at the high level of the clock signal clk (corresponding to the attached Figure 5 That is, during the reset phase 1, the clock signal clk reaches a high level, latch 1 also collects the output result of latch 4, and the output result of latch 4 is the level of the reset signal reset 4 (low level), so the output of latch 1 is also clk_div1_1=0 (corresponding to the attached Figure 5 (shown as the middle curve ②).

[0060] In the embodiment of the present disclosure, since the reset signal phase zero (Reset phase0) has been applied in time period A, it can be known from region d that, according to the applied reset signal phase zero (Reset phase0), the output signal of latch latch1 should be high level, that is, clk_div1_0=1, but after the reset signal phase one (Resetphase1) is applied again in time period B, the output signal of latch1 is low level, that is, clk_div1_1=0. Therefore, for latch1, the output clk_div1_0 when the reset signal phase zero (Reset phase0) is applied is exactly opposite to the output clk_div1_1 when the reset signal phase one (Resetphase1) is applied, which will inevitably cause circuit timing confusion. Since the reset signal phase zero (Reset phase0) and the reset signal phase one (Reset Phase 1) There is one falling edge between the two reset end positions, for example, falling edge b, that is, there is an odd number of falling edges. It can be concluded that if there is an odd number of falling edges between the end positions of two adjacent reset signals, the output signal of the same latch will have opposite phases. Since for a divide-by-two frequency divider, a falling edge of the clock signal clk represents a divide-by-two clock cycle, therefore, if the time interval between the end moments of two adjacent reset signals is an odd number of divide-by-two clock cycles, the output signal phase of the divide-by-two frequency divider will be reversed. Conversely, if the time interval between the end moments of two adjacent reset signals is an even number of divide-by-two clock cycles, the output signal phases of the divide-by-two frequency divider will be the same.

[0061] In the disclosed embodiment, it can be seen from the above that in order to ensure that the clock cycle phase of the output signal of the two-frequency divider that is reset multiple times is the same, it is necessary to ensure that the time interval between the end moments of any two adjacent reset signals is 2*k*T, where k is a positive integer and T is the clock cycle of the two-frequency divider. This scheme can be applied to the scenario when any two-frequency divider applies multiple reset signals, and can be extended to the scenario when any four-frequency divider, six-frequency divider, eight-frequency divider, etc., applies multiple reset signals. The difference is that for different frequency division signals, the time interval between the end moments of any two adjacent reset signals is different in 2*k*T. If it is four-frequency division, T is the clock cycle of the four-frequency division signal; if it is six-frequency division, T is the clock cycle of the six-frequency division signal; by analogy, it can be known that T is the clock cycle of the frequency division signal output by the frequency divider, that is, the aforementioned first clock cycle, that is, the time interval between the end moments of any two adjacent reset signals is an even multiple of the first clock cycle.

[0062] In the embodiment of the present disclosure, when there is one target object and the target object generates one output signal, the even multiple is any even multiple of the first clock cycle;

[0063] When there are one or more target objects, the number of output signals generated by the target objects is m, and there are n first clock cycles, the even multiple is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the division of the least common multiple of the n corresponding frequency division numbers of the first clock cycles; m and n are positive integers greater than 1, and m is greater than or equal to n.

[0064] In the disclosed embodiment, the target object is still taken as a frequency divider for explanation. If there is only one frequency divider to be reset, and the frequency divider only generates one frequency division signal, for example, only generates a frequency division signal of four, then when two adjacent reset signals reset the frequency divider, in order to ensure that the phase of the frequency division signal output by the frequency divider remains unchanged, it is necessary to satisfy that the time interval between the end times of the two reset signals is any even multiple of the clock period of the four-frequency division signal, for example, 2 times, 4 times, 6 times, etc.

[0065] In the disclosed embodiment, if there is one frequency divider to be reset, and the frequency divider generates multiple frequency division signals, for example, frequency division signals of four and six, then when two adjacent reset signals reset the frequency divider, in order to ensure that the phase of each frequency division signal output by the frequency divider remains unchanged, it is necessary to satisfy that the time interval between the end times of the two reset signals is an even multiple of the clock period of the four-division signal and an even multiple of the clock period of the six-division signal. In order to meet this condition, the time interval is set to any even multiple of the clock period of the frequency division signal (i.e., the twelve-division signal) which is the least common multiple of the four-division signal and the six-division signal.

[0066] In the disclosed embodiment, if there are multiple frequency dividers to be reset, and each frequency divider generates a frequency division signal, when a reset signal is used to reset multiple frequency dividers, it is also necessary to set the time interval between the end moments of two adjacent reset signals to any even multiple of the clock cycle corresponding to the frequency division signal of the least common multiple of the multiple frequency division signals. For example, if two frequency dividers generate frequency division signals of four and eight, respectively, the time interval is set to any even multiple of the clock cycle of the frequency division signal of the least common multiple of the four-frequency division signal and the eight-frequency division signal (i.e., the eight-frequency division signal).

[0067] In the embodiments of the present disclosure, through the above-mentioned embodiment scheme, the embodiment scheme of the present disclosure can be applied to various scenarios, thereby expanding the application scope of the scheme.

[0068] In the embodiment of the present disclosure, before counting the time interval between the current moment and the end moment of the synchronization alignment signal applied to the target object, the method may further include:

[0069] receiving a synchronization alignment signal;

[0070] Starting from the end time of the synchronization alignment signal, the synchronization phase signal is continuously generated;

[0071] The clock cycle of the synchronous phase signal is used to calculate the time interval; the clock cycle of the synchronous phase signal is the first clock cycle or the second clock cycle; and the time interval is an even multiple of the clock cycle of the synchronous phase signal.

[0072] In the disclosed embodiment, the state switching signal can be regarded as reset signal 1, and the synchronization alignment signal can be regarded as reset signal 2. Since the synchronization alignment signal is a standard synchronization signal, it is used to phase-align the output signal of the target object. In order to ensure that the output signal of the target object is still phase-aligned during any subsequent state switching of the target object (for example, waking up the target object), the synchronization alignment signal (i.e., reset signal 2) can be saved, especially the end time of the reset signal 2. For example, the timing can be started at the end time of the reset signal 2. The clock period used for the timing can be the same as the clock period of the output signal of the target object, that is, the same as the first clock period. For example, if the target object outputs a two-frequency division signal, the clock period for timing is also the clock period of the two-frequency division signal. If the target object outputs a six-frequency division signal, the clock period for timing is also the clock period of the six-frequency division signal. Similarly, if the signal output by the target object is a plurality of frequency-divided signals, for example, including a divided-by-two signal, a divided-by-six signal, and a divided-by-eight signal, the clock period for timing is the clock period of the frequency-divided signal whose frequency division numbers are the least common multiple of the divided-by-two signal, the divided-by-six signal, and the divided-by-eight signal (the least common multiple of 2, 6, and 8 is 24), that is, the clock period of the 24-divided-by-two signal (the second clock period).

[0073] In the disclosed embodiment, the above timing can be realized by a frequency divider, that is, after receiving the synchronization alignment signal, the frequency divider starts working from the end time of the synchronization alignment signal and continuously generates a frequency division signal (for example, the above-mentioned 24-division frequency division signal) as a synchronization phase signal.

[0074] In the embodiment of the present disclosure, when determining the time interval based on the synchronization phase signal, since the clock period of the synchronization phase signal is the first clock period or the second clock period, the time interval can be directly determined as an even multiple of the clock period of the synchronization phase signal, that is, it is calculated whether the time interval between the current moment and the end moment of the synchronization alignment signal is an even multiple of the clock period of the synchronization phase signal.

[0075] In the embodiment of the present disclosure, based on the above embodiment scheme, by generating a synchronous phase signal and determining the time interval according to the clock cycle of the synchronous phase signal, the accuracy of the end time of the reset signal 1 is guaranteed.

[0076] The present disclosure also provides a state switching device 100, such as Figure 6 As shown, it may include: a state switching unit 101; the state switching unit 101 is configured to implement the state switching method.

[0077] In the embodiment of the present disclosure, the state switching unit 101 may include: a synchronous phase preservation circuit 1011 and a state switching signal generating circuit 1012;

[0078] The state switching signal generating circuit 1012 is configured to generate and maintain the state switching signal when a preset state switching condition is met;

[0079] The state switching signal generating circuit 1012 is further configured to use the state switching signal to switch the state of the target object 200;

[0080] The synchronous phase preservation circuit 1011 counts the time interval between the current moment and the end moment of the synchronous alignment signal; the synchronous alignment signal is a signal applied to the target object earlier than the state switching signal;

[0081] The state switching signal generating circuit 1012 is also configured to end the state switching signal and complete the state switching of the target object 200 when the time interval meets the preset conditions; the preset conditions may include but are not limited to: the time interval is an even multiple of the first clock cycle, and the first clock cycle is the clock cycle of the output signal of the target object 200.

[0082] In the disclosed embodiment, the signal output terminal of the synchronization phase preservation circuit 1011 is connected to the first signal input terminal of the state switching signal generating circuit 1012;

[0083] The signal output terminal of the state switching signal generating circuit 1012 is connected to the signal input terminal of the target object 200 .

[0084] In the embodiments of the present disclosure, Figure 7As shown, the target object 200 may include but is not limited to a frequency divider Divider. For example, the frequency divider Divider may generate X1 frequency division for the decoder Decoder, X2 frequency division for the serializer Serializer and X3 frequency division for the switch driver Switch Driver. The frequency divider Divider may include a first frequency divider corresponding to the decoder Decoder (for generating X1 frequency division), a second frequency divider corresponding to the serializer Serializer (for generating X2 frequency division), and a third frequency divider corresponding to the switch driver Switch Driver (for generating X3 frequency division); or, the frequency divider Divider may generate multiple frequency divisions: X1 frequency division, X2 frequency division, X3 frequency division, etc. The frequency divider is connected to a state switching unit 101, and multiple frequency division signals (X1 frequency division, X2 frequency division, X3 frequency division) may be synchronized through the state switching unit 101.

[0085] In the embodiments of the present disclosure, Figure 8 As shown, the frequency divider Divider as the target object 200 may also be a frequency divider that generates only one frequency division signal, for example, it may be only the first frequency divider Divider-1 mentioned above, the first frequency divider Divider-1 is connected to a first state switching unit 101-1, and the frequency division signal (X1 division) of the first frequency divider Divider-1 is synchronized through the first state switching unit 101-1; it may also be only the second frequency divider Divider-2 mentioned above, the second frequency divider Divider-2 ider-2 is connected to a second state switching unit 101-2, and the frequency division signal (X2 division) of the second frequency divider Divider-2 is synchronized through the second state switching unit 101-2; it can also be only the third frequency divider Divider-3 mentioned above, and the third frequency divider Divider-3 is connected to a third state switching unit 101-3, and the frequency division signal (X3 division) of the third frequency divider Divider-3 is synchronized through the third state switching unit 101-3. Among them, the state switching unit 101 includes the first state switching unit 101-1, the second state switching unit 101-2, and the third state switching unit 101-3 mentioned above. The first state switching unit 101-1, the second state switching unit 101-2, and the third state switching unit 101-3 all include: a synchronization phase preservation circuit 1011 and a state switching signal generating circuit 1012.

[0086] In the embodiment of the present disclosure, the synchronous phase preservation circuit 1011 is in a continuous working state. When the target object 200 needs to switch states, the state switching signal generating circuit 1012 can generate a state switching signal (which can be regarded as a first reset signal, such as the aforementioned reset signal 1), apply the state switching signal to the target object 200, and obtain the time interval calculated by the synchronous phase preservation circuit 1011 based on the clock cycle of the synchronous phase preservation circuit 1011 itself. The time interval may refer to the duration between the end time of the synchronous alignment signal applied to the target object 200 when the signal phase was last aligned for the target object 200 and the end time of the state switching signal. The time interval needs to satisfy the following requirements: it must be an even multiple of the first clock cycle of the output signal of the target object 200 to ensure that the phase of the output signal of the target object 200 remains unchanged after the state switching, that is, to maintain synchronization. In order to enable the target object 200 to achieve signal synchronization after state switching (for example, waking up the target object 200 so that the target object 200 switches from sleep mode to working mode, for example, waking up through a wake-up signal Sleepstop signal), the time interval is counted, and the state switching signal is terminated when the time interval is an even multiple of the first clock cycle, thereby completing the state switching of the target object 200.

[0087] In the embodiment of the present disclosure, when the state switching condition includes the state switching indication information of the target object, the state switching signal generating circuit 1012 further includes: a second signal input terminal;

[0088] The second signal input terminal is configured to be an input terminal for state switching indication information.

[0089] In the embodiment of the present disclosure, the target object 200 can switch states through external state switching indication information (wake-up signal Sleepstop signal), and the state switching signal generating circuit 1012 receives the state switching indication information through the second signal input terminal and generates a state switching signal according to the state switching indication information.

[0090] In the embodiment of the present disclosure, the target object 200 can also switch states according to a preset state switching cycle. The state switching signal generating circuit 1012 receives the output signal of the synchronous phase preservation circuit 1011 through the first signal input terminal, counts the duration according to the clock cycle of the output signal, and generates a state switching signal when the counted duration reaches the state switching cycle.

[0091] In the embodiment of the present disclosure, after the state switching signal is generated and applied to the target object 200, the time interval can be counted, and when the time interval is an even multiple of the first clock cycle, the state switching signal is terminated to complete the state switching of the target object 200.

[0092] In the embodiment of the present disclosure, after the state of the target object 200 is switched, Figure 7 and Figure 8 The phases of the output signals of the decoder, serializer, switch driver and synchronous phase preservation circuit 1011 (equivalent to a frequency divider) are all synchronized.

[0093] In the embodiments of the present disclosure, Fig. 9 As shown, the embodiment of the present disclosure is still described by taking the automatic reset of the frequency divider of the two-frequency divider in the time division duplex mode (converting from the sleep mode to the working mode) as an example. At this time, the synchronous phase preservation circuit 1011 also uses the two-frequency divider. Fig. 9 The middle curve ③ indicates that after the synchronization alignment signal (also called reset signal, which is used for synchronization alignment, such as the reset signal dac sync pulse, which can be simply represented as reset-1) synchronizes the target object 200 (two-frequency division circuit), the output clock of the target object 200 begins to synchronize. At this time, the synchronization phase storage circuit 1011 receives the synchronization alignment signal and starts to work, continuously generating a state switching signal (such as Fig. 9 As shown in the signal syncphase saved in the figure, it is also a two-frequency divided signal), wherein the two-frequency divided inverted output clock (inverted div2 clk) corresponding to the state switching signal can be stored, such as Fig. 9 The middle curve ④ indicates that the falling edge of the synchronization alignment signal is stored at the rising edge of the two-frequency division inverted output clock (inverted div2 clk) after the synchronization alignment (that is, the state switching signal generated by the synchronization phase storage circuit 1011 can be aligned with the synchronization alignment signal according to the rising edge of the two-frequency division inverted output clock inverted div2 clk, and the clock cycle of the two-frequency division signal is officially started, and the two-frequency division signal is continuously generated). Fig. 9 As shown in the middle curve ⑤, the rising edge of the divided-by-two inverted output clock (inverted div2 clk) and the falling edge of the state switching signal (which can be regarded as another reset signal here, as shown in the reset signal auto reset) are separated by 2*k*T, where k is a positive integer and T is the divided-by-two clock period of the divider.

[0094] In the embodiment of the present disclosure, in the state switching signal generating circuit 1012 (also referred to as the Sync Pulse Auto Gen circuit), the rising edge of the wake-up signal (Sleepstop Signal) of the sleep mode (the end of the transmitter sleep mode) is sampled using a two-frequency inverted output clock (inverted div2 clk), and a state switching signal (also referred to as a reset signal, such as reset-2 in the automatic reset signal auto reset) is obtained with an interval of 2*k*T with the falling edge of the synchronization alignment signal (reset-1), as shown in the attached Fig. 9 As shown in the middle curve ⑥, as long as there is a rising edge of the state switching prompt signal (e.g., the wake-up signal sleepstop signal), a state switching signal (reset-2) is automatically generated. The end time of the state switching signal (reset-2), or the falling edge, is 2*k*T away from the synchronization alignment signal (reset-1), so that the two-frequency division clock (div2 clk with sleep mode) that automatically resets after sleep achieves signal synchronization after state switching (e.g., reset) according to the state switching signal (reset-2). Among them, the dotted line d in the wake-up signal sleepstopsignal means that after the wake-up signal sleepstop signal is detected (e.g., the rising edge of the wake-up signal sleepstop signal is detected), the state switching signal (reset-2) may not be generated immediately, and the state switching signal (reset-2) may be generated within a preset period after the rising edge of the wake-up signal sleepstop signal is detected.

[0095] In the embodiment of the present disclosure, by attaching Fig. 9 It can be seen that the phase of the divided-by-two clock (div2 clkwith sleep mode) that is automatically reset after sleep mode is the same as that of the divided-by-two clock (div2 clk without sleep mode) that has not entered the sleep mode. Therefore, by saving the phase of the synchronization alignment signal (for example, saving the falling edge of the synchronization alignment signal at the end time), and automatically resetting the divider according to the time interval that meets the preset conditions after the sleep mode ends, the purpose of turning off the clock division circuit in TDD mode to reduce power consumption and ensuring that the phase relationship of the clocks in each clock domain does not change is achieved.

[0096] In the embodiments of the present disclosure, Fig.10 As shown, the state switching device 100 may further include: a synchronization alignment signal generating circuit 102;

[0097] The signal input terminal of the synchronization alignment signal generating circuit 102 is a reference clock synchronization signal input terminal; the first clock cycle may be obtained by dividing the clock cycle of the reference clock synchronization signal;

[0098] The signal output terminal of the synchronization alignment signal generating circuit 102 is connected to the signal input terminal of the target object 200 and / or to the signal input terminal of the synchronization phase preservation circuit 1011;

[0099] The synchronization alignment signal generating circuit 102 is configured to generate a synchronization alignment signal.

[0100] In the embodiment of the present disclosure, the synchronization alignment signal generating circuit 102 can be used as a clock and synchronization signal receiver (Clock & Sync Receiver) to receive the clock and synchronization signal from the PLL (Phase Locked Loop), such as Fig. 9 The clock signal clk to dac and the synchronization signal sync to dac shown in FIG. The clock signal clk to dac and the synchronization signal sync to dac can be transmitted to the synchronization alignment signal generating circuit 102 (for example, the synchronization alignment signal generating circuit 102 can be an initialization synchronization pulse generating module Initial Sync Pulse Gen, which is used to generate an initial reset signal during initialization and can be used as a synchronization alignment signal) to generate a reset pulse, such as Fig. 9 The reset signal dac sync pulse shown in the figure, wherein the reset pulse is the signal reset-1 mentioned above, wherein curve ⑦ represents the clock edge that generates the reset pulse.

[0101] In the embodiment of the present disclosure, when the signal output terminal of the synchronization alignment signal generating circuit 102 is connected to the signal input terminal of the target object and the signal input terminal of the synchronization phase preservation circuit 1011:

[0102] The synchronization alignment signal generating circuit 102 is further configured to apply a synchronization alignment signal to the target object 200 to perform phase synchronization on the first clock cycle of the target object 200;

[0103] The synchronous phase preservation circuit 1011 is also configured to receive a synchronous alignment signal, and continuously generate a synchronous phase signal synchronized with the synchronous alignment signal starting from the end time of the synchronous alignment signal; the clock period of the synchronous phase signal is the first clock period or the second clock period; the second clock period is the clock period corresponding to the frequency division of the least common multiple of the frequency division numbers corresponding to n kinds of first clock periods; n is a positive integer greater than 1.

[0104] In the embodiment of the present disclosure, the synchronization alignment signal generating circuit 102 can be connected to the target object 200 only during power-on initialization, perform signal alignment on the target object 200, and be connected to the synchronization phase preservation circuit 1011. When the target object 200 subsequently switches states and needs signal synchronization, signal synchronization can be performed only through the state switching unit 101.

[0105] In the disclosed embodiment, the synchronization alignment signal generating circuit 102 may also be connected only to the synchronization phase preservation circuit 1011. After the synchronization alignment signal is generated at any time to trigger the synchronization phase preservation circuit 1011 to start working, when the state of the target object 200 switches and needs to perform signal synchronization, the output signal of the target object 200 can be synchronized through the state switching unit 101. The signal phase of the synchronization alignment signal is the same as that of the output signal of the target object 200.

[0106] In the embodiments of the present disclosure, Figure 8 As shown, in the case where a state switching unit 101 is connected to a target object 200 and the target object 200 generates an output signal:

[0107] The state switching signal generating circuit 1012 is further configured to terminate the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the first clock cycle.

[0108] In the embodiment of the present disclosure, if there is only one target object 200, for example, there is only one frequency divider, and only one frequency division signal is generated, for example, a two-division signal or a four-division signal, then a state switching unit 101 can be set for the one target object 200, and the clock cycle of the synchronous phase preservation circuit 1011 in the state switching unit 101 is also the clock cycle of the output signal of the target object 200 (i.e., the first clock cycle).

[0109] In the embodiments of the present disclosure, Figure 7 As shown, in the case where a state switching unit 101 is connected to one or more target objects 200, the target object 200 generates m output signals, and the first clock cycle is n:

[0110] The state switching signal generating circuit 1012 is also configured to end the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the division of the least common multiple of the division numbers corresponding to the n first clock cycles; m is a positive integer greater than 1, and m is greater than or equal to n.

[0111] In the embodiment of the present disclosure, if there is only one target object 200 but multiple frequency division signals are generated, or there are multiple target objects 200 (for example, m), and multiple target objects 200 generate multiple different frequency division signals (for example, n types), in the above case, if signal synchronization is performed only through one state switching unit 101, the clock cycle of the synchronization phase preservation circuit 1011 in the state switching unit 101 is required to be the clock cycle (i.e., the second clock cycle) of the frequency division corresponding to the least common multiple of the n types of frequency divisions of the output signal of the target object 200. For example, if the target object 200 outputs four types of frequency division signals, for example, a two-division signal, a four-division signal, a six-division signal, and an eight-division signal, the clock cycle of the synchronization phase preservation circuit 1011 is a 24-division signal (the 24 is the least common multiple of 2, 4, 6, and 8).

[0112] In the embodiment of the present disclosure, the embodiment of the present disclosure can generate a synchronization alignment signal after the system is powered on. When the devices in the system (including the target object 200) are synchronized for the first time, the reset pulse in the synchronization alignment signal resets the frequency divider (target object 200), so that clocks of different frequencies have clear synchronized phase information, and the synchronized phase information is saved at the edge of the divided clock (that is, when the edge of the reset pulse is detected, such as the falling edge, the synchronization phase storage circuit 1011 is started to generate a divided signal with the same clock period as the output signal of the divider); in the time slot when the receiver is working, the transmitter enters the sleep state, and the DAC internal divider and its application circuit are turned off. In the time slot when the transmitter is working normally, the DAC sleep state ends, and the state switching signal generating circuit 1012 is used to sample the divided signal generated by the synchronization phase storage circuit 1011 and regenerate a synchronization pulse (that is, the state switching signal) to reset the divider circuit. The phase of the divider after reset is the same as the phase at the time of initialization, so the clock phase of other clock domains remains unchanged. Through the above process, the time division duplex mode can turn off the frequency divider to reduce power consumption, while ensuring that the phase relationship of the clocks in each clock domain does not change.

[0113] The present disclosure also provides an electronic device 300, such as Fig.11 As shown, it includes the state switching device 100.

[0114] In the embodiment of the present disclosure, the electronic device may include but is not limited to a digital-to-analog converter DAC.

[0115] In the embodiments of the present disclosure, the solutions of the embodiments of the present disclosure can be used in, but not limited to, the TDD mode, and can also be used in other scenarios where circuit state switching requires synchronization.

[0116] The embodiments of the present disclosure may be used in, but not limited to, DAC circuits, and may also be used in other circuits that require synchronization.

[0117] The embodiments of the present disclosure may be used in, but not limited to, frequency division circuits (for example, including but not limited to, frequency division by two circuits, frequency division by four circuits, frequency division by six circuits, etc.), and may also be used in other circuits that require synchronization or resetting of signals.

[0118] The synchronization alignment signal of the embodiment of the present disclosure may include but is not limited to an initialization reset signal, and may be a signal used for phase alignment at any time.

[0119] The method for preserving the phase information of the synchronization alignment signal of the embodiment of the present disclosure may have multiple variations, and may adopt a four-phase two-frequency division circuit, or other signals that retain synchronization phase information. All circuits that require synchronization phase may preserve the synchronization phase information.

[0120] The method for automatically sending synchronization alignment signals of the embodiment of the present disclosure may have many variations, and may be the synchronization alignment signal generating circuit 102, or may be implemented in conjunction with the synchronization alignment signal generating circuit 102, or may be implemented in conjunction with other circuits that send data information with a determined phase or a fixed phase, or may be implemented in conjunction with other external input signals or signals generated within the circuit.

[0121] The circuit for generating an arbitrary divided frequency signal of the embodiment of the present disclosure may have many variations, and may adopt but is not limited to a frequency divider and a shift register, wherein a divided frequency clock is generated by a frequency divider, and then the divided clock is serially sampled using an undivided clock to obtain a multi-phase multi-divided frequency clock; if there is no need for multiple phases, a single trigger output may be directly used, and the embodiment of the present disclosure may be extended to a circuit for generating an arbitrary divided frequency clock of any phase.

[0122] The disclosed embodiment scheme uses a synchronous alignment signal and adopts synchronous timing logic to generate a reset pulse (synchronous alignment pulse) to reset the clocks of different clock domains, and saves the phase information of the synchronous alignment signal through a frequency division circuit (such as a synchronous phase preservation circuit 1011). In the TDD mode, a reset pulse (i.e., a state switching signal) is automatically generated to reset the frequency division clock with uncertain phase, so that the clock phase relationship of each clock domain is determined, and the phase relationship between the data of the serializer and the clock of the switch driver is determined, thereby avoiding the problem of misbeat or metastable state caused by clock phase changes; through the above scheme, the switch drive circuit is turned off and automatically reset.

[0123] Those skilled in the art will appreciate that all or some of the functional modules / units disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0124] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0125] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0126] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A state switching method, characterized in that: The method comprises: When a preset state switching condition is met, generating and maintaining a state switching signal; Using the state switching signal to switch the state of the target object; Counting the time interval between the current moment and the end moment of the synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal; When the time interval meets a preset condition, the state switching signal is terminated to complete the state switching of the target object; the preset condition includes: the time interval is an even multiple of a first clock cycle, and the first clock cycle is the clock cycle of the output signal of the target object.

2. The state switching method according to claim 1, characterized in that: In the case where there is one target object and the target object generates one output signal, the even multiple is any even multiple of the first clock cycle; When there are one or more target objects, the output signals generated by the target objects are m, and there are n first clock cycles, the even multiple is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the division of the least common multiple of the n corresponding frequency division numbers of the first clock cycles; m and n are positive integers greater than 1, and m is greater than or equal to n.

3. The state switching method according to claim 2, characterized in that: Before counting the time interval between the current moment and the end moment of the synchronization alignment signal applied to the target object, the method further includes: receiving the synchronization alignment signal; Starting from the end time of the synchronization alignment signal, continuously generating a synchronization phase signal; The clock cycle of the synchronous phase signal is used to calculate the time interval; the clock cycle of the synchronous phase signal is the first clock cycle or the second clock cycle; and the time interval is an even multiple of the clock cycle of the synchronous phase signal.

4. The state switching method according to any one of claims 1 to 3, characterized in that: The state switching condition includes: receiving state switching indication information of the target object, and / or reaching a preset state switching period.

5. The state switching method according to claim 4, characterized in that: The state switching indication information includes: wake-up indication information of the target object; The state switching cycle includes: a sleep mode wake-up cycle; The state switching signal includes: a first reset signal for waking up the target object; The synchronization alignment signal includes: a second reset signal for performing phase alignment on the frequency-divided signal output by the target object.

6. A state switching device, characterized in that: include: A state switching unit; the state switching unit is configured to implement the state switching method described in any one of claims 1-5.

7. The state switching device according to claim 6, characterized in that: The state switching unit comprises: a synchronous phase storage circuit and a state switching signal generating circuit; The state switching signal generating circuit is configured to generate and maintain the state switching signal when a preset state switching condition is met; The state switching signal generating circuit is further configured to use the state switching signal to switch the state of the target object; The synchronous phase storage circuit counts the time interval between the current moment and the end moment of the synchronous alignment signal; the synchronous alignment signal is a signal applied to the target object earlier than the state switching signal; The state switching signal generating circuit is also configured to end the state switching signal and complete the state switching of the target object when the time interval meets a preset condition; the preset condition includes: the time interval is an even multiple of a first clock cycle, and the first clock cycle is the clock cycle of the output signal of the target object.

8. The state switching device according to claim 7, characterized in that: The signal output terminal of the synchronous phase preservation circuit is connected to the first signal input terminal of the state switching signal generating circuit; The signal output terminal of the state switching signal generating circuit is connected to the signal input terminal of the target object.

9. The state switching device according to claim 8, characterized in that: In the case where the state switching condition includes the state switching indication information of the target object, the state switching signal generating circuit further includes: a second signal input terminal; The second signal input terminal is configured to serve as an input terminal for the state switching indication information.

10. The state switching device according to any one of claims 7 to 9, characterized in that: Also included: a synchronization alignment signal generating circuit; The signal input terminal of the synchronization alignment signal generating circuit is a reference clock synchronization signal input terminal; the first clock period is obtained by dividing the clock period of the reference clock synchronization signal; The signal output terminal of the synchronization alignment signal generating circuit is connected to the signal input terminal of the target object and / or is connected to the signal input terminal of the synchronization phase preservation circuit; The synchronization alignment signal generating circuit is configured to generate the synchronization alignment signal.

11. The state switching device according to claim 10, characterized in that: In the case where the signal output terminal of the synchronization alignment signal generating circuit is connected to the signal input terminal of the target object and the signal input terminal of the synchronization phase preservation circuit: The synchronization alignment signal generating circuit is further configured to apply the synchronization alignment signal to the target object to perform phase synchronization on the first clock cycle of the target object; The synchronous phase preservation circuit is also configured to receive the synchronous alignment signal, and continuously generate a synchronous phase signal synchronized with the synchronous alignment signal starting from the end time of the synchronous alignment signal; the clock period of the synchronous phase signal is the first clock period or the second clock period; the second clock period is the clock period corresponding to the frequency division of the least common multiple of n frequency division numbers corresponding to the first clock period; n is a positive integer greater than 1.

12. The state switching device according to claim 7, characterized in that: When one of the state switching units is connected to a target object and the target object generates an output signal: The state switching signal generating circuit is further configured to terminate the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the first clock cycle.

13. The state switching device according to claim 7, characterized in that: When one state switching unit is connected to one or more target objects, the target object generates m output signals, and the first clock cycles are n: The state switching signal generating circuit is also configured to end the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the division of the least common multiple of the n types of frequency division numbers corresponding to the first clock cycle; m is a positive integer greater than 1, and m is greater than or equal to n.

14. An electronic device, characterized in that: It comprises a state switching device as described in any one of claims 6 to 13.

15. The electronic device according to claim 14, characterized in that: The electronic device includes a digital-to-analog converter.

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