Clock synchronization optimization calculation method for security monitoring system

Abstract

The invention relates to a safety monitoring system clock synchronization optimization calculation method, which belongs to the technical field of mining safety monitoring communication, and comprises the following steps: S1, selecting a main clock, and synchronizing initial time; s2, calculating main clock sending compensation time; s3, calculating substation receiving compensation time and feedback compensation time; s4, the master clock source calculates transmission compensation time; s5, the master clock issues a synchronous clock; s6, the substation synchronizes the clock; and S7, the master clock and the substations check the clocks. According to the invention, the data transmission time consistency and the low data transmission delay of the monitoring system are ensured, and the normal operation of the monitoring system is ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of mine safety monitoring communication and relates to a clock synchronization optimization calculation method for a safety monitoring system. Background Art

[0002] At present, the security monitoring system does not have the clock synchronization function, and the time of the equipment in the system is inconsistent. The clock in the system mainly relies on the substation to actively request the clock from the central station, and then the clock sends the clock to the substation. This mode has the following problems: First, each substation needs to design a separate clock command format, and the command needs to be completed independently. When the substation is busy, the reception of clock data will be delayed, resulting in large errors; second, this mode does not calculate the transmission compensation of data in the network, resulting in increased errors; third, in this mode, the substation equipment does not calculate its own operating losses, which increases the synchronization error; fourth, in this mode, there is no verification mode for the internal clock of the system, and the clock synchronization status is unknown; fifth, the asynchronous system clock may cause communication dislocation and data loss, which may seriously affect the normal operation of the security monitoring system.

[0003] At present, the communication technology for underground signal transmission using leakage cables is mainly reflected in the following types: First, the traditional PTP or gPTP protocol is adopted. This protocol requires the support of hardware TSN chips, which increases the difficulty of designing the monitoring system and the product cost; second, the standard clock protocol requires the calculation of the system master clock and confirms the master clock through complex calculations. When the master clock fails, the master clock must be obtained through complex calculations again, and then the clock is synchronized. This method is very complicated and may lead to large differences between the main clocks before and after, resulting in inconsistencies in the clocks before and after; third, the transmission loss of the standard protocol requires multiple network communications to confirm, and then the transmission loss is calculated. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a clock synchronization optimization calculation method for a security monitoring system.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A clock synchronization optimization calculation method for a security monitoring system comprises the following steps:

[0007] S1: Select the master clock and synchronize the initial time;

[0008] S2: Calculate the master clock sending compensation time;

[0009] S3: Calculate the receiving compensation time and feedback compensation time of the substation;

[0010] S4: The master clock source calculates the transmission compensation time;

[0011] S5: The master clock sends the synchronous clock;

[0012] S6: Substation synchronization clock;

[0013] S7: The master clock and substation calibrate the clock.

[0014] Further, in step S1, a master clock is first selected, and the master clock records the initial time C t0 , and then perform network data packet.

[0015] Further, step S2 specifically includes the following steps:

[0016] The master clock sends a network broadcast data packet to the network device and records the time when the transmission is completed C t1 ;

[0017] Calculate the master clock sending compensation time T g1 , as shown below:

[0018] T g1 =C t1 -C t0 .

[0019] Further, step S3 specifically includes the following steps:

[0020] The substation starts to receive data packets and records the time t2;

[0021] The substation parses the data packet to obtain the initial time of the master clock C t0 , and use this time as the initial clock of the synchronization clock, and record the time t3 when the parsing is completed;

[0022] Calculate the number of bytes of the received data packet n, then the sum of the number of bytes of received data and parsed data is 2n;

[0023] Calculate the receiving compensation time T of the substation e1 :

[0024] T e1 =t3-t2

[0025] Calculate the single byte retention time T of the substation e :

[0026]

[0027] Calculate the number of data bytes m that the substation needs to feed back to the master clock source;

[0028] Calculate the substation feedback compensation time T e2 :

[0029] T e2 =mT e

[0030] The substation feeds back a clock synchronization data packet, which contains the substation receiving compensation time T e1 and feedback compensation time T e2 .

[0031] Further, step S4 specifically includes the following steps:

[0032] The master clock receives the clock synchronization data packet fed back by the substation and records the time when it starts receiving data C t2 ;

[0033] The master clock parses the feedback data packet, obtains the data content of the substation feedback, and records the time C t3 ;

[0034] The master clock calculates the receiving compensation time T g2 :

[0035] T g2 =C t3 -C t2

[0036] Substation calculates transmission compensation time C T :

[0037] C T =(C t3 -T g1 -T e1 -T e2 -T g2 ) / 2.

[0038] Further, step S5 specifically includes the following steps:

[0039] The master clock records the current clock C t3 ;

[0040] The master clock adds the master clock source correction time T to the synchronization clock data packet. g and C T ;

[0041] The master clock sends clock synchronization data packets.

[0042] Further, step S6 specifically includes the following steps:

[0043] The substation receives the clock data packet and parses the data packet;

[0044] Substation calculates synchronization time C t , in C t3 Add T to the clock g , C T and T e1 , the calculation formula is as follows;

[0045] Ct =C t3 +T g +C T +T e1

[0046] Substation clock synchronization is completed.

[0047] Further, step S7 specifically includes the following steps:

[0048] The master clock sends the standard room regularly with information to be confirmed;

[0049] The substation receives the same standard time and compares it with its own time. If there is no difference, the feedback is normal;

[0050] If there is a difference in the clock verification, the master clock will be synchronized again.

[0051] The beneficial effects of the present invention are as follows: the present invention notifies the entire network equipment (substation) to perform clock synchronization by specifying the master clock mode, and achieves precise time synchronization between the network equipment and the master clock equipment through an optimized time compensation algorithm, achieves clock consistency of the entire network equipment, ensures time consistency of data transmission of the monitoring system, and low latency of data transmission, thereby ensuring the normal operation of the monitoring system.

[0052] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0054] Figure 1 Optimizing computational methods for clock synchronization in security surveillance systems. DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and the features in the embodiments can be combined with each other without conflict.

[0056] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0058] The present invention provides a clock synchronization optimization calculation method for a security monitoring system, such as Figure 1 As shown, the following steps are included:

[0059] 1. Synchronize initial time

[0060] Select the master clock, which records the initial time C t0 , network data packets.

[0061] 2. Calculate the master clock compensation time T g

[0062] The master clock sends a network broadcast data packet to the network device and records the time when the transmission is completed C t1 ;

[0063] The difference between the sending completion time and the initial time is the compensation T sent by the master clock g1 , the formula is shown in formula (1).

[0064] T g1 = C t1 - C t0 (1)

[0065] 3. Calculate the substation retention time T e

[0066] The substation starts receiving data packets and records the time t2;

[0067] The substation parses the data packet to obtain the main clock time C t0 , and use this time as the initial clock of the synchronization clock, and record the clock t3 when the data is parsed;

[0068] Calculate the number of bytes of the received data packet. If the number of bytes of the received data packet is n, then the sum of the number of bytes of the received data and the parsed data is 2n;

[0069] Substation receiving compensation time T e1 The calculation formula is shown in formula (2);

[0070] T e1 = t3 - t2 (2)

[0071] The calculation of the single byte retention time of the substation is shown in formula (3);

[0072]

[0073] The substation calculates the number of data bytes m required to feedback the main clock source;

[0074] Substation calculation feedback compensation time T e2 , i.e., the feedback data packet time and data sending time, as shown in formula (4);

[0075] T e2 = mT e (4)

[0076] The substation feeds back a clock synchronization data packet, which contains the compensation time T for receiving data at the substation. e1 and sending compensation time T e2 .

[0077] 4. Master clock source calculation transmission compensation

[0078] The clock source receives the data packet fed back by the substation and records the time when it starts receiving data C t2 ;

[0079] The main clock source parses the feedback data packet, obtains the data content of the substation feedback, and records the time C t3 ;

[0080] The master clock calculates the receiving compensation time T g1 , as shown in formula (5);

[0081] T g1 = C t3 - C t2 (5)

[0082] Substation calculates transmission compensation time C T , as shown in formula (6);

[0083] C T = (C t3 -T g1 -T e1 -T e2 -T g2 ) / 2 (6)

[0084] 5. The master clock source sends the synchronous clock

[0085] The main clock source records the current clock C t3 ;

[0086] The master clock source adds the master clock source correction time T to the synchronization clock data packet. g and C T ;

[0087] The master clock source sends clock synchronization data packets.

[0088] 6. Substation Synchronous Clock

[0089] The substation receives the clock data packet and parses the data packet;

[0090] Substation calculates synchronization time C t , in C t3 Add T to the clock g , C T and T e1 , as shown in formula (7);

[0091] C t = C t3 + T g + C T + T e1 (7)

[0092] Clock synchronization is complete.

[0093] 7. Clock calibration

[0094] The master clock source sends the standard room periodically with information to be confirmed;

[0095] The substation receives the same standard time and compares it with its own time. If there is no difference, the feedback is normal;

[0096] If there is a difference in the clock verification, the master clock source will perform clock synchronization again.

[0097] In the above embodiments, the description's reference to "this embodiment" indicates that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least some embodiments, but not necessarily all embodiments. Multiple occurrences of "this embodiment" do not necessarily all refer to the same embodiment.

[0098] In the above-described embodiments, although the invention has been described in conjunction with specific embodiments of the invention, many substitutions, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other storage structures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed. Embodiments of the invention are intended to encompass all such substitutions, modifications, and variations that fall within the broad scope of the appended claims.

[0099] This embodiment further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, any one of the methods in this embodiment is implemented.

[0100] This embodiment also provides an electronic terminal, including: a processor and a memory;

[0101] The memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes any one of the methods in this embodiment.

[0102] The computer-readable storage medium in this embodiment can be understood by ordinary technicians in this field: all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0103] The electronic terminal provided in this embodiment includes a processor, a memory, a transceiver and a communication interface. The memory and the communication interface are connected to the processor and the transceiver and complete communication with each other. The memory is used to store computer programs, the communication interface is used to communicate, and the processor and the transceiver are used to run computer programs so that the electronic terminal executes each step of the above method.

[0104] In this embodiment, the memory may include a random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0105] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0106] The present invention can be used in many general or special computing system environments or configurations, such as personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like.

[0107] The present invention may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A clock synchronization optimization calculation method for a security monitoring system, characterized by: The following steps are involved: S1: Select the master clock and synchronize the initial time; S2: Calculate the master clock sending compensation time; S3: Calculate the receiving compensation time and feedback compensation time of the substation; S4: The master clock source calculates the transmission compensation time; S5: The master clock sends the synchronous clock; S6: Substation synchronization clock; S7: The master clock and substation calibrate the clock.

2. The clock synchronization optimization calculation method for a security monitoring system according to claim 1 is characterized in that: In step S1, a master clock is first selected, and the master clock records the initial time C t0 , and then perform network data packet.

3. The clock synchronization optimization calculation method for a security monitoring system according to claim 2 is characterized in that: Step S2 specifically includes the following steps: The master clock sends a network broadcast data packet to the network device and records the time when the transmission is completed C t1 ; Calculate the master clock sending compensation time T g1 , as shown below: T g1 =C t1 -C t0 。 4. The clock synchronization optimization calculation method for a security monitoring system according to claim 3 is characterized in that: Step S3 specifically includes the following steps: The substation starts to receive data packets and records the time t2; The substation parses the data packet to obtain the initial time of the master clock C t0 , and use this time as the initial clock of the synchronization clock, and record the time t3 when the parsing is completed; Calculate the number of bytes of the received data packet n, then the sum of the number of bytes of received data and parsed data is 2n; Calculate the receiving compensation time T of the substation e1 : <h2 style=";text-align:left;direction:ltr">T<h2 style=";text-align:left;direction:ltr"> e1 <h2 style=";text-align:left;direction:ltr"> (t3-t2) Calculate the single byte retention time T of the substation e : Calculate the number of data bytes m that the substation needs to feed back to the master clock source; Calculate the substation feedback compensation time T e2 : T e2 =mT e The substation feeds back a clock synchronization data packet, which contains the substation receiving compensation time T e1 and feedback compensation time T e2 .

5. The clock synchronization optimization calculation method for a security monitoring system according to claim 4 is characterized in that: Step S4 The specific steps include: The master clock receives the clock synchronization data packet fed back by the substation and records the time when it starts receiving data C t2 ; The master clock parses the feedback data packet, obtains the data content of the substation feedback, and records the time C t3 ; The master clock calculates the receiving compensation time T g2 : T g2 =C t3 -C t2 Substation calculates transmission compensation time C T : C T =(C t3 -T g1 -T e1 -T e2 -T g2 ) / 2。 6. The clock synchronization optimization calculation method for a security monitoring system according to claim 5 is characterized in that: Step S5 specifically includes the following steps: The master clock records the current clock C t3 ; The master clock adds the master clock source correction time T to the synchronization clock data packet. g and C T ; The master clock sends clock synchronization data packets.

7. The clock synchronization optimization calculation method for a security monitoring system according to claim 6 is characterized in that: Step S6 specifically includes the following steps: The substation receives the clock data packet and parses the data packet; Substation calculates synchronization time C t , in C t3 Add T to the clock g , C T and T e1 , the calculation formula is as follows; C t =C t3 +T g +C T +T e1 Substation clock synchronization is completed.

8. The clock synchronization optimization calculation method for a security monitoring system according to claim 7 is characterized in that: Step S7 specifically includes the following steps: The master clock sends the standard room regularly with information to be confirmed; The substation receives the same standard time and compares it with its own time. If there is no difference, the feedback is normal; If there is a difference in the clock verification, the master clock will be synchronized again.

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