A method, apparatus, system, equipment, and medium for identifying encryption machines.

Abstract

This invention relates to the fields of communication and electronic information security, and provides a method, apparatus, system, device, and medium for identifying encryption machines. It involves designing a CTR scheduling module and a G-function scheduling module. The CTR scheduling module includes an encryption module based on a symmetric key encryption algorithm, and the G-function scheduling module includes a finite field multiplication module. The CTR scheduling module schedules the encryption module, and the G-function scheduling module schedules the finite field multiplication module, collaboratively completing encryption and decryption operations and outputting ciphertext C and a flag T. This invention balances encryption speed and hardware footprint, achieving a high encryption and decryption rate while using less hardware space.

Description

Technical Field

[0001] This invention relates to the fields of communication and electronic information security, and more specifically, to a method, apparatus, system, device, and medium for identifying encryption machines. Background Art

[0002] SM4 is a commercially available cryptographic algorithm independently developed in my country. It is a block cipher algorithm that uses a symmetric key for encryption. The algorithm has a block length of 128 bits and a key length of 128 bits. Both the encryption algorithm and the key expansion algorithm employ a 32-round nonlinear iterative structure.

[0003] GCM (Galois / Counter Mode) is the operating mode of a block cipher algorithm used for symmetric key encryption. This mode combines the block cipher's CTR mode with the Galois field's GHASH function (G function for short). The CTR mode provides confidentiality protection, while the GHASH function provides integrity protection.

[0004] When GCM mode performs encryption operations, it has four input signals: encryption key K, start variable S, plaintext D, and additional identifiable data A; and two output signals: ciphertext C and flag T.

[0005] The GCM mode encryption process is defined as follows:

[0006] The originator should perform the following steps to protect data D and ensure the integrity of additional identifiable data A.

[0007] a) Select a starting variable S of arbitrary length; different S can be selected for each protected data, and ensure that S can be known by the message recipient; there is no need to ensure that the value of S is unpredictable or secret.

[0008] b) Divide D into blocks to obtain a sequence of data groups: D1, D2, ... D m Where D1 contains the first 128 bits of D, D2 contains the second 128 bits of D, and so on, up to D... m The last r bits of D are included (0 < r ≤ 128); therefore, len(D) = (m - 1) × 128 + r;

[0009] c) Let H = e K (0 128 );

[0010] d) If len(S) = 96, then Y0 = S||0 31 ||1; otherwise Y0=G(H,{},S);

[0011] e) For i = 1, 2, ..., m-1, perform the following two steps:

[0012] 1)Y i =inc(Y i-1 )

[0013] 2)C i =D i ⊕e K (Y i )

[0014] f)Y m =inc(Y m-1 );

[0015] g)C m =D m ⊕(e K (Y m ))| r ;

[0016] h)T=(G(H,A,C1||C2||…||C m )⊕(e K (Y0))| t ;

[0017] Through the above process, the verifiable encrypted data output of data D is C = C1||C2||…||C m ||T.

[0018] The scheme produces identifiable encrypted data C that is t bits longer than the original data D. In addition, the sender must send a variable-length start variable S and additional identifiable data A to the receiver.

[0019] The GCM mode decryption process is defined as follows:

[0020] The recipient should perform the following steps to decrypt and verify the identifiable encrypted data C, and verify additional identifiable data A.

[0021] a) If the length of C is less than t, stop the calculation and return an error;

[0022] b) Determine integers m and r such that the number of bits in C is equal to (m-1)×128+r+t, where 0<r≤128; divide C into blocks to obtain a data block sequence: C1,C2,…,C m T; where C1 contains the first 128 bits of C, C2 contains the second 128 bits of C, and so on, up to C m It contains r bits (0 < r ≤ 128); finally, let T be the last t bits of C;

[0023] c) Let H = e K (0 128 );

[0024] d) If len(S) = 96, then Y0 = S||0 31 ||1; otherwise Y0=G(H,{},S);

[0025] e)T'=(G(H,A,C1||C2||…||C m )⊕(e K (Y0))| t ;

[0026] f) If T≠T', stop the calculation and return an error;

[0027] g) For i = 1, 2, ..., m-1, perform the following two steps:

[0028] 1)Y i =inc(Y i-1 )

[0029] 2)D i =C i ⊕e K (Y i )

[0030] h)Y m =inc(Y m-1 );

[0031] i)D m =C m ⊕(e K (Y m ))| r ;

[0032] j) Output D with additional discriminable data A;

[0033] When using existing encryption schemes, the CTR operation process is highly coupled with the G function operation process, the data interaction during operation is complex, the G function scheduling module is complex to design and has a low operation speed, it is difficult to balance encryption speed and hardware area usage, and it is impossible to obtain a high encryption and decryption speed while using less hardware area. Summary of the Invention

[0034] The present invention aims to provide a method, apparatus, system, device and medium for identifying encryption machines, so as to achieve a high encryption and decryption rate while using less hardware area.

[0035] In a first aspect, the present invention provides an identifiable encryption method, comprising:

[0036] (1) After the GCM operation starts, the CTR scheduling module starts the encryption module and inputs 0. 128 And calculate the H value, and then wait to receive the Y0 value;

[0037] (2) After receiving the H value, the G function scheduling module starts calculating the Y0 value;

[0038] (3) After the Y0 value is calculated, the G function scheduling module starts to receive additional identifiable data A, and performs G function calculation based on the additional identifiable data A and the H value as the initial value of the subsequent calculation flag T;

[0039] (4) Simultaneously with step (3), after receiving the Y0 value, the CTR scheduling module writes the Y0 value into the encryption module and calculates e. K (Y0); where e K () indicates that encryption is performed using the encryption key K;

[0040] (5) After the CTR scheduling module writes the Y0 value to the encryption module, it notifies the outside to write plaintext D. Plaintext D is divided into groups D1, D2, ..., D m Write to the input register; for each group written, the Y generation logic generates Y according to the design. i (1≤i≤m) and write it into the encryption module, calculate e K (Y1), ..., E K (Y m );

[0041] (6) The calculation result e of the encryption module K (Y0), e K (Y1), ..., e K (Y m Enter the encryption result register in sequence;

[0042] (7) The G function scheduling module reads e from the encryption result register. K (Y0) is registered, and then e is read sequentially. K (Y1), ..., e K (Y m Simultaneously, D1, ..., D2 are read sequentially from the input registers. m The ciphertext block sequence C1, ..., C is calculated. m When performing decryption, the ciphertext sequence C1, ..., C is used. m With e K (Y1), ..., e K (Y m The plaintext sequence D1, ..., D2 is calculated. m ;

[0043] (8) While computing the ciphertext sequence, the G function scheduling module calls the finite field multiplication module to sequentially group the ciphertext into C1, ..., C2 groups. m The output values ​​Z1, ..., Z of the finite field multiplication module mPerform iterative calculations, when the last group C is sent... m Then, len(A)||len(C) is fed into the final G function operation; during the decryption operation, the ciphertext sequence C1, ..., C1 read from the input register is used directly. m Perform G function operations; where len() represents the data length;

[0044] (9) After completing the last G-function operation in step (8), the G-function scheduling module will process the result Z of the finite field multiplication module function. m With r K (Y0) is calculated to obtain the flag T, which is then output.

[0045] In some embodiments, in step (2), if the length of the initial variable S is equal to 96 bits, then S||0 31 ||1 is used as the Y0 value; if the length of S is not equal to 96 bits, the S value is received sequentially and the finite field multiplication module is called to calculate the G function based on the S length and H value as the Y0 value.

[0046] In some embodiments, the calculations in the method are as follows:

[0047] In step (7), e is read K (Y1), ..., e K (Y m Simultaneously, D1, ..., D2 are read sequentially from the input registers. m Performing an XOR operation yields the ciphertext block sequence C1, ..., C2. m During decryption, the ciphertext sequence C1, ..., C is used. m With e K (Y1), ..., e K (Y m Perform an XOR operation to obtain the plaintext sequence D1, ..., D2. m ;

[0048] In step (8), the ciphertext is grouped into C1, ..., C... m The output values ​​Z1, ..., Z of the finite field multiplication module m Perform an XOR operation followed by iterative computation;

[0049] In step (9), the result Z of the finite field multiplication module function is... m With e K (Y0) is XORed to obtain the flag T.

[0050] Secondly, the present invention also provides an identifiable encryption device for performing the above-described identifiable encryption method, comprising a CTR scheduling module and a G function scheduling module connected together;

[0051] The CTR scheduling module is equipped with an encryption module based on a symmetric key encryption algorithm;

[0052] The G function scheduling module includes a finite field multiplication module.

[0053] In some embodiments, the symmetric key encryption algorithm of the encryption module is the SM4 algorithm.

[0054] In some embodiments, the encryption module includes a key expansion module and 32 encryption cores; the key expansion module expands the key only when the key is updated.

[0055] In some embodiments, the finite field multiplication module is implemented using combinational logic.

[0056] Thirdly, the present invention also provides an identifiable encryption system, comprising a plurality of the above-described identifiable encryption devices; each of the identifiable encryption devices performs parallel computation.

[0057] Fourthly, the present invention also provides an electronic device, comprising:

[0058] At least one processor; and a memory communicatively connected to said at least one processor;

[0059] The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the instructions stored in the memory to perform the above-described method.

[0060] Fifthly, the present invention also provides a computer-readable storage medium for storing instructions that, when executed, cause the above-described method to be implemented.

[0061] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0062] 1. This invention designs a CTR scheduling module and a G-function scheduling module. The CTR scheduling module includes an encryption module based on a symmetric key encryption algorithm, and the G-function scheduling module includes a finite field multiplication module. The CTR scheduling module schedules the encryption module, and the G-function scheduling module schedules the finite field multiplication module, working together to complete encryption and decryption operations and output ciphertext C and a flag T. Therefore, this invention balances encryption speed and hardware footprint, achieving a high encryption and decryption speed with a smaller hardware footprint.

[0063] 2. In this invention, the encryption module uses only one key expansion module, and the key expansion is only performed when the key is updated. This allows for continuous encryption and decryption calculations of the data stream without changing the key, reducing the hardware footprint and lowering the data stream caching pressure.

[0064] 3. This invention has low complexity and is easy to implement on FPGA and ASIC. Attached Figure Description

[0065] Figure 1 This is a structural block diagram of an identifiable encryption device in an embodiment of the present invention.

[0066] Figure 2 This is a block diagram illustrating the principle of the identifiable encryption method in an embodiment of the present invention.

[0067] Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0069] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0070] like Figure 1 As shown, the present invention provides an identifiable encryption device, comprising a CTR scheduling module and a G function scheduling module connected together; the CTR scheduling module is equipped with an encryption module based on a symmetric key encryption algorithm; and the G function scheduling module is equipped with a finite field multiplication module.

[0071] In this embodiment, the symmetric key encryption algorithm of the encryption module is the SM4 algorithm (therefore, the encryption module is also the SM4 encryption module in the attached figure). Other 128-bit block cipher algorithms, such as AES, can also be used. The number of encryption cores in the SM4 algorithm is the same as the number of encryption operation iterations, that is, 32 encryption cores. Therefore, the operation cycle is 32 clock cycles. After writing the current block, the next block can be written in the next clock cycle, which can realize continuous writing of data stream.

[0072] In this embodiment, the finite field multiplication module is implemented using combinational logic to match the rate of the block cipher. According to the definition of function G, the finite field multiplication module initiates the multiplication operation when the encrypted / decrypted data is valid, and in actual operation, its speed can be significantly greater than the encryption rate of the block cipher.

[0073] In this embodiment, the G function scheduling module uses the GHASH function to obtain a flag T based on the additional identifiable data A and the transmitted encrypted / decrypted data, which is used to indicate whether the message encrypted according to the GCM mode is complete.

[0074] like Figure 2 As shown, based on the aforementioned identifiable encryption device, the flow of an identifiable encryption method is as follows:

[0075] (1) After the GCM operation starts, the CTR scheduling module starts the encryption module and inputs 0. 128 And calculate the H value, and then wait to receive the Y0 value;

[0076] (2) After receiving the H value, the G function scheduling module starts calculating the Y0 value; if the initial variable S has a length of 96 bits, S||0 31 ||1 is used as the Y0 value; if the length of S is not equal to 96 bits, the S values ​​are received sequentially and the finite field multiplication module is called to calculate G(H,{},S) as the Y0 value;

[0077] (3) After the Y0 value is calculated, the G function scheduling module starts to receive additional identifiable data A and calculates G(H,{},A) as the initial value of the subsequent calculation flag T;

[0078] (4) Simultaneously with step (3), after receiving the Y0 value, the CTR scheduling module writes the Y0 value into the encryption module and calculates e. K (Y0); where e K () indicates that encryption is performed using the encryption key K;

[0079] (5) After the CTR scheduling module writes the Y0 value to the encryption module, it notifies the outside that plaintext D can be written. The plaintext D is then grouped into D1, D2, ..., D m Write to the input register; for each group written, the Y generation logic generates Y according to the design. i (1≤i≤m) and write it into the encryption module, calculate e K (Y1), ..., e K (Y m );

[0080] (6) The calculation result e of the encryption module K (Y0), e K (Y1), ..., e K (Y m Enter the encryption result register in sequence;

[0081] (7) The G function scheduling module reads e from the encryption result register. K (Y0) is registered, and then e is read sequentially. K(Y1), ..., e K (Y m Simultaneously, D1, ..., D2 are read sequentially from the input registers. m Perform XOR calculation D1⊕e K (Y1), ..., D m ⊕e K (Y m The ciphertext block sequence C1, ..., C is obtained. m When performing decryption, the ciphertext sequence C1, ..., C is used. m With e K (Y1), ..., e K (Y m Perform an XOR operation to obtain the plaintext sequence D1, ..., D2. m ;

[0082] (8) While computing the ciphertext sequence, the G function scheduling module calls the finite field multiplication module to sequentially group the ciphertext into C1, ..., C2 groups. m The output values ​​Z1, ..., Z of the finite field multiplication module m After performing an XOR operation, iterative calculations are performed until the last group C is input. m Then, len(A)||len(C) is fed into the final G function operation; during the decryption operation, the ciphertext sequence C1, ..., C1 read from the input register is used directly. m Perform G function operations; where len() represents the data length;

[0083] (9) After completing the last G-function operation in step (8), the G-function scheduling module will process the result Z of the finite field multiplication module function. m With e K After performing an XOR operation on (Y0), the flag T is obtained and output.

[0084] This invention designs a CTR scheduling module and a G-function scheduling module. The CTR scheduling module includes an encryption module based on a symmetric key encryption algorithm, and the G-function scheduling module includes a finite field multiplication module. The CTR scheduling module schedules the encryption module, and the G-function scheduling module schedules the finite field multiplication module, working together to complete encryption and decryption operations and output ciphertext C and a flag T. Thus, this invention balances encryption speed and hardware footprint, achieving a high encryption and decryption speed with minimal hardware footprint. Furthermore, the encryption module uses only one key expansion module, and key expansion is only performed when the key is updated. This allows for continuous encryption and decryption calculations of the data stream without key changes, reducing hardware footprint and lowering data stream buffer pressure. Simultaneously, this invention has low complexity and is easily implemented on FPGAs and ASICs.

[0085] Based on the same technical concept, embodiments of the present invention also provide an identifiable encryption system, including multiple of the above-described identifiable encryption devices; each of the identifiable encryption devices performs parallel computation, thereby achieving a higher encryption and decryption rate.

[0086] Based on the same technical concept, embodiments of the present invention also provide an electronic device that can implement the authenticated encryption method flow provided in the above embodiments of the present invention. In one embodiment, the electronic device can be a server, a terminal device, or other electronic devices. Figure 3 As shown, the electronic device may include:

[0087] At least one processor and a memory connected to the at least one processor. In this embodiment of the invention, the specific connection medium between the processor and the memory is not limited. Figure 3 The example used is the connection between the processor and memory via a bus. The bus... Figure 3 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. Buses can be divided into address buses, data buses, control buses, etc., but for ease of representation, [the specific bus type is not shown here]. Figure 3 The processor is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Alternatively, a processor can also be called a controller; there are no restrictions on the name.

[0088] In this embodiment of the invention, the memory stores instructions executable by at least one processor. By executing the instructions stored in the memory, the at least one processor can perform one of the verifiable encryption methods described above. The processor can implement... Figure 3 The functions of each module in the device shown.

[0089] The processor is the control center of the device. It can connect to various parts of the control device through various interfaces and lines. By running or executing instructions stored in memory and calling data stored in memory, it can monitor the device's various functions and process data, thereby enabling overall monitoring of the device.

[0090] In an alternative design, the processor may include one or more processing units. The processor may integrate an application processor and a modem processor, wherein the application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may also not be integrated into the processor. In some embodiments, the processor and memory may be implemented on the same chip; in some embodiments, they may also be implemented separately on separate chips.

[0091] The processor can be a general-purpose processor, such as a CPU, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the identifiable encryption method disclosed in the embodiments of this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0092] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. In embodiments of the present invention, memory can also be a circuit or any other device capable of implementing storage functions, used to store program instructions and / or data.

[0093] By designing and programming the processor, the code corresponding to one of the verifiable encryption methods described in the foregoing embodiments can be embedded into the chip, thereby enabling the chip to perform the steps of one of the verifiable encryption methods described in the foregoing embodiments during operation. How to design and program the processor is a technique well-known to those skilled in the art and will not be elaborated upon here.

[0094] Based on the same inventive concept, embodiments of the present invention also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform an identifiable encryption method as described above.

[0095] In some alternative embodiments, the present invention also provides that various aspects of the identifiable encryption method can also be implemented as a program product comprising program code that, when the program product is run on a device, causes the control device to perform the steps in an identifiable encryption method according to various exemplary embodiments of the present invention as described above.

[0096] It should be noted that although several units or sub-units of the apparatus have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the invention, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units. Furthermore, although the operation of the method of the invention is described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0097] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0098] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0099] Program code for performing the operations of this invention can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0100] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0101] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0102] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0103] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for identifying encryption, characterized in that, Includes the following steps: (1) After the GCM operation starts, the CTR scheduling module starts the encryption module input. And calculate H Value, and then wait to receive. value; (2) G The function scheduling module received H After the value is obtained, the calculation begins. value; (3) After the value calculation is completed, G The function scheduling module begins receiving additional identifiable data. A Based on additional identifiable data A and H value G Function computation serves as a marker for subsequent computations. T The initial value; (4) Simultaneously with step (3), the CTR scheduling module receives After the value, The value is written to the encryption module for calculation. ;in, This indicates that encryption is performed using the encryption key K; (5) The CTR scheduling module will Once the value is written to the encryption module, it notifies the outside world to write plaintext. D plain text D By group ... Write to the input register, one packet at a time. Y The generation logic is generated according to the design. ,1≤ i ≤ m And write it into the encryption module, calculate … ; (6) Calculation results of the encryption module 、 、…、 Enter the encryption result register in sequence; (7) G The function scheduling module reads from the encryption result register Register, then read sequentially. … And simultaneously read sequentially from the input register … The ciphertext block sequence is calculated. … When performing decryption, a ciphertext sequence is used. … and … Calculate the plaintext sequence … ; (8) G While computing the ciphertext sequence, the function scheduling module calls the finite field multiplication module to sequentially group the ciphertext. … Output value of the finite field multiplication module … Perform iterative calculations until the last group is sent. Afterwards, len ( A )|| len ( C Send in for the final test. G Function operations; when performing decryption operations, the ciphertext sequence read from the input register is used directly. … conduct G Function operations; where, len () indicates the data length; (9) G The function scheduling module completes step (8) for the last time. G After the function operation, the result of the finite field multiplication module function will be used. and The mark is obtained after calculation. T , and output.

2. The identifiable encryption method according to claim 1, characterized in that, In step (2), if the starting variable S The length is equal to 96 bits, S || ||1 as Value; if S Length not equal to 96 bits, received sequentially S Value calls the finite field multiplication module, based on S Length and H value G Function computation as value.

3. The identifiable encryption method according to claim 1, characterized in that, The calculations in the method are as follows: In step (7), read … And simultaneously read sequentially from the input register … Perform an XOR operation to obtain the ciphertext block sequence. … When performing decryption, a ciphertext sequence is used. … and … Perform an XOR operation to obtain the plaintext sequence … ; In step (8), the ciphertext is grouped. … Output value of the finite field multiplication module … Perform an XOR operation followed by iterative computation; In step (9), the result of the operation of the finite field multiplication module function is... and The flag is obtained after performing an XOR operation. T .

4. A detectable encryption device for performing the detectable encryption method as described in any one of claims 1-3, characterized in that, Including the connected CTR scheduling module and G Function scheduling module; The CTR scheduling module is equipped with an encryption module based on a symmetric key encryption algorithm; The G The function scheduling module includes a finite field multiplication module.

5. The identifiable encryption device according to claim 4, characterized in that, The symmetric key encryption algorithm of the encryption module is the SM4 algorithm.

6. The identifiable encryption device according to claim 5, characterized in that, The encryption module includes a key expansion module and 32 encryption cores; the key expansion module only expands the key when the key is updated.

7. The identifiable encryption device according to claim 4, characterized in that, The finite field multiplication module is implemented using combinational logic.

8. A distinguishable encryption system, characterized in that, It includes multiple identifiable encryption devices as described in any one of claims 4-7; each of the identifiable encryption devices is computed in parallel.

9. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, which executes the instructions stored in the memory to perform the method as described in any one of claims 1-3.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions that, when executed, cause the method as described in any one of claims 1-3 to be implemented.

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