Automatic time tracking method based on cycle on-off keying and wireless data transmission system thereof

Abstract

A wireless uplink data transmission system based on cyclic on / off keying (COOK) technology and its Automatic Time Tracking (ATT) method are disclosed. The system includes a COOK encoding module, a PLL module, a dynamic comparator, a comparator, a short-circuit switch, and an ATT module. The ATT module generates a reference clock CLK_UP aligned with the voltage signal crossover point by selecting, adjusting, and locking the clock phase generated by the VCO. This clock serves as the input to the COOK encoding module, used to encode the uplink data and control the on / off state of the short-circuit switch. The specific steps of the ATT method include selecting an initial phase, frequency division by two, voltage comparison, phase adjustment, repeated frequency division and comparison, determining whether ATT is complete, and outputting the finally selected CLK_UP. Through this series of steps, the ATT module can automatically track and lock the voltage signal crossover point, ensuring precise alignment of the COOK modulation signal with it.

Description

[Technical Field]

[0001] This invention relates to the field of wireless data transmission, and in particular to an automatic time tracking (ATT) optimization method based on cyclic on-off keying (COOK) and its wireless data transmission system. [Background Technology]

[0002] In recent years, with advancements in medical and integrated circuit technologies, implantable medical devices have been widely used in medical fields such as cochlear implants, retinal prostheses, and brain stimulators. These implantable devices collect signals from within the body and utilize wireless data transmission (WDT) technology to transmit data from inside the body to the outside (uplink), providing doctors with real-time analysis and monitoring of the patient's internal condition. In this field, inductive link-based wireless data transmission technology has become the mainstream choice due to its strong robustness and ease of integration with wireless power transfer systems.

[0003] Uplink data transmission technology based on inductive links employs various modulation methods, such as Load Shift Keying (LSK), Phase Shift Keying (PSK), On-Off Keying (OOK), and Cyclic On-Off Keying (COOK). Among these, the COOK modulation method (patent number US201515316835A) stands out due to its high power efficiency, simple structure, and high data transmission rate, making it a more suitable modulation method for medical implants. COOK-based wireless data transmission systems include... Figure 1 As shown, the system consists of a transmitter (TX), a receiver (RX), and a pair of coupling coils. At the receiver, the uplink data modulation module converts the encoded data into a COOK signal and transmits it to the TX terminal via a short-circuit switch connected in parallel across the receiver coil. When the switch is open, the current I... L2 The capacitor circulates in an LC resonant circuit and is converted to DC by a subsequent rectifier module to power subsequent functional modules; when the switch is closed, the capacitor is short-circuited, and the current I... L2 There is no energy loss as the switch simply idles on the inductor (except for parasitic resistance). A short circuit in the switch simultaneously means a short circuit in the load; this momentary disturbance causes the voltage at the TX terminal to drop. L The voltage amplitude at that point increases, thus being detected by TX as uplink data. However, as... Figure 2As shown, it is essential to ensure that the voltages VAC1 and VAC2 across the receiving coil are equal when the short-circuit switch is closed in order to minimize energy loss and achieve a higher modulation depth. In reality, due to various non-ideal factors (such as coil coupling, parasitic capacitance, and parasitic resistance), VAC1 and VAC2 are often difficult to achieve perfect equality. This mismatch not only increases energy loss but also reduces the modulation depth, thereby affecting the accuracy and reliability of data transmission.

[0004] Therefore, in order to fully leverage the advantages of the COOK modulation method and overcome its limitations, an optimization method is urgently needed to ensure precise alignment of the intersection of VAC1 and VAC2 when the switch is closed. This optimization method requires comprehensive consideration of circuit parameters, switching timing, and the influence of non-ideal factors to achieve more efficient and reliable wireless data transmission. [Summary of the Invention]

[0005] The purpose of this invention is to provide an ATT optimization method based on COOK, which uses phase-locked loop (PLL) and dynamic comparator technology to automatically adjust the clock signal (CLK_UP) generated to control the COOK switch, so as to ensure that the switch action is precisely aligned with the crossover point of VAC1 and VAC2 voltages. It can automatically track the moment when VAC1 and VAC2 voltages are equal and align the COOK switch closing time with it, so as to improve the modulation depth while reducing energy loss and improving energy efficiency.

[0006] The technical solution of the present invention is as follows:

[0007] On the one hand, the present invention provides an automatic time tracking method based on cyclic on / off key control, characterized by comprising the following steps:

[0008] a) Selecting the initial phase: Among the N phases generated by the VCO in the PLL module, select the first phase as the initial phase;

[0009] b) First frequency division operation: Divide the initial phase selected in step a) by two to obtain the clock signal CLK_S;

[0010] c) Compare voltages: At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the comparison result is recorded as CMP_REG. CMP_REG is 1 when VAC1 is greater than VAC2, and CMP_REG is 0 when VAC1 is less than VAC2.

[0011] d) Phase adjustment: Select the next adjacent phase of the VCO clock as the new phase;

[0012] e) Another frequency division operation: Perform frequency division on the adjacent next phase selected in step d) to update and obtain a new clock signal CLK_S;

[0013] f) Repeated comparison: On the rising edge of the new CLK_S, the voltage signals VAC1 and VAC2 are compared again by the dynamic comparator, and the comparison result is recorded as CMP. CMP is 1 when VAC1 is greater than VAC2 and CMP is 0 when VAC1 is less than VAC2.

[0014] g) Determine if automatic time tracking is complete: Compare the values ​​of CMP and CMP_REG. If they are not equal, it indicates that automatic time tracking is complete, and proceed to step h); if they are equal, return to step d), continue to adjust the phase and repeat steps e) to f), until CMP and CMP_REG are not equal.

[0015] h) Output the final selected CLK_UP: Once automatic time tracking is complete, the final selected CLK_S will be output as CLK_UP, which will serve as the clock source for subsequent circuit modules.

[0016] Furthermore, the N phases in step a) are continuous phases generated by the VCO within a preset frequency range.

[0017] Furthermore, the frequency division operation in steps b) and e) is implemented by a frequency divider, which is used to convert the phase generated by the VCO into a clock signal CLK_S.

[0018] Furthermore, the dynamic comparators in steps c) and f) have the characteristics of high-speed comparison and low latency to ensure accurate comparison of voltage signals VAC1 and VAC2 on the rising edge of CLK_S.

[0019] Furthermore, the subsequent circuit module in step h) is the COOK uplink modulation module, with CLK_UP serving as the clock source for this module to achieve accurate transmission of uplink data.

[0020] Second, the present invention also provides a COOK wireless data transmission system optimized based on ATT (Automatic Time Tracking), characterized in that it includes:

[0021] The COOK encoding module is used to receive uplink data (DATA_UP) and reference clock (CLK_UP). It uses CLK_UP as the reference clock to perform COOK encoding on DATA_UP. The encoded COOK signal directly controls the opening and closing of the short-circuit switch to realize the wireless transmission of uplink data.

[0022] The ATT module is used to perform the above method to generate CLK_UP aligned with the intersection of the voltage signals VAC1 and VAC2 at both ends of the receiving coil;

[0023] The PLL module is used to lock the phase of the input signal;

[0024] A dynamic comparator is used to sample and compare voltage signals VAC1 and VAC2 on the rising edge of CLK_S, and output the comparison result CMP or CMP_REG.

[0025] The CMP module is used to acquire the downlink carrier clock at the same frequency as the transmitter.

[0026] The short-circuit switch controls the opening and closing of the circuit based on the status of the COOK signal. When the COOK signal is 1, it closes to allow current to flow, and when the COOK signal is 0, it opens to cut off the current.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] 1) By using technologies such as phase-locked loop (PLL) and dynamic comparator, the clock signal (CLK_UP) generated to control the COOK switch is automatically adjusted to ensure that the switching action is precisely aligned with the voltage crossover point of VAC1 and VAC2. This not only reduces energy loss but also improves the overall energy efficiency of the system and optimizes the modulation depth.

[0029] 2) The ATT module accurately tracks the intersection of the voltage signals VAC1 and VAC2 at both ends of the receiving coil and generates a COOK-coded reference clock CLK_UP accordingly, ensuring precise synchronization of data transmission and thus significantly improving the accuracy and efficiency of data transmission.

[0030] 3) By dynamically adjusting the edges of the clock signal, the ATT module can ensure that the intersection of the clock signal and the voltage signal is precisely aligned, further reducing errors and delays in data transmission.

[0031] 4) The combined use of the PLL module and VCO component enables the system to generate an output signal that is synchronized with the frequency and phase of the input signal, further improving the stability and reliability of the system.

[0032] 5) The ATT module adopts frequency division by two and successive approximation (SAR) logic. By continuously comparing and adjusting the phase, it can automatically adapt to different voltage signal changes, thereby enhancing the robustness and stability of the system. [Attached Image Description]

[0033] Figure 1 This is a block diagram of a COOK-based uplink wireless data transmission system for example purposes.

[0034] Figure 2 The waveform diagrams for the working state of COOK and those assisted by the ATT optimization method are shown.

[0035] Figure 3 This is the actual implementation circuit diagram of a COOK uplink wireless data transmission system with ATT optimization method;

[0036] Figure 4 This is the COOK uplink encoding method used for the example;

[0037] Figure 5 This is the PLL circuit structure used for the example;

[0038] Figure 6 This is a 20-phase VCO circuit structure used as an example;

[0039] Figure 7 It is the successive approximation logic of the proposed ATT optimization method;

[0040] Figure 8 This is a flowchart of the ATT optimization method provided by the present invention;

[0041] Figure 9 These are the COOK test waveforms in Example 1 with / without ATT optimization method assistance.

Detailed Implementation Methods

[0042] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the inventive concept. In the accompanying drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the invention.

[0043] Figure 3 A wireless data transmission system based on ATT-optimized cookie, comprising:

[0044] COOK encoding module 1 receives uplink data (DATA_UP) and a reference clock (CLK_UP). Using CLK_UP as the reference clock, it performs COOK encoding on the uplink data DATA_UP. The resulting COOK signal directly controls the on / off state of the short-circuit switch. The encoding method is as follows: Figure 4 As shown.

[0045] ATT Module 2: Used to generate a reference clock CLK_UP that is aligned with the crossover points of VAC1 and VAC2. The accuracy and efficiency of transmission can be improved by adjusting or optimizing the edges of the clock signal to ensure precise alignment with the crossover points of VAC1 and VAC2.

[0046] PLL (Phase-Locked Loop) 3: Used to generate an output signal that is synchronized with the frequency and phase of the input signal;

[0047] Internally, it contains components of a voltage-controlled oscillator (VCO). The VCO can generate an N-phase clock, with phases covering one carrier cycle. Its circuit diagram is shown below. Figure 5 As shown.

[0048] Latch CMP (Dynamic Comparator) 4: Samples the voltage values ​​of VAC1 and VAC2 on the rising edge of the clock signal CLK_S and compares them.

[0049] CMP (Comparator) 5: Used to obtain the downlink carrier clock with the same frequency as the transmitter.

[0050] Short circuit switch 6: controls the opening and closing of the circuit according to the state of the COOK signal (1 or 0); when COOK is 1, it is closed, allowing current to pass through; when COOK is 0, it is open, cutting off the current.

[0051] ATT's SAR logic is as follows Figure 7 As shown.

[0052] like Figure 8 As shown, the present invention provides a COOK-based ATT method, which includes the following steps:

[0053] Step 1: Select the initial phase

[0054] Among the N phases generated by the VCO within the PLL module, the first phase is selected as the initial phase. This initial phase will serve as the starting point for subsequent operations, used to generate the clock signal and perform subsequent voltage comparisons.

[0055] Step 2: Frequency division operation

[0056] The initial phase selected in step one is divided by two to obtain the clock signal CLK_S. This clock signal will be used in the subsequent dynamic comparator as a reference for comparing voltage signals.

[0057] Step 3: Compare voltages

[0058] At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the comparison result is recorded as CMP_REG. When VAC1 is greater than VAC2, CMP_REG is 1; when VAC1 is less than VAC2, CMP_REG is 0.

[0059] Step 4: Adjust the phase

[0060] The next adjacent phase of the VCO clock is selected as the new phase to prepare for the next frequency division operation and voltage comparison.

[0061] Step 5: Frequency division operation

[0062] The adjacent phase selected in step four is divided by two to obtain a new clock signal CLK_S. This new clock signal will be used for the next voltage comparison.

[0063] Step Six: Repeat the comparison

[0064] At the rising edge of the new CLK_S, the two voltage signals VAC1 and VAC2 are compared again by the dynamic comparator, and the comparison result is recorded as CMP. If VAC1 is greater than VAC2, CMP_REG is 1; if VAC1 is less than VAC2, CMP_REG is 0.

[0065] Step 7: Determine if automatic time tracking is complete.

[0066] Compare the values ​​of CMP and CMP_REG:

[0067] If CMP and CMP_REG are not equal, it means that a point has been found that changes the voltage signal relationship by adjusting the phase, i.e., automatic time tracking has been completed. At this point, we can proceed to the next step and output the finally selected clock signal.

[0068] If CMP and CMP_REG are equal, it means that automatic time tracking has not yet been completed and further phase adjustment is needed. In this case, return to step four, select the next adjacent phase of the VCO clock for a frequency divide-and-comparison comparison, and repeat steps four to seven until a phase point that makes CMP and CMP_REG unequal is found.

[0069] Step 8: Output the final selected CLK_UP

[0070] Once automatic time tracking is complete, the phase point where CMP and CMP_REG are not equal is found. The finally selected CLK_S is output as CLK_UP, which serves as the clock source for the COOK switch and is used in the subsequent COOK uplink modulation module.

[0071] The number of phases in the VCO in step one determines the accuracy of the ATT; the more phases, the higher the accuracy.

[0072] Example 1

[0073] This embodiment discloses an Automatic Time Tracking (ATT) method based on cyclic on / off keying (COOK) technology. This method is applied to a wireless uplink data transmission system. The system employs COOK modulation technology and uses the ATT mechanism to precisely align the closing time of the COOK short-circuit switch with the moment when the voltage across the receiving end (RX end) coil is equal, thereby optimizing data transmission efficiency and quality.

[0074] like Figure 3 As shown, the carrier frequency is 13.56MHz, and module 1 is the COOK encoding module. Using CLK_UP as the reference clock, it encodes the uplink data DATA_UP to generate a COOK signal, which directly controls the on / off state of the short-circuit switch. The encoding method is as follows: Figure 4 As shown. 3 is a PLL, and its circuit diagram is as follows. Figure 5 As shown, it contains a VCO. In this embodiment, the VCO can generate a 20-phase clock, therefore the ATT module's accuracy is... 4 is a dynamic comparator that samples and compares VAC1 and VAC2 on the rising edge of CLK_S. 5 is a comparator used to obtain the downlink carrier clock at the same frequency as the transmitter. 6 is a short-circuit switch, closed when COOK is 1 and open when COOK is 0. 2 is the proposed ATT module, used to generate a COOK-encoded reference clock with its edges aligned with the intersection points of VAC1 and VAC2. The SAR logic of the ATT is as follows: Figure 7 As shown.

[0075] To achieve the aforementioned automatic time tracking COOK modulation, the automatic time tracking module in this embodiment performs the following steps:

[0076] Step 1: Select the initial phase

[0077] Of the 20 phases generated by the VCO within the PLL module, the first phase, VCO[0], is selected as the initial phase. This phase will serve as the starting point for subsequent operations.

[0078] Step 2: Frequency division operation

[0079] The phase selected in step one is divided by two to obtain the clock signal CLK_S. This signal will be used in the subsequent dynamic comparator.

[0080] Step 3: Compare voltages

[0081] At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the result is recorded as CMP_REG (CMP_REG is 1 if VAC1 is greater than VAC2, and 0 if VAC1 is less than VAC2).

[0082] Step 4: Adjust the phase

[0083] Select the next adjacent phase of the VCO clock.

[0084] Step 5: Frequency division operation

[0085] Perform a frequency division by two and update it to the clock signal CLK_S.

[0086] Step Six: Repeat the comparison

[0087] At the rising edge of the new CLK_S, the two voltage signals VAC1 and VAC2 are compared by a dynamic comparator, and the result is recorded as CMP (CMP_REG is 1 if VAC1 is greater than VAC2, and 0 if VAC1 is less than VAC2).

[0088] Step 7: Determine if automatic time tracking is complete.

[0089] If CMP and CMP_REG are not equal, this indicates that automatic time tracking has been completed and you can proceed to the next step.

[0090] If CMP equals CMP_REG, this indicates that automatic time tracking is not yet complete and further phase adjustment is needed. In this case, return to step four and select the next adjacent phase of the VCO clock for division by two. Repeat steps four through seven until the comparison result of the dynamic comparator shows that CMP and CMP_REG are not equal, indicating that automatic time tracking is complete.

[0091] Step 8: Output the final selected CLK_UP

[0092] Once automatic time tracking is complete, the final selected CLK_S will be output as CLK_UP, which will serve as the clock source for the COOK switch. This clock source will be used in the subsequent COOK uplink modulation module.

[0093] like Figure 9 As shown, the COOK signal without the ATT optimization method cannot be aligned with the intersection of VAC1 and VAC2, resulting in a lower modulation depth. The COOK signal assisted by the ATT optimization method is aligned with the intersection of VAC1 and VAC2, resulting in a higher modulation depth.

[0094] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0095] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and additions without departing from the principle of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention.

Claims

1. An automatic time tracking method based on cyclic on / off key control, characterized in that, Includes the following steps: a) Selecting the initial phase: Among the N phases generated by the VCO in the PLL module, select the first phase as the initial phase; b) First frequency division operation: Divide the initial phase selected in step a) by two to obtain the clock signal CLK_S; c) Compare voltages: At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the comparison result is recorded as CMP_REG. CMP_REG is 1 when VAC1 is greater than VAC2, and CMP_REG is 0 when VAC1 is less than VAC2. d) Phase adjustment: Select the next adjacent phase of the VCO clock as the new phase; e) Another frequency division operation: Perform frequency division on the adjacent next phase selected in step d) to update and obtain a new clock signal CLK_S; f) Repeated comparison: On the rising edge of the new CLK_S, the voltage signals VAC1 and VAC2 are compared again by the dynamic comparator, and the comparison result is recorded as CMP. CMP is 1 when VAC1 is greater than VAC2 and CMP is 0 when VAC1 is less than VAC2. g) Determine if automatic time tracking is complete: Compare the values ​​of CMP and CMP_REG. If they are not equal, it indicates that automatic time tracking is complete, and proceed to step h); if they are equal, return to step d), continue to adjust the phase and repeat steps e) to f), until CMP and CMP_REG are not equal. h) Output the final selected CLK_UP: Once automatic time tracking is complete, the final selected CLK_S will be output as CLK_UP, which will serve as the clock source for subsequent circuit modules.

2. The automatic time tracking method based on cyclic on / off key control according to claim 1, characterized in that, The N phases in step a) are continuous phases generated by the VCO within a preset frequency range.

3. The automatic time tracking method based on cyclic on / off key control according to claim 1, characterized in that, The frequency division operation in steps b) and e) is implemented by a frequency divider, which is used to convert the phase generated by the VCO into a clock signal CLK_S.

4. The automatic time tracking method based on cyclic on / off key control according to claim 1, characterized in that, The dynamic comparators in steps c) and f) have high-speed comparison and low-latency characteristics to ensure accurate comparison of voltage signals VAC1 and VAC2 on the rising edge of CLK_S.

5. The automatic time tracking method based on cyclic on / off key control according to claim 1, characterized in that, The subsequent circuit module in step h) is the cyclic on / off key control COOK uplink modulation module, with CLK_UP serving as the clock source for this module to achieve accurate transmission of uplink data.

6. A wireless data transmission system based on Automatic Time Tracking (ATT) optimization using cyclic on / off keying (COOK), characterized in that, include: The cyclic on / off key control COOK encoding module is used to receive uplink data (DATA_UP) and reference clock (CLK_UP). CLK_UP is used as the reference clock to perform cyclic on / off key control COOK encoding on DATA_UP. The encoded cyclic on / off key control COOK signal directly controls the on / off state of the short-circuit switch to realize wireless transmission of uplink data. The ATT module is used to perform the method of any one of claims 1-5 to generate CLK_UP aligned with the intersection of the voltage signals VAC1 and VAC2 at both ends of the receiving coil; The PLL module is used to lock the phase of the input signal; A dynamic comparator is used to sample and compare voltage signals VAC1 and VAC2 on the rising edge of CLK_S, and output the comparison result CMP or CMP_REG. The CMP module is used to acquire the downlink carrier clock at the same frequency as the transmitter. The short-circuit switch controls the on / off state of the circuit based on the status of the cyclic switch key control COOK signal. When the cyclic switch key control COOK signal is 1, it closes to allow current to flow, and when the COOK signal is 0, it opens to cut off the current.

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