Method for correcting phase difference between data and clock, receiver, chip and device
By synchronizing the data lines and compensating for error signals in the receiver, the communication compatibility problem caused by the phase difference between the data and clock lines under the ISO7816 protocol was solved, resulting in more stable communication and higher compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING HONGSI ELECTRONICS TECH
- Filing Date
- 2022-09-14
- Publication Date
- 2026-05-12
AI Technical Summary
Under the ISO7816 protocol, there is a phase difference between the data received by the receiver and the clock line, resulting in poor communication compatibility and the inability to correctly receive the start bit on the data line.
The receiver performs secondary synchronization of the IO signal, obtains the falling edge pulse signal of the start bit, calculates the synchronization delay and logic delay, designs the data line synchronization, and performs compensation processing when an error is detected to ensure that the data line is driven low at the appropriate time to retransmit the character frame.
It improves communication stability and compatibility, enabling normal communication with more products, avoiding transmitter misjudgment and bidirectional drive situations, and enhancing the performance of the ISO7816 protocol interface.
Smart Images
Figure CN115454203B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to methods, receivers, chips, and devices for correcting phase differences between data and clock. Background Technology
[0002] Smart cards and their reader systems are widely used in mobile communications, financial payments, transportation, and public utilities. Typically, contact smart cards and their information exchange with readers are based on the ISO 7816 protocol, including PSAM cards, SAM cards, and SIM cards, all of which comply with the ISO 7816 protocol.
[0003] In traditional designs, when using an interface based on the ISO7816 protocol as a receiver, it is generally assumed that the received data and clock line are synchronized. However, due to differences in the internal logic paths of the chip, actual transmission losses, and non-standard interfaces, there is always a phase difference between the data received by the receiver and the clock line. When the phase difference is large, the receiver cannot correctly receive the start bit on the data line, so the interfaces cannot communicate normally. This makes the communication compatibility of traditional interfaces based on the ISO7816 protocol very poor. Summary of the Invention
[0004] This application provides a method, receiver, chip, and device for correcting phase difference between data and clock signals. The technical solution is as follows:
[0005] In a first aspect, embodiments of this application provide a method for correcting the phase difference between data and clock, including:
[0006] The receiver performs secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal;
[0007] Based on the IO synchronization signal, the starting bit falling edge pulse signal is obtained;
[0008] The hardware logic unit of the receiver sets the start bit enable signal according to the start bit falling edge pulse signal;
[0009] Obtain the synchronization delay between the IO synchronization signal and the falling edge of the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0010] The receiver determines whether the checksum of the character frame is incorrect;
[0011] If so, the receiver determines the compensation time to take over the data line based on the first preset time and the delay duration, and takes over the data line at the compensation time, driving the data line to a low level so that the transmitter retransmits the character frame.
[0012] Secondly, embodiments of this application provide a receiver, which includes a first processing unit, a second processing unit, a third processing unit, a fourth processing unit, and a fifth processing unit;
[0013] The first processing unit is used to perform secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal;
[0014] The second processing unit is used to obtain a start bit falling edge pulse signal based on the IO synchronization signal;
[0015] The third processing unit is used by the hardware logic unit of the receiver to set the start bit enable signal according to the start bit falling edge pulse signal;
[0016] The fourth processing unit is used to obtain the synchronization delay between the IO synchronization signal and the falling edge of the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0017] The fifth processing unit is used to determine whether the checksum of the character frame is incorrect;
[0018] If so, the receiver determines the compensation time to take over the data line based on the first preset time and the delay duration, and takes over the data line at the compensation time, driving the data line to a low level so that the transmitter retransmits the character frame.
[0019] Thirdly, embodiments of this application provide a chip configured as a receiver, the receiver performing the data and clock phase difference correction method described in the first aspect.
[0020] Fourthly, embodiments of this application provide a device including a receiver that performs the data and clock phase difference correction method described in the first aspect.
[0021] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:
[0022] This application provides a method for correcting the phase difference between data and clock signals. It employs a data line synchronization design, synchronizing the clock and data lines to enable the receiver to better receive the start bit on the data line for normal communication. This reduces the timing requirements on the other end of the communication, allowing for communication with a wider range of products. Furthermore, by compensating for erroneous signals through the receiver, it avoids potential misjudgments and bidirectional drive issues that might occur with the transmitter, ensuring stable communication between the two parties. This further improves the performance of interfaces based on the ISO7816 protocol and enhances compatibility. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic flowchart of the data and clock phase difference correction method provided in the embodiments of this application;
[0025] Figure 2 This is a schematic flowchart of the data and clock phase difference correction method provided in the embodiments of this application;
[0026] Figure 3 This is a schematic diagram of the character frame structure provided in an embodiment of this application;
[0027] Figure 4 This is a schematic diagram of a data frame compensation method using the phase difference correction between data and clock provided in an embodiment of this application;
[0028] Figure 5 This is a schematic diagram of the phase difference between data and clock signals appearing in the receiver according to an embodiment of this application;
[0029] Figure 6 This is a schematic diagram of the phase difference between data and clock after the receiver has undergone secondary synchronization, as provided in the embodiments of this application.
[0030] Figure 7 This is a flowchart illustrating a data and clock phase difference correction method provided in another embodiment of this application;
[0031] Figure 8 This is a schematic diagram of a receiver module provided in another embodiment of this application. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0033] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0034] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.
[0035] Example 1:
[0036] The following will be combined with the appendix Figure 1 This application provides a detailed description of a method for correcting the phase difference between data and clock provided in its embodiments.
[0037] This application provides a method for correcting the phase difference between data and clock, comprising the following steps:
[0038] S1. The receiver performs secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal.
[0039] S2. Based on the IO synchronization signal, obtain the starting bit falling edge pulse signal.
[0040] S3. The receiver's hardware logic unit sets the start bit enable signal based on the starting bit falling edge pulse signal.
[0041] S4. Obtain the synchronization delay between the falling edge of the IO synchronization signal and the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0042] S5. The receiver determines whether the check bit of the character frame is incorrect. If so, proceed to step S6; otherwise, proceed to step S7.
[0043] S6. If so, the receiver determines the compensation time for taking over the data line according to the first preset time and the delay duration, and takes over the data line at the compensation time, driving the data line to a low level so that the transmitter retransmits the character frame.
[0044] S7. If the parity check result of the receiver is correct, the receiver will continue to monitor the data line at the beginning of the guard bit stage of the received character frame until the data line is detected to be low, and then start receiving the next character frame.
[0045] Based on the above embodiments, further, in step S6, the receiver determines the compensation time for taking over the data line according to the first preset time and the delay duration, specifically including:
[0046] The receiver advances the first preset time of the receiver by a certain time to obtain the compensation time for the receiver to take over the data line, so that the position of the CLK signal corresponding to the compensation time coincides with the position of the CLK signal corresponding to the first preset time of the IO signal.
[0047] Based on the above embodiments, further, in step S6, driving the data line to a low level so that the transmitter retransmits the character frame specifically includes:
[0048] Drive the data line to a low level so that the transmitter can detect at a second preset time and retransmit the character frame at a third preset time.
[0049] Based on the above embodiments, step S2 further includes:
[0050] After inverting the IO synchronization signal, perform an AND operation with the sampled signal obtained from the sampled IO synchronization signal to obtain the starting bit falling edge pulse signal.
[0051] Based on the above embodiments, the receiver's hardware logic unit further sets a start bit enable signal according to the start bit falling edge pulse signal, specifically including:
[0052] When the starting bit falling edge pulse signal is 1, the starting bit enable signal is set to 1.
[0053] Based on the above embodiments, further, after the receiver takes over the data line, it also includes:
[0054] The receiver's hardware logic unit sets the output enable signal to a high level and sets the value of the output data signal to a first preset value.
[0055] Based on the above embodiments, further, the receiver drives the data line to a low level, including:
[0056] When the output enable signal is high, the receiver controls the data line. The receiver pin outputs a first voltage based on the value of the output data signal, driving the data line to a low level.
[0057] Based on the above embodiments, the first preset time is the 10.5th moment of the character frame, the second preset time is the 11th moment of the character frame, and the third preset time is the 13th moment of the character frame.
[0058] This application provides a method for correcting the phase difference between data and clock signals. It employs a data line synchronization design, synchronizing the clock and data lines to enable the receiver to better receive the start bit on the data line for normal communication. This reduces the timing requirements on the other end of the communication, allowing for communication with a wider range of products. Furthermore, by compensating for erroneous signals through the receiver, it avoids potential misjudgments and bidirectional drive issues that might occur with the transmitter, ensuring stable communication between the two parties. This further improves the performance of interfaces based on the ISO7816 protocol and enhances compatibility.
[0059] Example 2:
[0060] The following will be combined with the appendix Figure 2-6 This application provides a detailed description of a method for correcting the phase difference between data and clock provided in its embodiments.
[0061] like Figure 2 As shown in the figure, an embodiment of this application provides a method for correcting the phase difference between data and clock signals, applied to a chip configured as a receiver, and includes the following steps:
[0062] 110. The receiver performs secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal.
[0063] Specifically, the receiver performs the first synchronization of the IO signal based on the CLK signal to obtain the first-level IO synchronization signal, and then performs the second synchronization of the first-level IO synchronization signal based on the CLK signal to obtain the IO synchronization signal.
[0064] 120. Sample the IO synchronization signal to obtain the sampled signal. Invert the IO synchronization signal and perform an AND operation with the sampled signal to obtain the starting bit falling edge pulse signal.
[0065] Specifically, the I / O synchronization signal is evaluated by the hardware logic unit at the rising edge of the clock. If the I / O synchronization signal is 1, the sampling signal is 1; if the I / O synchronization signal is 0, the sampling signal is 0.
[0066] 130. The receiver's hardware logic unit sets the start bit enable signal based on the starting bit falling edge pulse signal.
[0067] Specifically, when the starting bit falling edge pulse signal is 1, the starting bit enable signal is set to 1.
[0068] 140. Obtain the synchronization delay between the falling edge of the IO synchronization signal and the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0069] For example, the synchronization delay between the falling edge of the IO synchronization signal and the IO signal is 2 communication clocks. The logic delay between the IO synchronization signal and the start bit enable signal is 1 communication clock. Adding the 2 communication clocks of the synchronization delay and the 1 communication clock of the logic delay, we get the delay time between the receiver and the IO signal as 3 communication clocks.
[0070] 150. Determine if the checksum of the character frame is incorrect. If yes, proceed to step 160; otherwise, proceed to step 190.
[0071] For example, according to the frame structure of the 7816 forward protocol, if 0_11000000_1_XXXX appears sequentially on the data line, the first stage is a start bit (logic 0), the second stage is the least significant bit (0x03), and the third stage is a parity bit (logic 1). When the parity bit in the third stage is 1, the parity bit of the character frame is incorrect.
[0072] 160. The receiver advances the 10.5th moment of the receiver's character frame by a certain time to obtain the compensation time for the receiver to take over the data line, so that the position of the CLK signal corresponding to the compensation time coincides with the position of the CLK signal corresponding to the first preset time of the IO signal.
[0073] 170. The receiver's hardware logic unit sets the output enable signal to a high level and sets the value of the output data signal to a first preset value.
[0074] 180. When the output enable signal is high, the receiver controls the data line. The receiver pin outputs the first voltage according to the value of the output data signal, driving the data line to low level, so that the transmitter performs detection at the 11th moment of the character frame and retransmits the character frame at the 13th moment of the character frame.
[0075] 190. If the parity check result of the received character frame is correct, the receiver will continue to monitor the data line at the beginning of the guard bit stage of the received character frame until it detects that the data line is at a low level, and then start receiving the next character frame.
[0076] It should be understood that the embodiments of this application are applicable to protocols such as T=0 and T=1 under the ISO7816 protocol. Taking the T=0 protocol as an example, this application uses a data line synchronization compensation design to achieve higher performance and stronger compatibility.
[0077] Specifically, the ISO 7816 protocol specifies that the duration of one bit on a data line is the Elementary Time Unit (ETU), as shown in the formula. As shown, 1 ETU is equal to the duration of F / D communication clock cycles, where F is the clock frequency conversion factor, D is the bit rate adjustment factor, and f is the frequency of the communication clock.
[0078] like Figure 3 As shown, the T=0 protocol specifies that the character frame structure consists of 12 ETU time periods, where start bit 1 is low, bits 2-9 are data bits, bit 10 is a parity bit, and bits 11-12 are high.
[0079] like Figure 4 As shown, the receiver checks the parity bit of the character frame received from the data line. If the parity bit is incorrect, it takes over the data line from time 10.5 and keeps it low for one or two ETUs until it releases the data line at time 11.5 or 12.5. If the parity bit is correct, it waits to receive the next character frame structure. During this period, the transmitter checks the data line at time 11. If it is high, it will send a new character frame structure at time 12 or 0; if it is low, it considers the receiver to have made a mistake in receiving the current frame and will retransmit the current character frame structure at time 13 or 0 until the receiver receives it correctly or the retransmission limit is reached.
[0080] When the 7816 interface is used as a receiver, it is generally assumed that the received data lines and clock lines are synchronized. Specifically, in traditional designs, such as... Figure 5 In this system, the clock and data lines can be considered synchronous signals. To obtain the falling edge of the start bit low level of the frame structure, the data line is sampled under the communication clock of the clock line. Then, the sampled signal is ANDed with the inverse of the data line to obtain the start bit falling edge pulse signal. However, the data line and the clock line are actually asynchronous signals. When the data line changes at the rising edge of the clock line, due to metastability, the sampled data line may be consistent with the data line, and the calculated start bit falling edge pulse will not exist, making it impossible to generate the start bit enable signal. Alternatively, because the start bit falling edge pulse is extremely narrow, less than one communication clock cycle, it does not meet the normal timing requirements. Furthermore, due to metastability, it is impossible to sample and obtain the start bit enable signal under the timing logic of the clock line, causing the receiver to fail to correctly detect the start bit of the frame structure, resulting in subsequent communication errors.
[0081] The above embodiments employ a data line synchronization design, which synchronizes the clock line and data line, enabling the receiver to better receive the start bit on the data line and perform normal communication. Therefore, it has stronger compatibility, less timing requirements on the other party in the communication, and can communicate with more products.
[0082] In the above embodiments, the clock line and data line received by the receiver are considered as asynchronous signals, such as... Figure 6 As shown, under the communication clock domain of the clock line, the data line is synchronized twice to obtain the data line synchronization 2 signal. The data line synchronization 2 signal is sampled, and the sampled signal is ANDed with the inverse of the data line synchronization 2 signal to obtain the starting bit falling edge pulse signal. Compared with the traditional design, the starting bit falling edge pulse signal obtained after data line synchronization is guaranteed to be one communication clock cycle, which can definitely generate the starting bit enable signal under the timing logic, thereby starting subsequent communication.
[0083] like Figure 6 As shown, there is a delay between the start bit enable signal obtained using the synchronous design and the falling edge on the data line. Analysis shows that the two-level synchronization logic of the data line and clock line requires 2 communication clock cycles, and the logic for generating the start bit falling edge pulse requires 1 communication clock cycle. Therefore, the delay between the receiver's internal timing and the external data line is the duration of 3 communication clock cycles.
[0084] Therefore, in this embodiment of the application, in order to solve the compatibility problem, the data line is synchronized at two levels in the communication clock domain of the clock line to obtain the data line synchronization 2 signal. However, the two-level synchronization causes data lag, thereby affecting communication performance.
[0085] To simultaneously address compatibility issues and reduced communication performance, this embodiment employs a receiver error signal compensation scheme based on data line synchronization. This scheme is better suited for communication scenarios with smaller F / D parameters, further improving the performance of the 7816 interface. Taking the minimum F / D parameter of 8, which is the most difficult to satisfy, as an example, if communication is possible even in the most challenging scenario, then larger F / D parameters will result in even better performance and compatibility.
[0086] exist Figure 4 Before adding the compensation design, the design used a two-level synchronous signal for start bit detection, which actually delayed the start bit detection by three clock cycles. If the receiver determines that the received check bit is incorrect, it will take over the data line after a delay of three communication clock cycles from the 10.5th moment of the character frame, driving it low so that the transmitter can detect it at the 11th moment of the character frame, and then retransmit the current frame structure at the 13th moment of the character frame. Figure 4The starting position of the error signal before compensation is only one communication cycle away from the 11th moment of the key character frame. This margin is too small and can easily cause misjudgment by the transmitter. Furthermore, if the error signal is set to two ETUs, the ending position of the error signal is only one communication cycle away from the 13th moment of the key character frame. This margin is also too small, which can easily lead to bidirectional drive during transmitter transmission, resulting in the absence of a high-level protection bit phase on the data line. This would prevent the receiver from correctly detecting the falling edge of the start bit, affecting subsequent communication.
[0087] The receiver in this embodiment of the application performs error signal compensation processing, such as... Figure 4 As shown, when the receiver detects a parity error, considering the delay of the synchronization logic, it takes over the data line and drives it to a low level three communication clock cycles in advance. This timing coincides with the transmitter's designated 10.5-second timing, and provides sufficient margin for the transmitter-specific 11-second and 13-second timings mentioned earlier. This avoids potential misjudgments and bidirectional driving by the transmitter, ensuring stable communication between the two parties, further improving the performance of the 7816 interface and enhancing compatibility.
[0088] Traditional solutions, with an F / D parameter of 12, can only achieve a normal communication clock frequency of no more than 10MHz; if the F / D parameter is 8, the performance is even lower. The synchronization compensation design used in this application achieves a normal communication clock frequency of up to 60MHz even with an F / D parameter of 8; if the F / D parameter is even higher, the performance is even better. (Based on the formula...) Based on the ETU rate, the interface communication performance in this embodiment can reach 9 times that of traditional designs.
[0089] This application provides a method for correcting the phase difference between data and clock signals. It employs a data line synchronization design, synchronizing the clock and data lines to enable the receiver to better receive the start bit on the data line for normal communication. This reduces the timing requirements on the other end of the communication, allowing for communication with a wider range of products. Furthermore, by compensating for erroneous signals through the receiver, it avoids potential misjudgments and bidirectional drive issues that might occur with the transmitter, ensuring stable communication between the two parties. This further improves the performance of interfaces based on the ISO7816 protocol and enhances compatibility.
[0090] Example 3:
[0091] The following will be combined with the appendix Figure 7 This application provides a detailed description of a method for correcting the phase difference between data and clock provided in its embodiments.
[0092] This application provides a method for correcting the phase difference between data and clock signals, applicable to a chip system where the main chip is configured as a receiver and the slave chip is configured as a transmitter. The method includes the following steps:
[0093] 210. The receiver initiates the CLK signal.
[0094] 220. The transmitter initiates an I / O signal that reaches the receiver.
[0095] 230. The receiver uses a level synchronizer to perform two-stage synchronization of the IO signal based on the CLK signal.
[0096] 240. The receiver samples the IO synchronization signal to obtain the sampled signal. The inverted IO synchronization signal is ANDed with the sampled signal to obtain the starting bit falling edge pulse signal.
[0097] 250. The receiver's hardware logic unit sets the start bit enable signal based on the starting bit falling edge pulse signal.
[0098] Specifically, when the starting bit falling edge pulse is 1, the hardware logic unit sets the starting bit enable signal to a high level.
[0099] 260. The receiver obtains the synchronization delay between the falling edge of the IO synchronization signal and the start bit of the IO signal, calculates the logic delay of the IO synchronization signal and the start bit enable signal, and obtains the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0100] 270. The receiver determines whether the checksum of the character frame is incorrect. If yes, proceed to step 280; otherwise, proceed to step 320.
[0101] 280. The receiver advances the 10.5th moment of the receiver's character frame by a certain time to obtain the compensation time for the receiver to take over the data line, so that the position of the CLK signal corresponding to the compensation time coincides with the position of the CLK signal corresponding to the first preset time of the IO signal, and takes over the data line at the compensation time.
[0102] 290. The receiver's hardware logic unit sets the output enable signal to a high level and sets the value of the output data signal to a first preset value.
[0103] 300. When the output enable signal is high, the receiver controls the data line. The receiver pin outputs the first voltage according to the value of the output data signal, driving the data line to low level.
[0104] 310. The transmitter performs a detection at time 11 of the character frame and retransmits the character frame at time 13 of the character frame.
[0105] 320. If the parity check result of the receiver is correct, the receiver will continue to monitor the data line at the beginning of the guard bit stage of the received character frame until it detects that the data line is at a low level, and then start receiving the next character frame.
[0106] Specifically, when the master chip is configured as a transmitter and the slave chip as a receiver, or vice versa, both the receiver and transmitter are connected via CLK and IO signals. The master chip generates the CLK signal, and the slave chip receives it. The chip acting as the transmitter needs to send data based on the CLK signal, and the chip acting as the receiver also needs to receive data based on the CLK signal. When the master chip is configured as a transmitter, it generates a clock signal CLK_m to drive the data line IO_m signal. However, the CLK and IO signals reaching the receiver may not be synchronized due to factors such as line length, environment, material, or even hardware logic. The receiver needs to synchronize the data line IO_s signal based on the CLK_s signal received by the receiver; otherwise, metastability may occur, leading to errors. Similarly, when the slave chip acts as a transmitter, the phase between the CLK_s and IO_s signals at the slave chip's transmitter interface may also be inconsistent with the CLK_m and IO_m signals at the master chip's receiver port. The master chip's receiver needs to synchronize the data line IO_m signal at its port with the CLK_m signal.
[0107] This application provides a method for correcting the phase difference between data and clock signals. It employs a data line synchronization design, synchronizing the clock and data lines to enable the receiver to better receive the start bit on the data line for normal communication. This reduces the timing requirements on the other end of the communication, allowing for communication with a wider range of products. Furthermore, by compensating for erroneous signals through the receiver, it avoids potential misjudgments and bidirectional drive issues that might occur with the transmitter, ensuring stable communication between the two parties. This further improves the performance of interfaces based on the ISO7816 protocol and enhances compatibility.
[0108] Example 4:
[0109] This application provides a method for correcting the phase difference between data and clock signals, applicable to a chip system where the main chip is configured as a transmitter and the slave chip is configured as a receiver. The method includes the following steps:
[0110] 410. The transmitter initiates the CLK signal.
[0111] 420. The receiver initiates an I / O signal that reaches the transmitter.
[0112] 430. The receiver uses a level synchronizer to perform two-stage synchronization of the IO signal based on the CLK signal.
[0113] 440. The receiver samples the IO synchronization signal to obtain the sampled signal. The inverted IO synchronization signal is ANDed with the sampled signal to obtain the starting bit falling edge pulse signal.
[0114] 450. The receiver's hardware logic unit sets the start bit enable signal based on the starting bit falling edge pulse signal.
[0115] Specifically, when the starting bit falling edge pulse is 1, the hardware logic unit sets the starting bit enable signal to a high level.
[0116] 460. The receiver obtains the synchronization delay between the falling edge of the IO synchronization signal and the start bit of the IO signal, calculates the logic delay between the IO synchronization signal and the start bit enable signal, and obtains the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0117] 470. The receiver determines whether the checksum of the character frame is incorrect. If yes, proceed to step 480; otherwise, proceed to step 520.
[0118] 480. The receiver advances the 10.5th moment of the receiver's character frame by a certain time to obtain the compensation time for the receiver to take over the data line, so that the position of the CLK signal corresponding to the compensation time coincides with the position of the CLK signal corresponding to the first preset time of the IO signal, and takes over the data line at the compensation time.
[0119] 490. The receiver's hardware logic unit sets the output enable signal to a high level and sets the value of the output data signal to a first preset value.
[0120] 500. When the output enable signal is high, the receiver controls the data line. The receiver pin outputs the first voltage according to the value of the output data signal, driving the data line to low level.
[0121] 510. The transmitter performs a detection at time 11 of the character frame and retransmits the character frame at time 13 of the character frame.
[0122] 520. If the parity check result of the receiver is correct, the receiver will continue to monitor the data line at the beginning of the guard bit stage of the received character frame until it detects that the data line is at a low level, and then start receiving the next character frame.
[0123] This application provides a method for correcting the phase difference between data and clock signals. It employs a data line synchronization design, synchronizing the clock and data lines to enable the receiver to better receive the start bit on the data line for normal communication. This reduces the timing requirements on the other end of the communication, allowing for communication with a wider range of products. Furthermore, by compensating for erroneous signals through the receiver, it avoids potential misjudgments and bidirectional drive issues that might occur with the transmitter, ensuring stable communication between the two parties. This further improves the performance of interfaces based on the ISO7816 protocol and enhances compatibility.
[0124] Example 5:
[0125] The following will be combined with the appendix Figure 8 This application provides a detailed description of a receiver provided in its embodiments.
[0126] An embodiment of this application provides a receiver, which includes a first processing unit, a second processing unit, a third processing unit, a fourth processing unit, and a fifth processing unit;
[0127] The first processing unit is used to perform secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal;
[0128] The second processing unit is used to obtain a start bit falling edge pulse signal based on the IO synchronization signal;
[0129] The third processing unit is used by the hardware logic unit of the receiver to set the start bit enable signal according to the start bit falling edge pulse signal;
[0130] The fourth processing unit is used to obtain the synchronization delay between the IO synchronization signal and the falling edge of the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay.
[0131] The fifth processing unit is used to determine whether the checksum of the character frame is incorrect;
[0132] If so, the receiver determines the compensation time to take over the data line based on the first preset time and the delay duration, and takes over the data line at the compensation time, driving the data line to a low level so that the transmitter retransmits the character frame.
[0133] Based on the above embodiments, the fifth processing unit is specifically used to advance the first preset time of the receiver by the delay duration to obtain the compensation time for the receiver to take over the data line, so that the position of the CLK signal corresponding to the compensation time coincides with the position of the CLK signal corresponding to the first preset time of the IO signal.
[0134] Based on the above embodiments, the fifth processing unit is specifically used to drive the data line to a low level so that the transmitter performs detection at a second preset time and retransmits the character frame at a third preset time.
[0135] Based on the above embodiments, the second processing unit is further configured to invert the IO synchronization signal and perform an AND operation with the sampled signal obtained by sampling the IO synchronization signal to obtain the starting bit falling edge pulse signal.
[0136] Based on the above embodiments, the third processing unit is specifically used to set the start bit enable signal to 1 when the start bit falling edge pulse signal is 1.
[0137] Based on the above embodiments, the fifth processing unit is specifically used to set the output enable signal to a high level and set the value of the output data signal to a first preset value in the hardware logic unit of the receiver.
[0138] Based on the above embodiments, the fifth processing unit is specifically used to control the data line when the output enable signal is high, and the receiver pin outputs a first voltage according to the value of the output data signal to drive the data line to low level.
[0139] This application provides a receiver that employs a data line synchronization design, synchronizing the clock and data lines. This allows the receiver to better receive the start bit on the data line for normal communication, reducing timing requirements on the other end and enabling communication with a wider range of products. Furthermore, by compensating for erroneous signals, the receiver avoids potential misjudgments and bidirectional driving issues that might occur with the transmitter, ensuring stable communication between the two parties. This further improves the performance of interfaces based on the ISO7816 protocol and enhances compatibility.
[0140] This application also provides a chip configured as a receiver, which performs the data and clock phase difference correction method described above.
[0141] This application also provides a device including a receiver, which performs the data and clock phase difference correction method described above.
[0142] Those skilled in the art will understand that each block in these structural diagrams and / or block diagrams and / or flow diagrams, as well as combinations of blocks in these structural diagrams and / or block diagrams and / or flow diagrams, can be implemented using computer program instructions. Those skilled in the art will also understand that these computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing method for implementation, thereby enabling the processor of the computer or other programmable data processing method to execute the schemes specified in the blocks or multiple blocks of the structural diagrams and / or block diagrams and / or flow diagrams disclosed in this application.
[0143] The various modules of the device described in this application can be integrated into one unit or deployed separately. These modules can be combined into one module or further divided into multiple sub-modules.
[0144] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing this application.
[0145] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.
[0146] The serial numbers in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0147] The above-disclosed embodiments are merely a few specific examples of this application. However, this application is not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of this application.
Claims
1. A method for correcting the phase difference between data and clock, characterized in that, The method includes: The receiver performs secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal; Based on the IO synchronization signal, the starting bit falling edge pulse signal is obtained; The hardware logic unit of the receiver sets the start bit enable signal according to the start bit falling edge pulse signal; Obtain the synchronization delay between the IO synchronization signal and the falling edge of the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay. The receiver determines whether the checksum of the character frame is incorrect; If so, the receiver determines the compensation time for taking over the data line based on the first preset time and the delay duration, and takes over the data line at the compensation time, driving the data line to a low level so that the transmitter retransmits the character frame.
2. The method according to claim 1, characterized in that, The receiver determines the compensation time to take over the data line based on a first preset time and the delay duration, specifically including: The receiver advances the first preset time of the receiver by the delay duration to obtain the compensation time for the receiver to take over the data line, so that the position of the CLK signal corresponding to the compensation time coincides with the position of the CLK signal corresponding to the first preset time of the IO signal.
3. The method according to claim 1, characterized in that, Driving the data line to a low level so that the transmitter retransmits the character frame specifically includes: Drive the data line to a low level so that the transmitter can detect at a second preset time and retransmit the character frame at a third preset time.
4. The method according to claim 1, characterized in that, The step of obtaining the starting bit falling edge pulse signal based on the IO synchronization signal specifically includes: After inverting the IO synchronization signal, perform an AND operation with the sampled signal obtained by sampling the IO synchronization signal to obtain the starting bit falling edge pulse signal.
5. The method according to claim 1, characterized in that, The hardware logic unit of the receiver sets a start bit enable signal based on the starting bit falling edge pulse signal, specifically including: When the starting bit falling edge pulse signal is 1, the starting bit enable signal is set to 1.
6. The method according to claim 1, characterized in that, After the receiver takes over the data line, it also includes: The hardware logic unit of the receiver sets the output enable signal to a high level and sets the value of the output data signal to a first preset value.
7. The method according to claim 6, characterized in that, The receiver drives the data line to a low level, including: When the output enable signal is high, the receiver controls the data line, and the receiver pin outputs a first voltage according to the value of the output data signal, driving the data line to a low level.
8. The method according to claim 1 or 2, characterized in that, The first preset time is the 10.5th time of the character frame.
9. The method according to claim 3, characterized in that, The second preset time is the 11th moment of the character frame, and the third preset time is the 13th moment of the character frame.
10. A receiver, characterized in that, The receiver includes a first processing unit, a second processing unit, a third processing unit, a fourth processing unit, and a fifth processing unit; The first processing unit is used to perform secondary synchronization of the IO signal based on the CLK signal to obtain the IO synchronization signal; The second processing unit is used to obtain a start bit falling edge pulse signal based on the IO synchronization signal; The third processing unit is used by the hardware logic unit of the receiver to set the start bit enable signal according to the start bit falling edge pulse signal; The fourth processing unit is used to obtain the synchronization delay between the IO synchronization signal and the falling edge of the start bit of the IO signal, calculate the logic delay between the IO synchronization signal and the start bit enable signal, and obtain the delay duration between the receiver and the IO signal based on the synchronization delay and the logic delay. The fifth processing unit is used to determine whether the checksum of the character frame is incorrect; If so, the receiver determines the compensation time for taking over the data line based on the first preset time and the delay duration, and takes over the data line at the compensation time, driving the data line to a low level so that the transmitter retransmits the character frame.
11. A chip configured as a receiver, characterized in that, The receiver performs the data and clock phase difference correction method according to any one of claims 1-9.
12. An electronic device, characterized in that, The electronic device includes a receiver that performs the data and clock phase difference correction method according to any one of claims 1-9.