Preparation method of nonvolatile memory with assembly structure

Abstract

The invention provides a preparation method of a nonvolatile memory with an assembly structure. The preparation method comprises the steps that a substrate is provided, and a gate material layer, a first hard mask layer and a second hard mask layer which are stacked in sequence are formed on the substrate; forming a first opening in the second hard mask layer; forming a first side wall in the first opening, wherein the first side wall is of an annular structure attached to the side wall of the first opening; filling the first opening with a third hard mask layer; removing the second hard mask layer; forming a second side wall on the outer side of the first side wall; removing the third hard mask layer; sequentially etching the first hard mask layer and the gate material layer downwards by taking the first side wall and the second side wall as masks to form a gate ring; and etching to remove the two opposite end parts of the gate ring, so that the gate ring is cut into gate electrodes of the two storage tubes of the same pair of storage units. Therefore, the area of the pairing storage unit of the nonvolatile memory with the pairing structure can be reduced, and the size and the cost of a storage chip are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of memory manufacturing, and in particular to a method for preparing a pair structure non-volatile memory. Background Art

[0002] Figure 1 A layout diagram of a pair-structured non-volatile memory. Figure 2 for Figure 1 The illustrated diagram is an architectural diagram of a pair of memory cells in a pair-structured nonvolatile memory. Figure 3 Schematic diagram of a cross-section of a pair structure non-volatile memory, wherein: Figure 3 for Figure 1 The cross-sectional view of the position indicated by line BB in FIG. Figure 1 , Figure 2 and Figure 3 As shown, a pair memory cell of the pair structure non-volatile memory includes a first memory transistor M1 and a second memory transistor M2 electrically connected through a diffusion region A (Diffusion Region) in an active region. However, due to the resolution of photolithography, each logic technology node has a design rule for each node, so that a certain distance must be maintained between the gates 10 of the first memory transistor M1 and the second memory transistor M2 of the same pair memory cell, so that the width of the diffusion region A is larger, resulting in a larger area of ​​the pair memory cell, and further resulting in a larger area of ​​the pair structure non-volatile memory, which reduces the cost performance of the pair structure non-volatile memory. Summary of the invention

[0003] The present invention provides a method for preparing a pair structure non-volatile memory, which can reduce the area of ​​the pair storage unit of the pair structure non-volatile memory, reduce the size and cost of the memory chip, and improve the cost performance of the memory chip.

[0004] In order to achieve the above-mentioned purpose, the preparation method of the group-pair structure non-volatile memory provided in this embodiment includes: providing a substrate, on which a gate material layer, a first hard mask layer and a second hard mask layer are stacked in sequence from bottom to top; forming a first opening in the second hard mask layer; forming a first side wall in the first opening, the first side wall being a ring-shaped structure covering the side wall of the first opening; filling a third hard mask layer in the first opening; removing the second hard mask layer; forming a second side wall on the outer side of the first side wall, the second side wall surrounding and covering the first side wall; removing the third hard mask layer; using the first side wall and the second side wall as masks, etching the first hard mask layer and the gate material layer downward in sequence to form a gate ring; etching and removing the two opposite ends of the gate ring, so that the gate ring divides the gate electrodes of the two storage tubes of the same group-pair storage unit.

[0005] Optionally, in the step of providing a substrate, the substrate has an isolation structure and an active area defined by the isolation structure; in the step of forming a gate ring, the gate ring spans the active area, and two opposite ends of the gate ring are located on the isolation structure on both sides of the active area.

[0006] Optionally, the first sidewall spacer spans across the active area, and two opposite ends of the first sidewall spacer extend beyond the active area and are located on the isolation structures at two sides of the active area.

[0007] Optionally, the method for etching away the two opposite ends of the gate ring includes: forming a second photoresist mask layer on the substrate, the second photoresist mask layer having a plurality of second openings, the second openings being located above the isolation structure, and the two opposite ends of the gate ring are exposed from the corresponding second openings; using the second photoresist mask layer as a mask, etching away the two opposite ends of the gate ring and stopping on the isolation structure.

[0008] Optionally, two storage tubes of the same pair of storage cells are electrically connected via an active region between gate electrodes of the two storage tubes.

[0009] Optionally, the method of filling the first opening with a third hard mask layer includes: forming a third hard mask layer on the substrate, the third hard mask layer covering the second hard mask layer and the first side wall, and filling the first opening; and removing the third hard mask layer above the second hard mask layer by a chemical mechanical polishing process or a back etching process.

[0010] Optionally, the first sidewall spacer and the second sidewall spacer are made of the same material; and the first sidewall spacer, the first hard mask layer, the second hard mask layer and the third hard mask layer are made of different materials.

[0011] Optionally, in the step of providing a substrate, the substrate has a storage area and a logic area, a charge trap layer is formed on the storage area, a gate oxide layer is formed on the logic area, and the gate material layer covers the charge trap layer and the gate oxide layer; the gate ring formed subsequently is located on the storage area.

[0012] Optionally, after removing the third hard mask layer and before etching downward in sequence the first hard mask layer and the gate material layer, the preparation method further includes: forming a first photoresist mask layer on the first hard mask layer, the first photoresist mask layer covering a portion of the logic area and exposing the storage area; the step of etching downward in sequence the first hard mask layer and the gate material layer includes: using the first side wall, the second side wall and the first photoresist mask layer as a mask, etching downward the first hard mask layer, the gate material layer, the charge trap layer and the gate oxide layer and stopping on the substrate, retaining part of the gate material layer as the gate ring and part as the selection tube gate located on the logic area.

[0013] Optionally, after etching downward the first hard mask layer and the gate material layer in sequence and before etching away two opposite ends of the gate ring, the preparation method further includes: removing the first side wall, the second side wall and the first hard mask layer.

[0014] The preparation method of the paired structure non-volatile memory provided by the present invention has the following advantages: (1) using the first sidewall and the second sidewall as masks, etching the gate material layer to form a gate ring, and then etching away the two opposite ends of the gate ring, so that the gate ring divides the gate electrodes of the two storage tubes of the same paired storage unit. In this way, the spacing between the gate electrodes of the two storage tubes of the same paired storage unit is not restricted by the resolution capability of photolithography, so that the spacing between the gate electrodes of the two storage tubes of the same paired storage unit is small, thereby reducing the area of ​​the paired storage unit of the paired structure non-volatile memory, which helps to reduce the size and cost of the storage chip and improve the cost performance of the storage chip; (2) the present invention has a first opening in the second hard mask layer. A first side wall is formed in the opening, and then a third hard mask layer is filled in the first opening, and then the second hard mask layer is removed, and then a second side wall is formed on the outside of the first side wall and the third hard mask layer is removed, and then the first side wall and the second side wall are used as masks to sequentially etch downward the first hard mask layer and the gate material layer to form a gate ring, so that the gate ring can be defined by a one-step self-aligned etching, that is, the spacing between the gate electrodes of the two storage tubes of the same pair of storage cells and the length of the gate electrode of the storage tube are defined by a one-step self-aligned etching, the process is relatively simple, and it is helpful to improve the size consistency of the two gate electrodes of the pair of storage cells, improve the performance consistency of the two storage tubes of the pair of storage cells, and thus improve the performance of the pair structure non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A layout diagram of a pair-structured nonvolatile memory.

[0016] Figure 2 for Figure 1 The illustrated diagram is an architectural diagram of a pair of memory cells in a pair-structured nonvolatile memory.

[0017] Figure 3 A cross-sectional schematic diagram of a pair-structured non-volatile memory.

[0018] Figure 4 The present invention is a flowchart of a method for preparing a pair structure non-volatile memory according to an embodiment of the present invention.

[0019] Figures 5 to 30 A schematic diagram of the process structure of a method for preparing a pair structure non-volatile memory provided by an embodiment of the present invention.

[0020] Explanation of the reference numerals: 100-active area; 101-isolation structure; 102-charge trap layer; 103-gate oxide layer; 104-gate material layer; 104a-gate ring; 104b-selector gate; 104c-gate electrode; 105-amorphous carbon layer; 106-silicon oxynitride layer; 107-second hard mask layer; 108-first opening; 109-first sidewall; 110-third hard mask layer; 111-second sidewall; 112-bottom anti-reflective coating; 113-first photoresist mask layer; 114-second photoresist mask layer; 114a-second opening. DETAILED DESCRIPTION

[0021] The following is a further detailed description of the preparation method of the pair structure non-volatile memory proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] In the description of the present application, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, and at least one means one, two or more, unless otherwise clearly and specifically defined.

[0023] Figure 4 The flowchart of the method for preparing the pair structure non-volatile memory provided by one embodiment of the present invention is as follows. Figure 4 As shown, the preparation method of the pair structure non-volatile memory provided by the present application includes: Step S1, providing a substrate, on which a gate material layer, a first hard mask layer, and a second hard mask layer are stacked in sequence from bottom to top are formed; Step S2, forming a first opening in the second hard mask layer; Step S3, forming a first side wall in the first opening, wherein the first side wall is a ring-shaped structure covering the side wall of the first opening; Step S4, filling the first opening with a third hard mask layer; Step S5, removing the second hard mask layer; Step S6, forming a second side wall on the outer side of the first side wall, the second side wall surrounds and covers the first side wall; Step S7, removing the third hard mask layer; Step S8, using the first sidewall spacer and the second sidewall spacer as masks, sequentially etching the first hard mask layer and the gate material layer downward to form a gate ring; Step S9, etching and removing two opposite ends of the gate ring, so that the gate ring divides the gate electrodes of two storage tubes of the same pair of storage cells.

[0024] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0025] Figures 5 to 30 The following is a schematic diagram of the process structure of a method for preparing a pair structure non-volatile memory according to an embodiment of the present invention. Figure 4 , Figures 5 to 30 The preparation method of the pair structure non-volatile memory provided by the present application is described. Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 , Fig.25 , Fig. 27 , Fig.29 and Fig.30 This is a top view during the preparation process. Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 and Fig.28 The cross-sectional views are taken during the preparation process, and the cross-sectional views are taken along the CC line in the top view (reference Figure 5 ) cross-sectional view in the direction shown.

[0026] refer to Figure 5 and Figure 6 As shown, a gate material layer 104 , a first hard mask layer and a second hard mask layer 107 stacked in sequence from bottom to top are formed on the substrate provided in step S1 .

[0027] In this embodiment, reference Figure 5 and Figure 6 As shown, the substrate has an isolation structure 101 and an active area 100 defined by the isolation structure 101. The active area 100 and the isolation structure 101 can be formed on the top of the substrate. The substrate can have multiple active areas 100; the multiple active areas 100 can be arranged in parallel, but are not limited to this. The isolation structure 101 can be a shallow trench isolation structure (STI), but is not limited to this; the isolation structure 101 includes a shallow trench formed in the substrate and an isolation oxide layer filling the shallow trench, and the isolation oxide layer includes, for example, silicon oxide.

[0028] In this embodiment, the substrate may be a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc., and certain doping particles may be injected into the substrate according to design requirements to change electrical parameters.

[0029] In this embodiment, the storage tube of the pair structure non-volatile memory is a charge trap type storage tube, but it is not limited thereto. Figure 6 As shown, the substrate has a storage area and a logic area, a charge trap layer 102 is formed on the storage area, and a gate oxide layer 103 is formed on the logic area, or in other words, the charge trap layer 102 covers the storage area of ​​the substrate for forming a storage tube, and the gate oxide layer 103 covers the logic area of ​​the substrate, and the logic area is located outside the storage area.

[0030] For example, the charge trap layer 102 may be an ONO layer, including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked sequentially from bottom to top, but not limited thereto. For example, the gate oxide layer 103 may include a silicon oxide layer.

[0031] It should be noted that, in order to facilitate the illustration of the relationship between the isolation structure 101 and the active region 100 in the substrate, Figure 5 The first hard mask layer, the gate material layer 104, the charge trap layer 102 and the gate oxide layer 103 between the substrate and the second hard mask layer 107 are not shown.

[0032] refer to Figure 5 and Figure 6 As shown, the gate material layer 104 covers the charge trap layer 102 and the gate oxide layer 103. By way of example, the gate material layer 104 includes but is not limited to a polysilicon layer.

[0033] In this embodiment, the first hard mask layer is a double-layer structure, including an amorphous carbon layer 105 covering the gate material layer 104 and a silicon oxynitride (SiON) layer 106 covering the amorphous carbon layer 105. The silicon oxynitride layer 106 can be used as a dielectric anti-reflective coating (DARC) between the amorphous carbon layer 105 and the second hard mask layer 107. In some other embodiments, the first hard mask layer can also be a single-layer structure including a single material layer. In some embodiments, the silicon oxynitride layer 106 can be replaced with carbon-doped silicon oxide (SiCO) or the like, as long as the materials of the sidewalls (including the first sidewall and the second sidewall), the first hard mask layer, the second hard mask layer, and the third hard mask layer are different.

[0034] The second hard mask layer 107 includes, but is not limited to, a silicon nitride layer.

[0035] In this embodiment, the second hard mask layer 107 and the silicon oxynitride layer 106 may be formed at a temperature below 400° C.

[0036] Exemplarily, the thickness of the gate material layer 104 is 600Å~1000Å, for example, 800Å. The thickness of the amorphous carbon layer 105 is 400Å~800Å, for example, 600Å. The thickness of the silicon oxynitride layer 106 is 100Å~300Å, for example, 200Å. The thickness of the second hard mask layer 107 is 400Å~800Å, for example, 600Å. It should be noted that the thicknesses of the gate material layer 104, the amorphous carbon layer 105, the silicon oxynitride layer 106 and the second hard mask layer 107 can be adjusted as needed.

[0037] refer to Figure 7 and Figure 8 As shown, step S2 is performed to form a first opening 108 in the second hard mask layer 107 .

[0038] In this embodiment, the first opening 108 may cross the active region 100 and have both ends extending to the isolation structure 101 on both sides of the active region 100. Figure 7 As shown, the opening shape of the first opening 108 may be rectangular, but is not limited thereto.

[0039] In step S2 , a plurality of first openings 108 may be formed in the second hard mask layer 107 . The plurality of first openings 108 may be arranged in an array so as to subsequently form array-arranged storage tubes.

[0040] Exemplarily, step S2 may include: forming a photoresist layer on the second hard mask layer 107; exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, etching the second hard mask layer 107 and stopping on the first hard mask layer to form a first opening 108.

[0041] In this embodiment, after etching through the second hard mask layer 107, an appropriate amount of over-etching can be performed and the etching stops in the silicon oxynitride layer 106. In the process of etching to form the first opening 108, when it is detected that the etching reaches the surface of the silicon oxynitride layer 106, a slight over-etching can be performed by fixing the etching time so that the etching stops in the silicon oxynitride layer 106.

[0042] In this embodiment, the width of the first opening 108 (ie Figure 8 The size in the horizontal direction can be set according to the length of the gate electrodes of the two storage tubes of the memory cell and the designed spacing between the two gate electrodes. Exemplarily, the width of the first opening 108 can be 70nm-100nm, for example, 85nm.

[0043] refer to Fig. 9 and Fig.10 As shown, step S3 is executed to form a first sidewall 109 in the first opening 108 . The first sidewall 109 is a ring-shaped structure that covers the sidewall of the first opening 108 .

[0044] In this embodiment, reference Fig. 9 As shown, the first spacer 109 spans across the active region 100 , and two opposite ends (ie, left and right ends) of the first spacer 109 extend beyond the active region 100 and are located on the isolation structures 101 at two sides of the active region 100 .

[0045] Exemplarily, step S3 may specifically include: forming a first spacer material layer on the second hard mask layer 107, the first spacer material layer conformally covering the top surface of the second hard mask layer 107, the side walls and the bottom surface of the first opening 108; using an anisotropic dry etching process to etch away the first spacer material layer on the top surface of the second hard mask layer 107 and part of the first spacer material layer at the bottom of the first opening 108, and retaining the first spacer material layer on the side wall of the first opening 108 as the first spacer 109.

[0046] The material of the first sidewall spacer 109 is different from the material of the second hard mask layer 107 and the first hard mask layer, so that in the process of etching to form the first sidewall spacer 109, the etching speed of the first sidewall material layer is much greater than the etching speed of the second hard mask layer 107 and the first hard mask layer, that is, the first sidewall material layer can be selectively etched, so that a high-precision first sidewall spacer 109 can be formed and the etching damage of the second hard mask layer 107 and the first hard mask layer is small. Exemplarily, the material of the first sidewall spacer 109 includes but is not limited to amorphous silicon.

[0047] refer to Fig.10 As shown, the width D1 of the first spacer 109 can be set according to the gate electrode length of the two storage tubes of the memory cell and the designed spacing between the two gate electrodes. Exemplarily, the width of the first spacer 109 is 25nm-35nm, for example, 30nm.

[0048] refer to Fig.11 and Fig.12 As shown, step S4 is performed to fill the first opening 108 with a third hard mask layer 110 .

[0049] Exemplarily, step S4 may specifically include: forming a third hard mask layer 110 on the substrate, the third hard mask layer 110 covering the second hard mask layer 107 and the first sidewall 109, and filling the first opening 108; removing a portion of the third hard mask layer 110 by a chemical mechanical polishing process or a back etching process, that is, removing the third hard mask layer 110 above the second hard mask layer 107 to expose the top surface of the second hard mask layer 107.

[0050] It should be noted that, in this embodiment, when executing step S4, the height of the storage area of ​​the substrate is different from the height of other areas on its side. When removing part of the third hard mask layer 110, if a chemical mechanical polishing process is used, the structure of other areas will be damaged. Therefore, it is preferred to use an etch-back process to remove part of the third hard mask layer 110. In other embodiments, if there is no large height difference between the various areas of the substrate, a chemical mechanical polishing process can also be selected to remove part of the third hard mask layer 110.

[0051] In this embodiment, the third hard mask layer 110 may not need to fill the first opening 108, that is, even if the central area of ​​the third hard mask layer 110 (that is, the area in the first opening 108 not filled with the first spacer 109) has a small gap (Seam) or pit, it does not affect the third hard mask layer 110 to protect the sidewalls of the first spacer 109 covered by it and the silicon oxynitride layer 106. Exemplarily, the third hard mask layer 110 may be formed by an atomic layer deposition (ALD) process, which can improve the filling quality of the third hard mask layer 110 filling the first opening 108.

[0052] In this embodiment, the material of the third hard mask layer 110 is different from the materials of the first spacer 109, the second hard mask layer 107 and the first hard mask layer, so as to facilitate the subsequent selective etching to remove the second hard mask layer 107 and to facilitate the control of the subsequent formation of the second spacer. Exemplarily, the third hard mask layer 110 includes but is not limited to silicon oxide.

[0053] refer to Fig.13 and Fig.14 As shown, step S5 is performed to remove the second hard mask layer 107 .

[0054] In this embodiment, a wet etching process may be used to remove the second hard mask layer 107. The etching solution used in the wet etching process includes diluted hydrofluoric acid (DHF) and H3PO4, so that the etching rate of the second hard mask layer 107 is much greater than the etching rate of the silicon oxynitride layer 106, the first sidewall spacer 109 of amorphous silicon, and the third hard mask layer 110 of silicon oxide, that is, the second hard mask layer 107 can be selectively etched, and then the second hard mask layer 107 can be completely removed and the etching process is easy to control.

[0055] refer to Fig.15 and Fig.16 As shown, step S6 is executed to form a second sidewall 111 on the outer side of the first sidewall 109 . The second sidewall 111 surrounds and covers the first sidewall 109 .

[0056] Exemplarily, step S6 may include: forming a second spacer material layer on the first hard mask layer, the second spacer material layer covering the first spacer 109, the third hard mask layer 110 and the first hard mask layer; using an anisotropic dry etching process to etch away a portion of the second spacer material layer and stop on the silicon oxynitride layer 106, that is, removing the second spacer material layer above the first spacer 109 and above the third hard mask layer 110, and retaining the second spacer material layer on the side wall of the first spacer away from the third hard mask layer 110 as the second spacer 111.

[0057] like Fig.15 As shown, the second spacer 111 is also a ring-shaped structure, and the second spacer 111 spans across the active area 100 and two opposite ends (i.e. Fig.15 The left and right ends of the active area 100 are located on the isolation structure 101 on both sides of the active area 100.

[0058] It should be noted that the reference Fig.16 As shown, since over-etching is performed when forming the first opening 108 and stops in the silicon oxynitride layer 106 of the first hard mask layer, the bottom surface of the first spacer 109 is slightly lower than the bottom surface of the second spacer 111 .

[0059] In this embodiment, the materials of the first sidewall 109 and the second sidewall 111 can be the same, that is, the materials of the first sidewall 109 and the second sidewall 111 are both amorphous silicon, which facilitates the subsequent simultaneous removal of the first sidewall 109 and the second sidewall 111 and helps to simplify the process steps.

[0060] In this embodiment, the width D2 of the second spacer 111 can be set according to the gate electrode length of the storage tube. Exemplarily, the width of the second spacer 111 is 30nm~40nm, for example, 35nm. The thickness of the second spacer material layer can be set according to the width of the second spacer 111. Exemplarily, the thickness of the second spacer material layer is 300Å~500Å, for example, 400Å; the formation temperature of the second spacer material layer can be below 400°C.

[0061] refer to Fig.17 and Fig.18 As shown, step S7 is performed to remove the third hard mask layer 110 .

[0062] Exemplarily, a wet etching process may be used to remove the third hard mask layer 110. For example, the third hard mask layer 110 of silicon oxide may be removed by using diluted hydrofluoric acid, which can selectively etch silicon oxide and cause little damage to the silicon oxynitride layer 106, the first sidewall 109 of amorphous silicon, and the second sidewall 111, so that the etching of the third hard mask layer 110 is easily controlled.

[0063] refer to Fig.19 and Fig. 20 As shown, a first photoresist mask layer 113 is formed on the first hard mask layer, and the first photoresist mask layer 113 covers a portion of the logic area (corresponding to the gate oxide layer 103) to protect a portion of the gate material layer of the logic area, and the first photoresist mask layer 113 exposes the storage area (corresponding to the charge trap layer 102).

[0064] It should be noted that, in addition to some logic areas, the first photoresist mask layer 113 can also cover other areas that need to be protected. Specifically, the pattern of the first photoresist mask layer 113 can be set according to actual conditions.

[0065] The first photoresist mask layer 113 can be formed by exposure and development processes. The first photoresist mask layer 113 can be made of KrF photoresist, which is made using a 248nm KrF light source and is suitable for line width processes above 0.13μm. Using KrF photoresist helps to form high-precision small-sized graphics.

[0066] refer to Fig. 20As shown, a bottom anti-reflective coating (BARC) 112 may be formed between the first photoresist mask layer 113 and the first hard mask layer. The bottom anti-reflective coating 112 may reduce the reflection of light on the lower surface of the photoresist during the exposure process of the first photoresist mask layer 113, so that most of the exposure energy is absorbed by the photoresist, which helps to improve the graphic accuracy of the first photoresist mask layer 113.

[0067] Next, step S8 is performed to sequentially etch the first hard mask layer and the gate material layer 104 downwards using the first spacer 109 and the second spacer 111 as masks to form a gate ring 104 a.

[0068] Exemplarily, step S8 may include: referring to Fig.19 and Fig. 20 As shown, the first sidewall 109, the second sidewall 111 and the first photoresist mask layer 113 are used as masks to etch down the bottom anti-reflective coating 112 and the silicon oxynitride layer 106 of the first hard mask layer, and a slight over-etching can be performed and stop in the amorphous carbon layer 105 of the first hard mask layer; refer to Fig.21 and Fig. 22 As shown, the amorphous carbon layer 105 is continuously etched downward and stops on the gate material layer 104; Fig.23 and Fig.24 As shown, the gate material layer 104 is continuously etched downward and stops on the charge trap layer 102 and the gate oxide layer 103, and the remaining gate material layer 104 is partially used as a gate ring 104a and partially used as a selection tube gate 104b located on the logic area; Fig.25 and Fig.26 As shown, the charge trap layer 102 and the gate oxide layer 103 are etched downward and stopped on the substrate.

[0069] Since the substrate surface is not flat when the bottom anti-reflection coating 112 is coated, the thickness of the bottom anti-reflection coating 112 may be different between different regions. Therefore, when etching the bottom anti-reflection coating 112, an appropriate proportion of over-etching can be performed and stopped in the silicon oxynitride layer 106, so as to ensure that the bottom anti-reflection coating 112 is etched through.

[0070] After etching the charge trap layer 102 and the gate oxide layer 103, refer to Fig. 27 and Fig.28 As shown, the first spacer 109 , the second spacer 111 , the first photoresist mask layer 113 , the bottom anti-reflective coating layer 112 and the first hard mask layer are removed.

[0071] It should be noted that, in the actual etching process, the mask will damage part of the thickness. Fig. 20 and Fig. 22As shown, after the amorphous carbon layer 105 is etched, the first photoresist mask layer 113 can be etched away; Fig. 22 and Fig.24 As shown, after the etching of the gate material layer 104 is completed, the first sidewall spacer 109, the second sidewall spacer 111 and the bottom anti-reflective coating 112 may be etched away; Fig.24 and Fig.26 As shown, after the etching of the charge trap layer 102 and the gate oxide layer 103 is completed, the silicon oxynitride layer 106 can be etched away; after the etching of the charge trap layer 102 and the gate oxide layer 103 is completed, only the remaining amorphous carbon layer 105 needs to be removed to expose the gate electrode 104c of the storage tube and the gate 104b of the selection tube, but it is not limited to this.

[0072] refer to Fig. 27 As shown, the gate ring 104a is formed to span the active area 100, and the two opposite ends of the gate ring 104a are located on the isolation structure 101 at both sides of the active area 100. The two ends of the selection transistor gate 104b can also slightly exceed the corresponding active area 100.

[0073] In this embodiment, the gate ring 104 a is formed on the storage region.

[0074] It should be noted that the transistor corresponding to the selection tube gate 104 b formed in this embodiment may be a bit line selection tube in a bit line selection circuit, which is used to selectively connect a local bit line and a global bit line, but is not limited thereto.

[0075] refer to Fig.30 As shown, step S9 is performed to etch and remove two opposite ends of the gate ring 104a, so that the gate ring 104a divides the gate electrodes 104c of two storage tubes of the same pair of storage cells.

[0076] Exemplarily, step S9 may include: Fig.29 As shown, a second photoresist mask layer 114 is formed on the substrate, and the second photoresist mask layer 114 has a plurality of second openings 114a, the second openings 114a are located above the isolation structure 101, and the two opposite ends of the gate ring 104a are exposed from the corresponding second openings 114a; Fig.30 As shown, the second photoresist mask layer 114 is used as a mask to etch away two opposite ends of the gate ring 104 a and stop on the isolation structure 101 .

[0077] It should be noted that, in the present embodiment, the two opposite ends of the gate ring 104a are located on the isolation structure 101 on both sides of the active area 100, and the material of the gate ring 104a is different from the material of the isolation structure 101. In this way, when etching away the two opposite ends of the gate ring 104a, the etching can be stopped on the isolation structure 101, and the etching control of the gate ring 104a is more convenient.

[0078] In this embodiment, Fig.30 As shown, the gate electrode 104 c of the storage tube formed by cutting the gate ring 104 a may slightly exceed its corresponding active region 100 .

[0079] In this embodiment, the gate ring 104a can span across an active region 100, so that after etching and removing the two opposite ends of the gate ring 104a, one gate ring 104a forms a gate electrode 104c of two storage tubes of a group of memory cells. In other embodiments, the gate ring 104a can also span across multiple active regions 100. In the step of etching and removing the two opposite ends of the gate ring 104a, the second photoresist mask layer 114 can also expose a portion of the gate ring 104a on the isolation structure between adjacent active regions 100. In this way, when etching the gate ring 104a, a portion of the gate ring 104a on the isolation structure between adjacent active regions 100 can also be removed, so that one gate ring 104a can be divided to form a plurality of gate electrodes 104c of the group of memory cells.

[0080] In this embodiment, reference Fig.30 and Figure 1 The two storage transistors of the same pair of storage cells of the pair structure non-volatile memory are electrically connected through the active region between the gate electrodes 104c of the two storage transistors. Figure 1 and Figure 2 As shown, a column group of memory cells may correspond to a group of bit lines (BL), a group of bit lines includes two bit lines, a first memory tube M1 of the same column group of memory cells is connected to one of the bit lines in the group, and a second memory tube M2 of the same column group of memory cells is connected to the other bit line in the group, but not limited thereto. When performing data operations, one memory tube of the same group of memory cells may be used as a selection tube of another memory tube.

[0081] It should be noted that, precisely because in the present application, the two storage tubes of the same pair of storage cells are electrically connected through the active region between the two gate electrodes 104c, so that on the basis of achieving physical and electrical isolation, the distance between the two gate electrodes 104c of the same pair of storage cells can be reduced as much as possible, so that the distance can be smaller than the resolution of lithography.

[0082] Optionally, after etching and dividing the gate ring 104a to form the gate electrode 104c of the storage tube, an impurity can be injected into the substrate between the two gate electrodes 104c of the same pair of storage cells to form a doped region (not shown in the figure), which can be used to control the current between the two storage tubes of the same pair of storage cells to prevent leakage between the two storage tubes of the same pair of storage cells.

[0083] The preparation method of the paired structure non-volatile memory provided by the present invention has the following advantages: (1) using the first sidewall 109 and the second sidewall 111 as a mask, etching the gate material layer 104 to form a gate ring 104a, and then etching away the two opposite ends of the gate ring 104a, so that the gate ring 104a divides the gate electrodes 104c of the two storage tubes of the same paired storage unit. In this way, the spacing between the gate electrodes of the two storage tubes of the same paired storage unit is not restricted by the resolution capability of photolithography, so that the spacing between the gate electrodes of the two storage tubes of the same paired storage unit is smaller, thereby reducing the area of ​​the paired storage unit of the paired structure non-volatile memory, which helps to reduce the size and cost of the storage chip and improve the cost performance of the storage chip; (2) the first sidewall 109 in the first opening 108 of the second hard mask layer 107 of the present invention is formed by etching the gate material layer 104 to form a gate ring 104a, and then etching and removing the two opposite ends of the gate ring 104a, so that the gate ring 104a divides the gate electrodes 104c of the two storage tubes of the same paired storage unit. 109, then fill the third hard mask layer 110 in the first opening 108, remove the second hard mask layer 107, then form the second side wall 111 on the outer side of the first side wall 109 and remove the third hard mask layer 110, then use the first side wall 109 and the second side wall 111 as masks to sequentially etch the first hard mask layer and the gate material layer 104 downward to form a gate ring 104a, so that the gate ring 104a can be defined by a one-step self-aligned etching, that is, the spacing between the gate electrodes of the two storage tubes of the same pair of storage cells and the length of the storage tube gate electrode are defined by a one-step self-aligned etching, the process is relatively simple, and it is helpful to improve the size consistency of the two gate electrodes of the pair of storage cells, improve the performance consistency of the two storage tubes of the pair of storage cells, and thus improve the performance of the pair structure non-volatile memory.

[0084] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a pair structure non-volatile memory, wherein the pair storage unit of the pair structure non-volatile memory comprises two electrically connected storage tubes, characterized in that: The preparation method comprises: Providing a substrate, on which a gate material layer, a first hard mask layer, and a second hard mask layer are sequentially stacked from bottom to top are formed; forming a first opening in the second hard mask layer; forming a first side wall in the first opening, wherein the first side wall is an annular structure covering a side wall of the first opening; filling a third hard mask layer in the first opening; removing the second hard mask layer; A second side wall is formed on the outer side of the first side wall, and the second side wall surrounds and covers the first side wall; removing the third hard mask layer; Using the first sidewall spacer and the second sidewall spacer as masks, sequentially etching the first hard mask layer and the gate material layer downwards to form a gate ring; Two opposite ends of the gate ring are removed by etching, so that the gate ring divides the gate electrodes of two storage tubes of the same pair of storage cells.

2. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: In the step of providing a substrate, the substrate has an isolation structure and an active area defined by the isolation structure; In the step of forming the gate ring, the gate ring spans across the active area, and two opposite ends of the gate ring are located on the isolation structures at two sides of the active area.

3. The method for preparing the pair structure non-volatile memory according to claim 2, characterized in that: The first sidewall spacer spans across the active region, and two opposite ends of the first sidewall spacer exceed the active region and are located on the isolation structures at two sides of the active region.

4. The method for preparing the pair structure non-volatile memory according to claim 2, characterized in that: The method of etching and removing two opposite ends of the gate ring comprises: Forming a second photoresist mask layer on the substrate, wherein the second photoresist mask layer has a plurality of second openings, the second openings are located above the isolation structure, and two opposite ends of the gate ring are exposed from the corresponding second openings; Using the second photoresist mask layer as a mask, etching is performed to remove two opposite ends of the gate ring and stop at the isolation structure.

5. The method for preparing the pair structure non-volatile memory according to claim 2, characterized in that: The two storage tubes of the same pair of storage cells are electrically connected via an active region between gate electrodes of the two storage tubes.

6. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: The method of filling the first opening with a third hard mask layer comprises: forming a third hard mask layer on the substrate, wherein the third hard mask layer covers the second hard mask layer and the first sidewall spacer and fills the first opening; The third hard mask layer above the second hard mask layer is removed by a chemical mechanical polishing process or an etch-back process.

7. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: The first spacer and the second spacer are made of the same material; the first spacer, the first hard mask layer, the second hard mask layer and the third hard mask layer are made of different materials.

8. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: In the step of providing a substrate, the substrate has a storage area and a logic area, a charge trap layer is formed on the storage area, a gate oxide layer is formed on the logic area, and the gate material layer covers the charge trap layer and the gate oxide layer; the gate ring formed subsequently is located on the storage area.

9. The method for preparing the pair structure non-volatile memory according to claim 8, characterized in that: After removing the third hard mask layer and before sequentially etching downward the first hard mask layer and the gate material layer, the preparation method further comprises: forming a first photoresist mask layer on the first hard mask layer, wherein the first photoresist mask layer covers a portion of the logic area and exposes the storage area; The step of sequentially etching downward the first hard mask layer and the gate material layer comprises: using the first side wall, the second side wall and the first photoresist mask layer together as a mask, etching downward the first hard mask layer, the gate material layer, the charge trap layer and the gate oxide layer and stopping on the substrate, retaining part of the gate material layer as the gate ring and part as the selection tube gate located on the logic area.

10. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: After sequentially etching downward the first hard mask layer and the gate material layer and before etching away two opposite ends of the gate ring, the preparation method further includes: removing the first sidewall spacer, the second sidewall spacer and the first hard mask layer.

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