Method for producing power semiconductor structural element having plurality of fins and power semiconductor structural element produced thereby

Abstract

The invention relates to a method for producing a power semiconductor component having a plurality of fins, comprising the following steps: producing a plurality of mesas starting from a front side of a semiconductor substrate into a drift layer of the semiconductor substrate by means of etching, the mesas having an upper side corresponding to a front side region of the semiconductor substrate and being arranged between a first trench and a second trench, the first trench has a first trench bottom surface and the second trench has a second trench bottom surface, the mesa has a first side corresponding to a first trench side of the first trench and a second side corresponding to a second trench side of the second trench, the mesa having a width greater than 500 nm, a mask layer is applied to the upper side, the first side, the second side, the first trench bottom surface and the second trench bottom surface, regionally removing the mask layer creates a structured mask to create a bare surface including the first side, the regional ground side, the first trench bottom surface, processing the bare surface to create a fin, removing the structured mask, and removing the fin from the structured mask. And completing the power semiconductor structure element.

Description

Technical Field

[0001] The invention relates to a method for producing a power semiconductor component having a plurality of fins and a power semiconductor component having a plurality of fins. Background Art

[0002] Power semiconductor components with a fin structure and a wide bandgap substrate provide high channel density and minimal on-resistance in power electronics. The fins have a small width of less than 500 nm. The fins are produced by narrowing the mesa on both sides.

[0003] A disadvantage of this is that the surface quality of the fin side walls is negatively affected. In the case of SiC substrates, carbon clusters can form on the fin side walls, which leads to channel mobility. , since the charge carriers have increased scattering on these defects.

[0004] Another disadvantage is that the transconductance is very steep, so that problems can occur during dynamic operation of the power semiconductor components. For example, parasitic switching of transistors can occur in a half-bridge configuration.

[0005] The object of the present invention is to overcome these disadvantages. Summary of the invention

[0006] The method for producing a power semiconductor component with a plurality of fins according to the invention comprises: generating a plurality of terraces starting from the front side of a semiconductor substrate into a drift layer of the semiconductor substrate by means of etching, wherein each terrace has an upper side, which corresponds to a region of the front side of the semiconductor substrate, and each terrace is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface, wherein each terrace has a first side surface and a second side surface, wherein the first side surface corresponds to a first trench side surface of the first trench and the second side surface corresponds to a second trench side surface of the second trench, wherein each terrace has a width greater than 500 nm, and applying a mask layer to the upper side, the first side surface, the second side surface, the first trench bottom surface and the second trench bottom surface. In addition, the method comprises: generating a structured mask by removing the mask layer regionally, so that an exposed surface is generated, wherein the exposed surface comprises the first side surface, the upper side regionally and the first trench bottom surface, and generating the fins by machining the exposed surface. Furthermore, the method comprises removing the structured mask and completing the power semiconductor component.

[0007] This has the advantage that the fin is narrowed only on one side. As a result, the interface structure of the first side of the fin is different from the interface structure of the second side of the fin, so that the channel density is high and the transconductance is flat.

[0008] In one configuration, the semiconductor substrate includes SiC.

[0009] In another configuration, the mask layer includes SiN.

[0010] This has the advantage that SiN has a high resistance to oxidation processes and can therefore be used as a masking portion in order to inhibit thermal growth of an oxide layer on a portion of the semiconductor surface.

[0011] In one embodiment, the fins are produced by means of thermal oxidation.

[0012] In another configuration, the semiconductor substrate includes GaN.

[0013] In one configuration, the masking layer includes Ti or TiO 2 .

[0014] In another configuration, the fins are produced with the aid of TMAH.

[0015] A power semiconductor component according to the invention having a plurality of fins is produced by means of the method according to the invention.

[0016] In one embodiment, the power semiconductor component is a FinFET.

[0017] In another embodiment, the power semiconductor component is a FinMOSFET.

[0018] Further advantages emerge from the following description of exemplary embodiments and from the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention is described below based on preferred embodiments and the accompanying drawings. The drawings show:

[0020] Figure 1 A method according to the invention for producing a power semiconductor component having a plurality of fins is shown.

[0021] Figure 2a shows the initial product of the method according to the invention,

[0022] Figure 2b-2e shows intermediate products of the individual method steps of the method according to the invention,

[0023] Figure 3 A power semiconductor component produced according to the invention is shown. DETAILED DESCRIPTION

[0024] Figure 1 A method 100 for manufacturing a power semiconductor structure element with multiple fins according to the present invention is shown. The method 100 starts from step 110, in which a plurality of mesas (Mesa) in the drift layer of the semiconductor substrate starting from the front side of the semiconductor substrate are generated by etching. In this context, the term mesa is understood as a convex portion with a flat surface and steep flanks. Each mesa has an upper side, which corresponds to a region of the front side of the semiconductor substrate or coincides with the front side. Each mesa is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface. Each mesa has a first side and a second side, wherein the first side corresponds to the first trench side of the first trench and the second side corresponds to the second trench side of the second trench. Each mesa has a width greater than 500nm. In the next step 120, a mask layer is applied to the upper side, the first side, the second side, the first trench bottom surface, and the second trench bottom surface. In the next step 130, a structured mask is generated by removing the mask layer regionally. Here, an exposed surface is produced, which comprises the first side surface, the top side in a regional manner and the first trench bottom surface. In a subsequent step 140, a fin is produced by machining the exposed surface. In a subsequent step 150, the structured mask is removed and then in a step 160, the power semiconductor component is completed. Here, step 160 comprises a plurality of method steps from the prior art. In other words, the terrace is narrowed on one side, whereby a fin with a different interface structure is produced on the sidewall.

[0025] The semiconductor substrate includes, for example, SiC or GaN. If the semiconductor substrate is SiC, SiN is used as a mask layer, for example. Then, in step 140, thermal oxidation is used, for example, to produce fins. In the case of GaN, Ti or TiO2 is used as a mask layer, for example. Then, in step 140, TMAH is used, for example, to produce fins.

[0026] Figure 2a Show Figure 1 The initial product 200 according to the method 100 of the present invention is a FinMOSFET. The power semiconductor structure element manufactured based on the initial product is a FinMOSFET. The initial product 200 includes a semiconductor substrate 201, especially an n-conducting semiconductor substrate. A drift layer 202 is arranged on the semiconductor substrate 201. A channel region 204, especially a p-channel, is arranged on the drift layer 202. A source region layer 205 is arranged on the channel region 204. The semiconductor substrate 201 includes, for example, SiC or GaN.

[0027] Figure 2b Show Figure 1The intermediate product 210 of the method step 110 in FIG. It should be noted that like reference numerals describe like features. Figure 2b 2 shows two mesa structures 203 which are separated from one another by a second trench 207. The first trench 206 can be seen in the edge region.

[0028] Figure 2c Show Figure 1 The intermediate product 230 of the method step 130. Figure 2a and 2b In addition to the features described, a structured mask 211 is shown. Here, the structured mask 211 regionally covers the upper side of the mesa 203 and the second trench bottom surface of the second trench 207 and the second side surface of the mesa. In other words, the first side surface, the upper side region and the first trench bottom surface are exposed and form an exposed surface.

[0029] Figure 2d Show Figure 1 The intermediate product 240 of the method step 140 in the embodiment. The mesa structure 230 is narrowed into the fin 212. Here, the sidewalls of the fin 212, i.e., the second side, are protected respectively by the structured mask 211. This means that, in order to manufacture the fin 212, the final width of the fin 212 is produced only by the side of the mesa 203. In the example shown here, the narrowing of the fin 212 on the left side is achieved from the left side and the narrowing of the fin 212 on the right side is achieved from the right side. In other words, the sidewalls of the fin 212 located on the inner side remain unchanged during the narrowing process. Since the process for narrowing is not selective, the bottom surface of the groove adjacent to the fin is also affected. This means that the first groove 206 can be deeper than the second groove 207. In other embodiments not shown, the same sidewalls of each mesa can also be protected respectively by a structured mask, i.e., the left side of the mesa is always protected. In other embodiments not shown, the complete mesa can be protected by a structured mask before narrowing. Thus, for example, different fin widths can be achieved.

[0030] Figure 2e An intermediate product 250 of method step 150 is shown after the structured mask has been removed.

[0031] Figure 3A power semiconductor structure element 300 manufactured according to the present invention is shown. The power semiconductor structure element 300 shows a FinMOSFET. The FinMOSFET includes a drain electrode 309. A semiconductor substrate 301, such as SiC or GaN, is arranged on the drain electrode 309. A drift layer 302 is arranged on the semiconductor substrate 301. A channel region 304, preferably p-doped, is arranged on the drift layer 302. A source region 305 is arranged on the channel region 304. A source electrode 308 is arranged on the source region 305. The fin 312 extends from the drift layer 302 to the source electrode 308. The gate electrode 307 is electrically separated from the fin 312 by a gate dielectric 313.

[0032] In another embodiment, the manufactured power semiconductor structure element can be a FinFET. Here, the FinFET does not have Figure 3 Channel region 304 is shown.

[0033] FinMOSFETs or FinFETs produced according to the invention are used, for example, in electric drive trains of electric vehicles or hybrid vehicles and in inverters for domestic appliances.

Claims

1. A method (100) for producing a power semiconductor component having a plurality of fins, the method comprising the following steps: A plurality of terraces are produced (110) starting from the front side of a semiconductor substrate into a drift layer of the semiconductor substrate by etching, wherein: Each mesa has an upper side, the upper side corresponding to a region of the front side of the semiconductor substrate, and each mesa is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface, wherein each mesa has a first side surface and a second side surface, wherein the first side surface corresponds to a first trench side surface of the first trench and the second side surface corresponds to a second trench side surface of the second trench, wherein each mesa has a width greater than 500 nm, applying (120) a masking layer to the upper side, the first side, the second side, the first trench bottom surface, and the second trench bottom surface, A structured mask is produced (130) by removing the mask layer in regions, so that an exposed surface is produced, wherein the exposed surface includes the first side surface, in regions the top side and the first trench bottom surface, Producing (140) fins by machining the exposed surface, removing (150) the structured mask, The power semiconductor structure element is completed (160).

2. The method (100) according to claim 1, characterized in that: The semiconductor substrate includes SiC.

3. The method (100) according to any one of claims 1 or 2, characterized in that: The mask layer includes SiN.

4. The method (100) according to any one of the preceding claims, characterized in that The fins are produced by means of thermal oxidation.

5. The method (100) according to claim 1, characterized in that: The semiconductor substrate includes GaN.

6. The method (100) according to any one of claims 1 or 5, characterized in that: The mask layer includes Ti or TiO2.

7. The method (100) according to any one of claims 1 or 5 and 6, characterized in that: The fins were produced with the aid of TMAH.

8. A power semiconductor component (200, 300) having a plurality of fins, the power semiconductor component being produced by means of a method according to any of the preceding claims.

9. The power semiconductor component (200) according to claim 8, wherein: The power semiconductor component is a FinFET.

10. The power semiconductor component (200, 300) according to claim 8, characterized in that The power semiconductor component is a FinMOSFET.

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