Super junction semiconductor structure and preparation method thereof

Abstract

The invention provides a super-junction semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method comprises the following steps: providing a substrate structure; a voltage-withstanding region is arranged on one side of the substrate structure, and the voltage-withstanding region comprises a first voltage-withstanding region and a second voltage-withstanding region. A third voltage-withstanding area is arranged at the top of each second voltage-withstanding area, and a fourth voltage-withstanding area is arranged at the top of each first voltage-withstanding area; wherein the third voltage-withstanding region and the second voltage-withstanding region have the same conductive type, and the first voltage-withstanding region and the fourth voltage-withstanding region have the same conductive type. A groove-type gate structure and a second base region are arranged on one side, far away from the substrate structure, of each first voltage-resistant region; a first base region is arranged on the side, away from the substrate structure, of each second base region; the second base region and the first base region form a boss structure. A cut-off layer is arranged on one side, far away from the substrate structure, of each second voltage-withstanding region; a preset height difference exists between the cut-off layer and the boss structure. According to the invention, the reverse recovery oscillation can be improved on the premise of not influencing the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a superjunction semiconductor structure and a method for preparing the same. Background Art

[0002] Superjunction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device is an extremely important power switching device, which has the advantages of low on-resistance, low switching loss, etc., and can be applied to various full-bridge and / or half-bridge circuits.

[0003] The superjunction MOSFET device adopts a superjunction structure in the withstand voltage region, that is, the n-column region and the p-column region are arranged alternately in the horizontal direction in the withstand voltage region. When the superjunction structure is subjected to reverse bias, a lateral electric field will be generated at the PN junction between the n-column region and the p-column region. Before being broken down, the entire n-column region and the p-column region of the device are almost completely exhausted in the horizontal direction, and the withstand voltage of the above device will no longer depend on the doping concentration of the drift region. This reduces the contribution of ionized impurities in the body to the longitudinal electric field, thereby increasing the breakdown voltage of the device without affecting the device's specific on-resistance.

[0004] However, the superjunction structure greatly increases the PN junction area of ​​the body diode, causing more carriers to be stored inside the device during forward injection, making the reverse recovery charge (Q rr ) increases significantly. In addition, since the n-column region and the p-column region will be quickly depleted during the reverse recovery process, the reverse recovery of the body diode becomes hard, and the softness factor (S) is too small, which further leads to voltage overshoot and oscillation in the reverse recovery process, thus causing device failure.

[0005] Based on this, there is an urgent need for a super junction MOSFET device that can improve the number of unbalanced carriers in the body diode without affecting the breakdown voltage of the device, while improving the softness of the body diode. Summary of the invention

[0006] In view of this, the object of the present invention is to provide a superjunction semiconductor structure and a preparation method thereof, which can reduce the number of unbalanced carriers in the body diode without affecting the breakdown voltage of the device, while increasing the softness of the body diode, thereby improving reverse recovery oscillation.

[0007] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0008] In a first aspect, the present invention provides a method for preparing a superjunction semiconductor, comprising the following steps:

[0009] providing a substrate structure;

[0010] A voltage-resistant region is set based on one side of the substrate structure; the voltage-resistant region includes a first voltage-resistant region and a second voltage-resistant region that are alternately arranged; wherein the first voltage-resistant region and the second voltage-resistant region have different conductivity types;

[0011] A third voltage-resistant region is arranged on the top of each second voltage-resistant region; wherein the third voltage-resistant region has the same conductivity type as the second voltage-resistant region;

[0012] A fourth voltage-resistant region is arranged on the top of each first voltage-resistant region; wherein the first voltage-resistant region and the fourth voltage-resistant region have the same conductivity type;

[0013] A trench gate structure and a second base region are arranged on a side of each first voltage-resistant region away from the substrate structure; wherein the second base region is arranged on both sides of the trench gate structure;

[0014] A first base region is arranged on a side of each second base region away from the substrate structure; wherein the second base region and the first base region form a boss structure, and an upper surface of the boss structure is flush with an upper surface of the groove-type gate structure;

[0015] A cut-off layer is provided on a side of each second voltage-resistant region away from the substrate structure; wherein a preset height difference exists between the cut-off layer and the boss structure;

[0016] The doping concentration of the third voltage-sustaining region is lower than the doping concentration of the second voltage-sustaining region;

[0017] The doping concentration of the fourth voltage-sustaining region is lower than the doping concentration of the first voltage-sustaining region.

[0018] Optionally, the doping concentration of the first voltage-sustaining region is equal to the doping concentration of the second voltage-sustaining region;

[0019] The doping concentration of the fourth voltage-sustaining region is equal to the doping concentration of the third voltage-sustaining region.

[0020] Optionally, the thickness of the first pressure-resistant region is equal to the thickness of the second pressure-resistant region;

[0021] The thickness of the fourth voltage-sustaining region is equal to the thickness of the third voltage-sustaining region.

[0022] Optionally, a source Schottky contact conductor is disposed on a side of the cut-off layer away from the substrate structure.

[0023] Optionally, lateral surfaces and longitudinal surfaces of the first base region and the second base region are all covered by a source ohmic contact conductor.

[0024] Optionally, the doping concentration of the cutoff layer is lower than the doping concentration of the second base region.

[0025] Optionally, the doping concentration of the cutoff layer is higher than the doping concentration of the second voltage-sustaining region.

[0026] Optionally, a ratio of doping concentrations of the second voltage-resistant region to that of the third voltage-resistant region is greater than or equal to 3.

[0027] Optionally, a ratio of doping concentrations of the first voltage-resistant region to that of the fourth voltage-resistant region is greater than or equal to 3.

[0028] In a second aspect, the present invention provides a superjunction semiconductor structure, comprising:

[0029] Substrate structure;

[0030] A voltage-resistant region located on one side of the substrate structure; the voltage-resistant region comprises a first voltage-resistant region and a second voltage-resistant region which are alternately arranged; wherein the first voltage-resistant region and the second voltage-resistant region have different conductivity types;

[0031] a third voltage-sustaining region located on top of each second voltage-sustaining region; wherein the third voltage-sustaining region has the same conductivity type as the second voltage-sustaining region;

[0032] a fourth voltage-sustaining region located on top of each first voltage-sustaining region; wherein the first voltage-sustaining region and the fourth voltage-sustaining region have the same conductivity type;

[0033] A trench gate structure and a second base region located on a side of each first voltage-resistant region away from the substrate structure; wherein the second base region is arranged on both sides of the trench gate structure;

[0034] A first base region located on a side of each second base region away from the substrate structure; wherein the second base region and the first base region form a boss structure, and an upper surface of the boss structure is flush with an upper surface of the trench-type gate structure;

[0035] A cut-off layer located at a side of each second voltage-resistant region away from the substrate structure; wherein a preset height difference exists between the cut-off layer and the boss structure;

[0036] Among them, the doping concentration of the third voltage-resistant region is lower than the doping concentration of the second voltage-resistant region; and the doping concentration of the fourth voltage-resistant region is lower than the doping concentration of the first voltage-resistant region.

[0037] A superjunction semiconductor structure and a method for preparing the same provided by an embodiment of the present invention have the following beneficial effects:

[0038] The superjunction semiconductor preparation method of the present invention comprises the following steps: providing a substrate structure; setting a voltage-resistant region based on one side of the substrate structure, the voltage-resistant region comprising a first voltage-resistant region and a second voltage-resistant region. Subsequently, a third voltage-resistant region is set on the top of each second voltage-resistant region, and a fourth voltage-resistant region is set on the top of each first voltage-resistant region; wherein the third voltage-resistant region has the same conductivity type as the second voltage-resistant region, and the first voltage-resistant region has the same conductivity type as the fourth voltage-resistant region. A groove-type gate structure and a second base region are set based on the side of each first voltage-resistant region away from the substrate structure; the second base region is set on both sides of the groove-type gate structure. A first base region is set based on the side of each second base region away from the substrate structure; wherein the second base region and the first base region form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the groove-type gate structure. A cut-off layer is set based on the side of each second voltage-resistant region away from the substrate structure; wherein there is a preset height difference between the cut-off layer and the boss structure. It is possible to reduce the number of unbalanced carriers in the body diode without affecting the breakdown voltage of the device, while increasing the softness of the body diode, thereby improving the reverse recovery oscillation.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A schematic flow chart of a method for preparing a superjunction semiconductor provided by the present invention is shown;

[0042] Figure 2 A schematic structural diagram of a superjunction semiconductor structure provided by the present invention is shown;

[0043] Figure 3 A schematic diagram of a super substrate structure in the present invention is shown;

[0044] Figure 4 A schematic diagram showing the first epitaxial layer arrangement area and the corresponding ion implantation position in the present invention;

[0045] Figure 5 A schematic diagram showing the second epitaxial layer arrangement area and the corresponding ion implantation position in the present invention;

[0046] Figure 6 A schematic diagram showing the third epitaxial layer arrangement area and the corresponding ion implantation position in the present invention;

[0047] Figure 7 A schematic diagram showing the fourth to sixth epitaxial layer arrangement areas and corresponding ion implantation positions in the present invention;

[0048] Figure 8 A schematic diagram showing a super junction withstand voltage structure formed by thermal diffusion of the first to sixth epitaxial layers in the present invention;

[0049] Fig. 9 A schematic diagram showing the arrangement area of ​​the trench gate structure in the present invention is shown;

[0050] Fig.10 A schematic diagram showing the second base region arrangement area in the present invention is shown;

[0051] Fig.11 A schematic diagram showing the arrangement area of ​​the first base region and the source region in the present invention is shown;

[0052] Fig.12 A schematic diagram showing etching regions of the first base region and the second base region in the present invention is shown;

[0053] Fig.13 A schematic diagram showing a comparison of the breakdown voltage of the present invention and the conventional super junction MOSFET of the prior art is shown;

[0054] Fig.14 A schematic diagram showing a comparison of reverse recovery current waveforms of the present invention and conventional super junction MOSFETs in the prior art is shown.

[0055] Icon: 1-drain conductor; 2-gate conductor; 3-source ohmic contact conductor; 4-source Schottky contact conductor; 10-substrate; 11-high-dose ion implantation source of the first conductivity type; 12-low-dose ion implantation source of the first conductivity type; 20-auxiliary layer; 21-high-dose ion implantation source of the second conductivity type; 22-low-dose ion implantation source of the second conductivity type; 30-first voltage-resistant region; 31-second voltage-resistant region; 32-third voltage-resistant region; 33-fourth voltage-resistant region; 40-source region; 41-first base region; 42-second base region; 43-stop layer; 50-trench-type gate structure; 51-conductive polysilicon; 52-gate oxide layer; 201-first epitaxial layer; 202-second epitaxial layer; 203-third epitaxial layer; 204-fourth epitaxial layer; 205-fifth epitaxial layer; 206-sixth epitaxial layer. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0058] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0059] For ease of understanding, some structural names in the present invention are explained below.

[0060] Substrate: A clean single crystal wafer with specific crystal planes and appropriate electrical, optical and mechanical properties for growing epitaxial layers.

[0061] Auxiliary layer: in the present invention, refers to the auxiliary layer of the first conductivity type, which is used to withstand an external voltage not greater than 20% when the device is in a blocking state.

[0062] Doping concentration: refers to the concentration of dopants added to semiconductor materials. Dopants refer to the addition of a small amount of impurities to semiconductor materials to change the electrical properties of the semiconductor. Doping concentration is usually expressed in units of / cm 3 When the doping concentration is low, the conductivity of the semiconductor is poor. When the doping concentration increases, the conductivity of the semiconductor will gradually increase.

[0063] Ohmic contact: When metal and semiconductor materials are in contact, there is a pure resistance at the contact point, and the smaller the resistance, the better, so that when the component is operating, most of the voltage drop is in the active region rather than on the contact surface. Therefore, its IV characteristic is a linear relationship, the larger the slope, the smaller the contact resistance, and the size of the contact resistance directly affects the performance indicators of the device.

[0064] Source ohmic contact conductor: When metal and semiconductor materials are in contact, the metal conductor that forms an ohmic contact and serves as the source is called a source ohmic contact conductor.

[0065] Schottky contact: When metal and semiconductor materials come into contact, the energy band of the semiconductor bends at the interface, forming a Schottky barrier. The existence of the barrier leads to a large interface resistance.

[0066] Source Schottky contact conductor: When metal and semiconductor materials are in contact, a Schottky contact can be formed and the metal conductor that serves as the source is called a source Schottky contact conductor.

[0067] Source region: In the basic structure of the superjunction semiconductor structure, two regions of the second conductivity type are made on the semiconductor material of the first conductivity type, one of which is called the source region of the MOSFET and the other is called the drain region of the MOSFET.

[0068] Base region: Two PN junctions very close to each other are made on a semiconductor substrate. The two PN junctions divide the entire semiconductor into three parts. The two side parts are the emitter region and the collector region, and the middle part is the base region.

[0069] As described in the background technology, the n-column region and the p-column region of the super junction structure in the prior art are alternately arranged in the lateral direction, which greatly increases the PN junction area of ​​the body diode, causing more carriers to be stored inside the device during forward injection, making the reverse recovery charge (Q rr ) is greatly increased. In addition, the n-column region and the p-column region will be quickly depleted during the reverse recovery process, making the reverse recovery of the body diode hard and the softness factor (S) too small, which will further lead to voltage overshoot and oscillation during the reverse recovery process, thus causing device failure. The poor reverse recovery performance of the body diode is detrimental to device reliability and anti-EMI (electromagnetic interference) performance.

[0070] Based on this, a superjunction semiconductor structure and a preparation method thereof are provided, which can improve the number of unbalanced carriers in the body diode without affecting the breakdown voltage of the device, and at the same time improve the softness of the body diode.

[0071] The following is an exemplary description of the superjunction semiconductor preparation method provided in the present application:

[0072] As an optional implementation, please refer to Figure 1 , Figure 1 A flow chart showing a method for preparing a superjunction semiconductor is provided; the method comprises the following steps:

[0073] S100, providing a substrate structure.

[0074] S200, setting a voltage-resistant region based on one side of the substrate structure; the voltage-resistant region includes a first voltage-resistant region and a second voltage-resistant region which are alternately arranged.

[0075] The first voltage-sustaining region and the second voltage-sustaining region have different conductivity types.

[0076] S300 , setting a third voltage-resistant region based on the top of each second voltage-resistant region.

[0077] The third voltage-sustaining region has the same conductivity type as the second voltage-sustaining region.

[0078] S400 , setting a fourth voltage-resistant region based on the top of each first voltage-resistant region.

[0079] The first voltage-sustaining region and the fourth voltage-sustaining region have the same conductivity type.

[0080] S500 , a trench-type gate structure and a second base region are provided based on a side of each first voltage-resistant region away from the substrate structure.

[0081] Wherein, the second base region is arranged on both sides of the trench-type gate structure.

[0082] S600 , providing a first base region based on a side of each second base region away from the substrate structure.

[0083] The second base region and the first base region form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the groove-type gate structure.

[0084] S700 , providing a cutoff layer based on a side of each second voltage-resistant region away from the substrate structure.

[0085] There is a preset height difference between the cut-off layer and the boss structure.

[0086] The doping concentration of the third voltage-resistant region is lower than that of the second voltage-resistant region; and the doping concentration of the fourth voltage-resistant region is lower than that of the first voltage-resistant region.

[0087] Based on the above preparation method, please refer to Figure 2 , Figure 2A schematic diagram of a superjunction semiconductor structure is shown, the superjunction semiconductor structure comprising: a substrate structure; a voltage-resistant region located on one side of the substrate structure; the voltage-resistant region comprises first voltage-resistant regions 30 and second voltage-resistant regions 31 arranged alternately; wherein the first voltage-resistant regions 30 and the second voltage-resistant regions 31 have different conductivity types; a third voltage-resistant region 32 located on top of each second voltage-resistant region 31; wherein the third voltage-resistant region 32 and the second voltage-resistant region 31 have the same conductivity type; a fourth voltage-resistant region 33 located on top of each first voltage-resistant region 30; wherein the first voltage-resistant region 30 and the fourth voltage-resistant region 33 The conductive type is the same; a groove-type gate structure 50 and a second base region 42 located on the side of each first voltage-resistant region 30 away from the substrate structure; wherein the second base region 42 is arranged on both sides of the groove-type gate structure 50; a first base region 41 located on the side of each second base region 42 away from the substrate structure; wherein the second base region 42 and the first base region 41 form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the groove-type gate structure 50; a cut-off layer 43 located on the side of each second voltage-resistant region 31 away from the substrate structure; wherein there is a preset height difference between the cut-off layer 43 and the boss structure.

[0088] Among them, the first voltage-resistant region 30 and the second voltage-resistant region 31 are arranged at intervals on the substrate structure, and the conductivity types between the first voltage-resistant region 30 and the second voltage-resistant region 31 are different, so as to prepare a basic super junction structure. On this basis, a fourth voltage-resistant region 33 is arranged on the top of each first voltage-resistant region 30, and a third voltage-resistant region 32 is arranged on the top of each second voltage-resistant region 31, wherein the first voltage-resistant region 30 and the fourth voltage-resistant region 33 have the same conductivity type, and the third voltage-resistant region 32 and the second voltage-resistant region 31 have the same conductivity type. The conductivity type of the first voltage-resistant region 30 is the first conductivity type, and the conductivity type of the second voltage-resistant region 31 is the second conductivity type. At this time, the first voltage-resistant region 30 and the fourth voltage-resistant region 33 constitute a voltage-resistant region of the first conductivity type; the third voltage-resistant region 32 and the second voltage-resistant region 31 constitute a voltage-resistant region of the second conductivity type.

[0089] It should be noted that in order to improve the reverse recovery softness and suppress reverse recovery oscillation, the doping concentration of the third voltage-resistant region in this embodiment is lower than the doping concentration of the second voltage-resistant region; the doping concentration of the fourth voltage-resistant region is lower than the doping concentration of the first voltage-resistant region. Based on this, the overall equivalent resistance of the third voltage-resistant region and the second voltage-resistant region can be increased, and then during the reverse recovery process of the body diode, the resistance on the hole extraction path during the reverse recovery process is increased, thereby slowing down the hole extraction speed during the reverse recovery process.

[0090] At the same time, since the structure of the first base region and the second base region is improved by the arrangement of the third voltage-resistant region and the fourth voltage-resistant region, the superjunction voltage-resistant structure can maintain the overall charge balance and the local charge balance, thereby ensuring that the breakdown voltage of the superjunction voltage-resistant structure is not affected by the doping concentration of the first voltage-resistant region and the second voltage-resistant region, the third voltage-resistant region and the fourth voltage-resistant region. That is, taking the second conductive type voltage-resistant region composed of the third voltage-resistant region 32 and the second voltage-resistant region 31 as an example, in this embodiment, the proportion of the number of layers of the third voltage-resistant region 32 to the number of layers of the second voltage-resistant region 31 (that is, the depth proportion of the two), as well as the proportion of the concentration of the two, will not affect the breakdown voltage of the device.

[0091] In this embodiment, the substrate structure at least includes a substrate 10 and an auxiliary layer 20 , wherein the substrate 10 may be disposed on one side of the drain conductor 1 , wherein the auxiliary layer 20 is disposed on a side of the substrate 10 away from the drain conductor 1 .

[0092] In the meantime, please continue to refer to Figure 2 When preparing the second base region 42 and the first base region 41, a boss structure having a certain height difference with the cut-off layer 43 is formed by the second base region 42, the first base region 41 and the groove-type gate structure 50, so that a groove structure is formed in the top area of ​​the second voltage-resistant region 31.

[0093] The present invention improves the structures of the first voltage-resistant region 30, the second voltage-resistant region 31, the first base region 41, and the second base region 42, and can reduce the hole injection efficiency on the source side when the semiconductor device (hereinafter referred to as the device) corresponding to the superjunction semiconductor structure is in a reverse conduction state, thereby reducing the reverse recovery charge in the reverse recovery stage. In addition, during the reverse recovery process of the body diode, the resistance on the hole extraction path during the reverse recovery process can be increased, and the hole extraction speed during the reverse recovery process can be slowed down, thereby improving the reverse recovery softness and suppressing the reverse recovery oscillation.

[0094] In this embodiment, when the first conductivity type is n-type doping, the second conductivity type is p-type doping. When the first conductivity type is p-type doping, the second conductivity type is n-type doping.

[0095] Please refer to Figure 3 In this embodiment, a substrate structure is provided in S100, which includes a substrate 10 and an auxiliary layer 20 arranged on one side of the substrate 10, wherein the auxiliary layer 20 can withstand an external voltage not greater than 20% in the device blocking state, and in a possible implementation method, the auxiliary layer 20 is of the first conductive type.

[0096] In this embodiment, the superjunction withstand voltage structure (i.e., the withstand voltage structure formed by thermal diffusion of the first withstand voltage region 30, the second withstand voltage region 31, the third withstand voltage region 32, and the fourth withstand voltage region 33) is formed by multiple epitaxial growth techniques and ion implantation techniques, that is, multiple epitaxial layers are generated on the basis of the substrate structure, and then different doses of ion implantation sources are implanted in each epitaxial layer, and finally all epitaxial layers are thermally diffused. When six epitaxial layers are included, please Figure 3 Based on the reference Figure 4 , Figure 5 , Figure 6 as well as Figure 7 ,in, Figure 4 A schematic diagram showing the first epitaxial layer arrangement area and the corresponding ion implantation position in the voltage-resistant structure of the present invention; Figure 5 A schematic diagram showing the second epitaxial layer arrangement area and the corresponding ion implantation position in the voltage-resistant structure of the present invention; Figure 6 A schematic diagram showing the third epitaxial layer arrangement area and the corresponding ion implantation position in the voltage-resistant structure of the present invention; Figure 7 A schematic diagram showing the arrangement area of ​​the fourth epitaxial layer to the sixth epitaxial layer and the corresponding ion implantation positions in the voltage-resistant structure of the present invention.

[0097] by Figure 4 For example, a first epitaxial layer 201 may be grown on the substrate structure, and then a high-dose ion implantation source 11 of the first conductivity type and a high-dose ion implantation source 21 of the second conductivity type may be implanted into the first epitaxial layer 201 .

[0098] Continue to refer Figure 5 , then continue to grow the second epitaxial layer 202 on the side of the first epitaxial layer 201 away from the substrate structure, and then continue to implant the first conductivity type high-dose ion implantation source 11 and the second conductivity type high-dose ion implantation source 21 into the second epitaxial layer 202 respectively, wherein the implantation areas between the first conductivity type high-dose ion implantation source 11 and the second conductivity type high-dose ion implantation source 21 on the first epitaxial layer 201 and the second epitaxial layer 202 are alternately arranged.

[0099] Please continue to refer to Figure 6 , the third epitaxial layer 203 continues to grow on the side of the second epitaxial layer 202 away from the substrate structure, and a high-dose ion implantation source 21 of the second conductivity type, a high-dose ion implantation source 11 of the first conductivity type, a low-dose ion implantation source 12 of the first conductivity type, a high-dose ion implantation source 21 of the second conductivity type and a low-dose ion implantation source 22 of the second conductivity type are respectively implanted, wherein the above-mentioned ion implantation sources are respectively implanted according to the corresponding positions shown in the figure.

[0100] Please continue to refer to Figure 7In this embodiment, the implantation of the fourth epitaxial layer 204, the fifth epitaxial layer 205 and the sixth epitaxial layer 206 is completed respectively according to the above implantation method.

[0101] exist Figure 7 Based on Figure 8 , thermally diffuse each epitaxial layer to form the super junction withstand voltage structure in this embodiment, Figure 8 Based on this, the present invention can suppress the lateral doping diffusion at the junction of the first voltage-resistant region 30 and the second voltage-resistant region 31, thereby ensuring the morphology of the superjunction voltage-resistant structure finally formed.

[0102] Based on this, the upper part of the superjunction voltage-withstanding structure of the present invention is composed of the fourth voltage-withstanding region 33, the first voltage-withstanding region 30, the second voltage-withstanding region 31 and the third voltage-withstanding region 32 in the lateral direction; the lower part of the superjunction voltage-withstanding structure is composed of the first voltage-withstanding region 30 and the second voltage-withstanding region 31 in the lateral direction. The upper part of the superjunction voltage-withstanding structure satisfies the charge balance condition, and the lower part of the superjunction structure satisfies the charge balance condition, based on which the superjunction voltage-withstanding structure maintains overall charge balance and local charge balance.

[0103] In one possible implementation, in order to further improve the softness of the body diode and the number of unbalanced carriers so as to enhance the reverse recovery softness and suppress reverse recovery oscillation, in one possible implementation, the doping concentration of the first voltage-resistant region 30 is equal to the doping concentration of the second voltage-resistant region 31 ; the doping concentration of the fourth voltage-resistant region 33 is equal to the doping concentration of the third voltage-resistant region 32 .

[0104] Furthermore, the thickness of the first voltage-resistant region 30 is equal to the thickness of the second voltage-resistant region 31 ; the thickness of the fourth voltage-resistant region 33 is equal to the thickness of the third voltage-resistant region 32 .

[0105] After preparing the pressure-resistant area, Figure 8 Based on the reference Fig. 9 , Fig.10 , Fig. 9 A schematic diagram showing the arrangement area of ​​the trench gate structure in this embodiment is shown, Fig.10 A schematic diagram of the second base region setting area in the present embodiment is shown; the present embodiment is based on setting a groove-type gate structure 50 and a second base region 42 on the side of each first voltage-resistant region 30 away from the substrate structure, and the second base region 42 is set on both sides of the groove-type gate structure 50. The present embodiment sets a groove-type gate structure 50 on the side of each first voltage-resistant region 30 away from the substrate structure.

[0106] by Fig. 9For example, in one possible implementation, a trench can be formed by etching the top of the first voltage-sustaining region 30. A gate oxide layer 52 is formed by a thermal oxidation process, and then a conductive polysilicon 51 is deposited and etched to form a trench gate structure 50. Fig.10 For example, a second base region 42 can be formed at a first depth by ion implantation on the top of the voltage-resistant region, wherein the second base region 42 covers the top of the voltage-resistant region (the side away from the substrate structure) and exposes the top of the trench gate structure 50 (the side away from the substrate structure).

[0107] exist Fig.10 Based on the reference Fig.11 , Fig.12 , Fig.11 A schematic diagram showing the first base region and the source region setting area, Fig.12 A schematic diagram showing the etching area of ​​the first base region and the second base region is shown. In this embodiment, the first base region 41 is set on the side of each second base region 42 away from the substrate structure. In order to make the second base region 42 and the first base region 41 form a boss structure, and the upper surface height of the boss structure is consistent with the upper surface height of the groove-type gate structure 50, in a possible implementation method, the first base region 41 and the source region 40 can be formed at a second depth on the second base region 42 by ion implantation, wherein the source region 40 is located around the groove-type gate structure 50. Then, the first base region 41 and the second base region 42 at the top area of ​​the second voltage-resistant region 31 are etched to form a groove structure. At this time, the top areas of the second voltage-resistant region 31 and the third voltage-resistant region 32 are exposed again.

[0108] During the first etching process, in order to ensure that the top of the trench gate structure 50 (the side away from the substrate structure) is exposed, the etching depth may be equal to the second depth.

[0109] Please continue to refer to Fig.12 In this embodiment, a cut-off layer 43 is further provided on the top surface of the second voltage-sustaining region 31 and the third voltage-sustaining region 32. In a possible implementation, the cut-off layer 43 is provided by ion implantation. The cut-off layer 43 is formed by implanting acceptor impurity ions such as boron ions.

[0110] In this embodiment, the doping concentration of the cut-off layer 43 is lower than the doping concentration of the second base region 42, and / or higher than the doping concentration of the second voltage-sustaining region 31. When the doping concentration of the cut-off layer 43 is lower than the doping concentration of the second base region 42, the device works in the reverse conduction state, and electrons are easily injected from the first voltage-sustaining region 30 into the cut-off layer 43, and then collected by the Schottky contact conductor, which can reduce the injection efficiency of holes in the reverse conduction state, thereby reducing the reverse recovery charge Q of the body diode. rrWhen the doping concentration of the cut-off layer 43 is higher than the doping concentration of the second voltage-sustaining region 31 , electrons can pass through the cut-off layer 43 , thereby preventing the device from being punched through.

[0111] When the doping concentration of the cutoff layer 43 is lower than the doping concentration of the second base region 42 and higher than the doping concentration of the second voltage-resistant region 31, and the ratio of the doping concentrations of the second voltage-resistant region 31 to the third voltage-resistant region 32 is greater than or equal to 3, the softness factor S of the reverse recovery can be greatly reduced, and the current oscillation and voltage oscillation of the reverse recovery process can be suppressed.

[0112] Continue to refer Fig.12 It can be seen that there is a preset height difference between the stop layer 43 and the boss structure, that is, the first base region 41 and the second base region 42 form a groove structure in the top area of ​​the second voltage-resistant region 31, and the upper surface of the stop layer 43 is flush with the lower surface of the first base region 41 and the second base region 42, or the value of the preset height difference can be equal to the sum of the thickness of the first base region 41 and the second base region 42. This structure can expose the upper surface area of ​​the second voltage-resistant region 31 and the third voltage-resistant region 32 again.

[0113] Later in Fig.12 On the basis of the above, a source Schottky contact conductor 4, a gate conductor 2, and a source ohmic contact conductor 3 are respectively arranged. In a possible implementation, the gate conductor 2 is arranged on the surface of the groove-type gate structure 50. The source ohmic contact conductor 3 is arranged on the surface of the source region 40 and the first base region 41 between the two groove-type gate structures 50. The gate conductor 2 and the source ohmic contact conductor 3 are not connected.

[0114] You can then continue to refer to Figure 2 In this embodiment, when the first base region 41 and the second base region 42 form a groove structure in the top area of ​​the second voltage-resistant region 31, the longitudinal and lateral surfaces of the second base region 42 and the first base region 41 adjacent to the cut-off layer 43 are exposed, and after the source ohmic contact conductor 3 is set, the lateral and longitudinal surfaces of the first base region 41 and the second base region 42 are covered by the source ohmic contact conductor 3. In this way, the function of the source ohmic contact conductor 3 is not affected.

[0115] In this embodiment, the metal types of the source Schottky contact conductor 4 include aluminum, copper, titanium and other metals. In a possible implementation, the source Schottky contact conductor 4 is disposed in the form of deposition on the surface of the cutoff layer 43. The metal types of the source ohmic contact conductor 3 include aluminum, copper, titanium and other metals. The source ohmic contact conductor 3 is disposed in the form of deposition on the surface of the source region 40, the first base region 41 and the second base region 42.

[0116] In this embodiment, the substrate 10, the auxiliary layer 20, and the first voltage-sustaining region 30 are structures of the first conductivity type, and the second voltage-sustaining region 31, the stop layer 43, the first base region 41, and the second base region 42 are structures of the second conductivity type.

[0117] Please refer to Fig.13 , Fig.14 , Fig.13 A schematic diagram showing a comparison of the breakdown voltages of the superjunction semiconductor structure of the present invention (i.e., the superjunction MOSFET provided by the present invention in the figure) and the conventional superjunction MOSFET in the prior art; Fig.14 A schematic diagram is shown comparing the reverse recovery current waveforms of the superjunction semiconductor structure in the present invention (i.e., the superjunction MOSFET provided by the present invention in the figure) and the conventional superjunction MOSFET in the prior art; it can be seen that when in the reverse recovery stage, the conventional superjunction semiconductor structure exhibits the following characteristics: the reverse recovery duration of the conventional superjunction semiconductor structure is longer, the reverse recovery peak current and the reverse recovery charge are larger, and obvious current oscillations and voltage oscillations occur, which may cause device failure and be detrimental to the reliability of the device.

[0118] Compared with the traditional superjunction semiconductor structure, the reverse recovery peak current of the superjunction semiconductor structure of the present invention is reduced by 30%, the reverse recovery charge is reduced by 50%, and no current oscillation and voltage oscillation occur. The reverse recovery performance and reliability of the device are greatly improved.

[0119] In summary, an embodiment of the present invention provides a superjunction semiconductor structure and a preparation method thereof, wherein the doping concentration of the first voltage-resistant region of the present invention is equal to the doping concentration of the second voltage-resistant region, and the doping concentration of the fourth voltage-resistant region is equal to the doping concentration of the third voltage-resistant region; the thickness of the first voltage-resistant region is equal to the thickness of the second voltage-resistant region, and the thickness of the fourth voltage-resistant region is equal to the thickness of the third voltage-resistant region, so that the upper and lower halves of the prepared superjunction structure maintain charge balance to avoid the breakdown voltage of the device being affected. In addition, the present invention makes the doping concentration of the third voltage-resistant region lower than the doping concentration of the second voltage-resistant region, so that the overall equivalent resistance of the third voltage-resistant region and the second voltage-resistant region is increased. During the reverse recovery process of the body diode, the resistance on the hole extraction path during the reverse recovery process is increased, and the hole extraction speed during the reverse recovery process is slowed down, thereby improving the reverse recovery softness and suppressing reverse recovery oscillation. At the same time, the doping concentration of the cutoff layer is lower than that of the second base region. When the device operates in the reverse conduction state, electrons are easily injected from the first voltage-resistant region into the cutoff layer and then collected by the Schottky contact conductor. This can reduce the hole injection efficiency of the device in the reverse conduction state, thereby reducing the reverse recovery charge of the body diode.

[0120] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0121] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a superjunction semiconductor, characterized in that: include: providing a substrate structure; A voltage-resistant region is provided on one side of the substrate structure; the voltage-resistant region comprises a first voltage-resistant region and a second voltage-resistant region which are arranged alternately; wherein the first voltage-resistant region and the second voltage-resistant region have different conductivity types; A third voltage-resistant region is arranged on the top of each of the second voltage-resistant regions; wherein the third voltage-resistant region has the same conductivity type as the second voltage-resistant region; A fourth voltage-resistant region is arranged on top of each of the first voltage-resistant regions; wherein the first voltage-resistant region and the fourth voltage-resistant region have the same conductivity type; A trench gate structure and a second base region are arranged on a side of each of the first voltage-resistant regions away from the substrate structure; wherein the second base region is arranged on both sides of the trench gate structure; A first base region is arranged based on a side of each of the second base regions away from the substrate structure; wherein the second base region and the first base region form a boss structure; and an upper surface of the boss structure is flush with an upper surface of the groove-type gate structure; A cut-off layer is provided based on a side of each second voltage-resistant region away from the substrate structure; wherein a preset height difference exists between the cut-off layer and the boss structure; The doping concentration of the third voltage-sustaining region is lower than the doping concentration of the second voltage-sustaining region; The doping concentration of the fourth voltage-sustaining region is lower than the doping concentration of the first voltage-sustaining region.

2. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: The doping concentration of the first voltage-sustaining region is equal to the doping concentration of the second voltage-sustaining region; The doping concentration of the fourth voltage-sustaining region is equal to the doping concentration of the third voltage-sustaining region.

3. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: The thickness of the first pressure-resistant region is equal to the thickness of the second pressure-resistant region; The thickness of the fourth voltage-sustaining region is equal to the thickness of the third voltage-sustaining region.

4. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: A source Schottky contact conductor is disposed on a side of the cut-off layer away from the substrate structure.

5. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: The lateral surfaces and the longitudinal surfaces of the first base region and the second base region are all covered by a source ohmic contact conductor.

6. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: The doping concentration of the cutoff layer is lower than the doping concentration of the second base region.

7. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: The doping concentration of the cut-off layer is higher than the doping concentration of the second voltage-sustaining region.

8. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: A ratio of doping concentrations of the second voltage-resistant region to that of the third voltage-resistant region is greater than or equal to 3.

9. The method for preparing a superjunction semiconductor according to claim 1, characterized in that: A ratio of the doping concentrations of the first voltage-resistant region to the fourth voltage-resistant region is greater than or equal to 3.

10. A superjunction semiconductor structure, characterized in that: include; Substrate structure; A voltage-resistant region located at one side of the substrate structure; the voltage-resistant region comprises a first voltage-resistant region and a second voltage-resistant region that are alternately arranged; wherein the first voltage-resistant region and the second voltage-resistant region have different conductivity types; a third voltage-sustaining region located on top of each of the second voltage-sustaining regions; wherein the third voltage-sustaining region has the same conductivity type as the second voltage-sustaining region; a fourth voltage-sustaining region located on top of each of the first voltage-sustaining regions; wherein the first voltage-sustaining region and the fourth voltage-sustaining region have the same conductivity type; A trench gate structure and a second base region located at a side of each of the first voltage-resistant regions away from the substrate structure; wherein the second base region is arranged on both sides of the trench gate structure; A first base region located at a side of each of the second base regions away from the substrate structure; wherein the second base region and the first base region form a boss structure, and an upper surface of the boss structure is flush with an upper surface of the trench-type gate structure; A cut-off layer located on a side of each of the second voltage-resistant regions away from the substrate structure; wherein a preset height difference exists between the cut-off layer and the boss structure; Wherein, the doping concentration of the third voltage-resistant region is lower than the doping concentration of the second voltage-resistant region; The doping concentration of the fourth voltage-sustaining region is lower than the doping concentration of the first voltage-sustaining region.

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