Semiconductor structure and manufacturing method thereof
By providing multiple second grooves in the epitaxial layer of the SiC plane MOSFET device, increasing the channel width and conduction area, the problem of high device on-resistance is solved and the linearity and transconductance flatness of the device are improved.
Patent Information
- Application Number
- CN202311277891.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-28
- Publication Date
- 2025-04-04
AI Technical Summary
The high on-resistance of existing SiC plane MOSFET devices affects their performance, especially in power switch and converter applications.
A semiconductor structure is designed, including an N-type substrate and an epitaxial layer, which includes an N-type drift region, a P-type well region, an N-type source region and a JFET region, and a plurality of second grooves are provided on the side of the epitaxial layer away from the N-type substrate to increase the channel width and conduction area.
By increasing the channel width and conduction area, the channel resistance and interface state density are effectively reduced, and the linearity and transconductance flatness of the device are improved.
Smart Images
Figure CN119767756A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] Silicon carbide (SiC) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices have the advantages of fast switching speed and low on-resistance, and can achieve a higher breakdown voltage level at a smaller drift layer thickness, reducing the size of the power switch module and reducing energy consumption. They have obvious advantages in application fields such as power switches and converters.
[0003] SiC planar MOSFET devices are widely used due to their simple process, good unit consistency, and high avalanche energy. However, how to further improve the performance of SiC planar MOSFET devices, such as reducing device on-resistance and improving device linearity, has also become one of the hot issues that technicians in this field have been studying. Summary of the invention
[0004] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to further reduce the on-resistance of SiC planar MOSFET devices.
[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized in that it includes:
[0006] An N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other, the first surface having a plurality of first grooves;
[0007] an epitaxial layer, the epitaxial layer being located on the first surface of the N-type substrate, the epitaxial layer comprising an N-type drift region, a P-type well region, an N-type source region and a JFET region, the N-type drift region being located on a side of the epitaxial layer close to the N-type substrate, the P-type well region and the JFET region being located on a side of the epitaxial layer away from the N-type substrate and being laterally adjacent, the P-type well region being located on both sides of the JFET region, and the N-type source region being located within a surface of the P-type well region away from the N-type substrate;
[0008] The surface of the epitaxial layer away from the N-type substrate has a plurality of second grooves, the second grooves correspond to the first grooves one by one, and the second grooves and the first grooves are parallel to the channel length direction of the semiconductor structure.
[0009] As an optional embodiment, along the channel width direction, the thickness of the P-type well region below the second groove is smaller than the thickness of the P-type well region between two adjacent second grooves.
[0010] As an optional embodiment, the P-type ion doping concentration of the P-type well region below the second groove away from the surface of the N-type substrate is greater than the P-type ion doping concentration of the P-type well region between two adjacent second grooves away from the surface of the N-type substrate.
[0011] As an optional embodiment, the thickness of the JFET region below the second groove is smaller than the thickness of the JFET region between two adjacent second grooves.
[0012] As an optional embodiment, along the channel width direction, the thickness of the N-type source region is constant.
[0013] As an optional embodiment, along the channel width direction, the depth variation trend of the plurality of second grooves includes at least one of the following variation trends: periodic variation, gradual increase, gradual decrease, first increase and then decrease, or first decrease and then increase.
[0014] As an optional embodiment, along the channel width direction, a thickness variation trend of the P-type well region below the plurality of second grooves is opposite to a depth variation trend of the plurality of second grooves.
[0015] As an optional embodiment, the depth of the second groove is smaller than the thickness of the N-type source region.
[0016] As an optional embodiment, the bottom surface of the second groove is a (0001) crystal plane, and the sidewall of the second groove includes at least one of a (1100) crystal plane, a (1010) crystal plane, a (1120) crystal plane or a (0338) crystal plane.
[0017] As an optional embodiment, in a direction perpendicular to the channel length, the cross-sectional shape of the first groove and the second groove includes at least one of a rectangle, a trapezoid, a triangle, a bowl and an arc.
[0018] As an optional embodiment, a second protrusion is provided between two adjacent second grooves, and a width of the second protrusion is less than or equal to 1 μm.
[0019] As an optional embodiment, there is a first protrusion between two adjacent first grooves, and in the direction perpendicular to the channel length, the cross-sectional shape of the first protrusion and the second protrusion includes at least one of a rectangle, a trapezoid, a triangle, a bowl and an arc.
[0020] As an optional embodiment, the semiconductor structure further comprises:
[0021] A source electrode, located at a side of the N-type source region away from the N-type substrate;
[0022] A drain electrode, located at a side of the N-type substrate away from the N-type source region;
[0023] A gate, located on a side of the P-type well region and the JFET region away from the N-type substrate;
[0024] The gate oxide layer is located on a side of the gate close to the N-type substrate.
[0025] As an optional embodiment, the material of the gate oxide layer includes at least one of aluminum oxide, aluminum nitride and aluminum oxynitride.
[0026] As an optional embodiment, the material of the N-type substrate and the epitaxial layer includes silicon carbide.
[0027] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, characterized in that it includes the following steps:
[0028] S1. Provide an N-type substrate, wherein the N-type substrate comprises a first surface and a second surface opposite to each other, wherein the first surface has a plurality of first grooves;
[0029] S2, forming an epitaxial layer on the first surface of the N-type substrate, wherein a surface of the epitaxial layer away from the N-type substrate has a plurality of second grooves, the second grooves correspond to the first grooves one by one, and the second grooves and the first grooves are parallel to the channel length direction of the semiconductor structure;
[0030] S3. Performing ion implantation on a side of the epitaxial layer away from the N-type substrate to form a P-type well region, and performing ion implantation on a side of the P-type well region away from the N-type substrate to form an N-type source region. The epitaxial layer also includes an N-type drift region and a JFET region that have not been ion implanted. The N-type drift region is located on a side of the epitaxial layer close to the N-type substrate, the JFET region is located on a side of the epitaxial layer away from the N-type substrate, and the P-type well region is located on both sides of the JFET region.
[0031] As an optional embodiment, the second groove of the epitaxial layer is conformally formed on the first groove of the N-type substrate.
[0032] As an optional embodiment, a method for forming the P-type well region by ion implantation includes:
[0033] A silicon dioxide mask layer is disposed on a side of the epitaxial layer away from the N-type substrate, wherein the side of the silicon dioxide mask layer away from the N-type substrate is a plane;
[0034] Ion implantation forms a P-type well region with a plane on one side close to the N-type substrate;
[0035] The silicon dioxide mask layer is removed.
[0036] As an optional embodiment, the thickness of the N-type source region formed by ion implantation is constant.
[0037] As an optional embodiment, the step S3 further includes:
[0038] S4, conformally preparing a gate oxide layer on a side of the P-type well region and the JFET region away from the N-type substrate.
[0039] S5. Prepare a source electrode on a side of the N-type source region away from the N-type substrate, prepare a drain electrode on a side of the N-type substrate away from the N-type source region, and prepare a gate electrode on a side of the gate oxide layer away from the N-type substrate.
[0040] The present disclosure provides a semiconductor structure, comprising an N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other, the first surface having a plurality of first grooves; an epitaxial layer, the epitaxial layer being located on the first surface of the N-type substrate, the epitaxial layer comprising an N-type drift region, a P-type well region, an N-type source region and a JFET region, the N-type drift region being located on a side of the epitaxial layer close to the N-type substrate, the P-type well region and the JFET region being located on a side of the epitaxial layer away from the N-type substrate and being laterally adjacent, the P-type well region being located on both sides of the JFET region, and the N-type source region being located in a surface of the P-type well region away from the N-type substrate; wherein a surface of the epitaxial layer away from the N-type substrate has a plurality of second grooves, the second grooves correspond one-to-one to the first grooves, and the second grooves and the first grooves are parallel to a channel length direction of the semiconductor structure.
[0041] The second groove provided in the present invention can, on the one hand, effectively increase the channel width, thereby increasing the channel conduction area, and effectively reducing the channel resistance and interface state density; on the other hand, the electron mobility of the crystal plane of the side wall of the second groove is greater than the electron mobility of the horizontal plane, further improving the electron mobility of the device; on the other hand, the gate fills the second groove and covers the second protruding surface, effectively increasing the gate control area and improving the gate's control ability over the channel.
[0042] The N-type drift region disclosed in the present invention is formed on the first surface of the N-type substrate. Since the first surface has a plurality of first grooves, the side of the epitaxial layer away from the N-type substrate has a second groove. Compared with the method of forming the second groove by etching, etching damage to the epitaxial layer is avoided, thereby avoiding the introduction of interface impurities.
[0043] The second groove provided in the present invention can make the thickness of the P-type well region different along the channel width direction. Since the P-type impurity ions injected by ions are Gaussian distributed, the ion doping concentrations on the surfaces of the P-type well regions with different thicknesses are different, thereby forming different threshold voltages in the channel layer at different positions, so that the semiconductor structure is gradually turned on along the channel width direction, which can slow down the decrease of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the semiconductor structure, and further improving the linearity of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0045] Figure 2 Shown Figure 1 A schematic structural diagram of a semiconductor structure along the AA' cross section is provided.
[0046] Figure 3 Shown Figure 1 A schematic structural diagram of a semiconductor structure along the BB' cross section is provided.
[0047] Figures 4a to 4c Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0048] Figure 5a to Figure 5b Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0049] Figure 6a to Figure 6b Shown is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
[0050] Figure 7 Shown is a schematic flow chart of a semiconductor structure manufacturing method provided in one embodiment of the present disclosure.
[0051] Figures 8 to 15 Shown is a schematic structural diagram of an intermediate structure of a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0052] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0053] In order to further improve the performance of SiC planar MOSFET devices, the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes an N-type substrate having a plurality of first grooves on a first surface; an epitaxial layer located on the first surface of the N-type substrate, the epitaxial layer including an N-type drift region, a P-type well region, an N-type source region, and a JFET region; wherein the surface of the epitaxial layer away from the N-type substrate has a plurality of second grooves, the second grooves correspond to the first grooves one by one, and the second grooves and the first grooves are parallel to the channel length direction of the semiconductor structure. The present disclosure obtains the second grooves of the epitaxial layer by conformal preparation of the first grooves of the N-type substrate, which can effectively increase the channel width, thereby increasing the channel conduction area, and effectively reducing the channel resistance and interface state density; on the other hand, it can prevent the epitaxial layer from being damaged by etching, thereby preventing the introduction of interface impurities.
[0054] Combine the following Figures 1 to 15 A semiconductor structure and a manufacturing method thereof mentioned in the present disclosure are further illustrated by way of example.
[0055] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure includes: an N-type substrate 10, the N-type substrate 10 includes a first surface and a second surface opposite to each other, the first surface having a plurality of first grooves 101; an epitaxial layer 20, the epitaxial layer 20 is located on the first surface of the N-type substrate 10, the epitaxial layer 20 includes an N-type drift region 21, a P-type well region 22, an N-type source region 23 and a JFET region 24, the N-type drift region 21 is located on the side of the epitaxial layer 20 close to the N-type substrate 10, the P-type well region 22 and the JFET region 24 are located on the side of the epitaxial layer 20 away from the N-type substrate 10 and are laterally adjacent, the P-type well region 22 is located on both sides of the JFET region 24, and the N-type source region 23 is located in the surface of the P-type well region 22 away from the N-type substrate 10; wherein, the surface of the epitaxial layer 20 away from the N-type substrate 10 has a plurality of second grooves 201, the second grooves 201 correspond to the first grooves 101 one by one, and the second grooves 201 and the first grooves 101 are parallel to the channel length direction of the semiconductor structure. Figure 1 As shown, the semiconductor structure further includes: a source 31, located on a side of the N-type source region 23 away from the N-type substrate 10; a drain 32, located on a side of the N-type substrate 10 away from the N-type source region 23; a gate 33, located on a side of the P-type well region 22 and the JFET region 24 away from the N-type substrate 10; and a gate oxide layer 34, located on a side of the gate 33 close to the N-type substrate 10.
[0056] In this embodiment, the material of the N-type substrate 10 and the epitaxial layer 20 includes silicon carbide. In other optional embodiments, the material of the N-type substrate 10 may also be a substrate material such as Si or sapphire, and the material of the epitaxial layer 20 may also be a GaN-based material such as GaN or AlGaN. The material of the gate oxide layer 34 includes at least one of aluminum oxide, aluminum nitride and aluminum oxynitride. The material of the gate oxide layer 34 has a strong charge binding ability. In the external electric field formed, the charge is not easily polarized, the polarized charge is small, and the polarized electric field is weak, which effectively avoids the short channel effect of the semiconductor structure. Setting the gate oxide layer 34 to form a MIS gate structure can effectively reduce the gate leakage current, increase the gate voltage swing and the drain current swing, and further improve the device performance.
[0057] In this embodiment, Figure 2 Shown Figure 1 The schematic diagram of the structure of the semiconductor structure provided is along the AA' section. Figure 2 As shown, the thickness of the P-type well region 22 below the second groove 201 is less than the thickness of the P-type well region 22 between two adjacent second grooves 201. Since the P-type well region 22 is formed by an ion implantation process, the concentration distribution of the P-type ions in the P-type well region 22 is a Gaussian distribution, and the greater the thickness of the P-type well region 22, the smaller the P-type ion concentration of the surface of the P-type well region 22 away from the N-type substrate 10. Therefore, the P-type ion doping concentration of the P-type well region 22 below the second groove 201 away from the surface of the N-type substrate 10 is greater than the P-type ion doping concentration of the P-type well region 22 between two adjacent second grooves 201 away from the surface of the N-type substrate 10. By setting the second groove 201, the thickness of the P-type well region 22 is made different along the channel width direction, and the ion doping concentration on the surface of the P-type well region 22 with different thickness is further made different, so that different threshold voltages are formed in the channel layer at different positions, so that the semiconductor structure is gradually turned on along the channel width direction, and the decrease of the transconductance curve when the drain current is large is slowed down, thereby improving the transconductance flatness of the semiconductor structure, and then improving the linearity of the semiconductor structure.
[0058] In this embodiment, a JFET region 24 is formed between two adjacent P-type well regions 22, and the thickness of the JFET region 24 is the same as the thickness of the P-type well region 22, so the thickness of the JFET region 24 below the second groove 201 is less than the thickness of the JFET region 24 between two adjacent second grooves 201. The smaller the thickness of the JFET region 24, the smaller the resistance of the JFET region 24, and the thickness of the JFET region 24 can be controlled by controlling the thickness of the P-type well region 22, thereby adjusting the resistance of the JFET region 24, and finally adjusting the on-resistance.
[0059] In this embodiment, Figure 3 Shown Figure 1 The schematic diagram of the structure of the semiconductor structure provided is along the BB' section. Figure 3As shown, along the channel width direction, the thickness of the N-type source region 23 is constant, so that the current of the source 31 can be evenly distributed in the N-type source region 23, thereby improving the uniformity of the source current.
[0060] In one embodiment, the depth of the second groove 201 is less than the thickness of the N-type source region 23, the bottom surface of the second groove 201 is a (0001) crystal plane, the sidewall of the second groove 201 includes at least one of a (1100) crystal plane, a (1010) crystal plane, a (1120) crystal plane or a (0338) crystal plane, and the sidewall of the second groove 201 has a channel mobility greater than the bottom surface of the second groove 201. The arrangement of the second groove 201, on the one hand, can effectively increase the channel width, that is, increase the width of the sidewall of the second groove 201, thereby increasing the channel conduction area, and effectively reducing the channel resistance and interface state density; on the other hand, the electron mobility of the crystal plane of the sidewall of the second groove 201 is greater than the electron mobility of the horizontal plane, which effectively improves the electron mobility of the semiconductor structure, thereby reducing the channel resistance of the semiconductor structure.
[0061] In one embodiment, Figures 4a to 4c FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 4a As shown, at least one second groove 201 has a depth different from other second grooves 201, and the P-type well region 22 under at least one second groove 201 has a thickness different from that of the P-type well region 22 under other second grooves 201. The greater the depth of the second groove 201, the smaller the thickness of the P-type well region 22, and the greater the P-type ion concentration of the surface of the P-type well region 22 away from the N-type substrate 10. The thickness of the P-type well region 22 is negatively correlated with the depth of the second groove 201. By controlling the depth of the second groove 201, the thickness of the P-type well region 22 can be controlled, thereby controlling the ion doping concentration on the surface of the P-type well region 22, and ultimately controlling the threshold voltage of the channel layer.
[0062] Optionally, along the channel width direction, the depth variation trend of the plurality of second grooves 201 includes at least one of the following variation trends: periodic variation (such as Figure 4a As shown), gradually increasing (as Figure 4b As shown), gradually decreases, first increases and then decreases (as shown Figure 4cAs shown in the figure, or first decreases and then increases, along the channel width direction, the thickness variation trend of the P-type well region 22 below the plurality of second grooves 201 is opposite to the depth variation trend of the plurality of second grooves 201, and the P-type ion concentration variation trend of the surface of the P-type well region 22 below the plurality of second grooves 201 away from the N-type substrate 10 is the same as the depth variation trend of the plurality of second grooves 201. The P-type well region 22 with different surface ion concentrations along the channel width direction is provided, so that different threshold voltages are formed at channel layers at different positions, so that the semiconductor structure is gradually turned on along the channel width direction, and the decline of the transconductance curve at a large drain current can be slowed down, thereby improving the transconductance flatness of the semiconductor structure, and further improving the linearity of the semiconductor structure.
[0063] In one embodiment, Figure 5a to Figure 5b FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. In a direction perpendicular to the channel length, the cross-sectional shape of the first groove 101 and the second groove 201 includes a rectangular shape (eg Figure 5a As shown), trapezoid, triangle (as shown Figure 5b The present disclosure does not specifically limit the cross-sectional shape of the first groove 101 and the second groove 201. By controlling the shape of the second groove 201, the shape and surface ion concentration of the P-type well region 22 can be further controlled, thereby controlling the threshold voltage of the channel layer at different positions.
[0064] In one embodiment, Figure 6a to Figure 6b The structure diagram of the semiconductor structure provided by an embodiment of the present disclosure is shown. A second protrusion 202 is provided between two adjacent second grooves 201, and the width of the second protrusion 202 is less than or equal to 1 μm. A first protrusion 102 is provided between two adjacent first grooves 101. In the direction perpendicular to the channel length, the cross-sectional shapes of the first protrusion 102 and the second protrusion 202 include a rectangle, a trapezoid (such as Figure 6a ), triangle, bowl and arc (as shown in Figure 6b The shape of the second protrusion 202 can also be controlled to further control the shape and surface ion concentration of the P-type well region 22, thereby controlling the threshold voltage of the channel layer at different positions.
[0065] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure. Figure 7 FIG. 1 is a schematic diagram of a process for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figures 8 to 15 FIG. 1 is a schematic diagram of an intermediate structure of a semiconductor structure provided by an embodiment of the present disclosure. Figure 7 As shown, the method for manufacturing a semiconductor structure includes:
[0066] Step S1: Figure 8As shown, an N-type substrate 10 is provided, and the N-type substrate 10 includes a first surface and a second surface opposite to each other, and the first surface has a plurality of first grooves 101. The material of the N-type substrate 10 includes silicon carbide. In other optional embodiments, the material of the N-type substrate 10 can also be a substrate material such as Si or sapphire.
[0067] Step S2: Fig. 9 As shown, an epitaxial layer 20 is formed on the first surface of the N-type substrate 10, and a surface of the epitaxial layer 20 away from the N-type substrate 10 has a plurality of second grooves 201, and the second grooves 201 correspond to the first grooves 101 one by one, and the second grooves 201 and the first grooves 101 are parallel to the channel length direction of the semiconductor structure. The second grooves 201 of the epitaxial layer 20 are conformally formed on the first grooves 101 of the N-type substrate 10, and compared with the method of forming the second grooves 201 by etching, etching damage to the epitaxial layer 20 is avoided, thereby avoiding the introduction of interface impurities.
[0068] Step S3: Figures 10 to 12 As shown, ion implantation is performed on the side of the epitaxial layer 20 away from the N-type substrate 10 to form a P-type well region 22, and ion implantation is performed on the side of the P-type well region 30 away from the N-type substrate 10 to form an N-type source region 23. The epitaxial layer 20 also includes an N-type drift region 21 and a JFET region 24 that have not been ion implanted. The N-type drift region 21 is located on the side of the epitaxial layer 20 close to the N-type substrate 10, the JFET region 24 is located on the side of the epitaxial layer 20 away from the N-type substrate 10, and the P-type well region 22 is located on both sides of the JFET region 24. The thickness of the N-type source region 23 formed by ion implantation is constant, so that the current of the source 31 can be evenly distributed in the N-type source region 23, thereby improving the uniformity of the source current.
[0069] In this embodiment, the method for forming the P-type well region 22 by ion implantation includes: providing a silicon dioxide mask layer 202 on a side of the epitaxial layer 20 away from the N-type substrate 10, wherein the side of the silicon dioxide mask layer 202 away from the N-type substrate 10 is a plane (eg, Fig.13 ion implantation to form a planar P-type well region 22 (as shown in FIG. Fig.14 ); removing the silicon dioxide mask layer 202 (as shown); Fig.11As shown). The shape of the side of the P-type well region 22 close to the N-type substrate 10 can be controlled by controlling the surface shape of the silicon dioxide mask layer 202 away from the N-type substrate 10. The side of the P-type well region 22 close to the N-type substrate 10 is a plane, so the thickness of the P-type well region 22 is negatively correlated with the depth of the second groove 201. Since the P-type impurity ions implanted are Gaussian distributed, the ion doping concentrations on the surfaces of the P-type well regions 22 with different thicknesses are different, so that different threshold voltages are formed in the channel layers at different positions, so that the semiconductor structure is gradually turned on along the channel width direction, which can slow down the decline of the transconductance curve when the drain current is large, thereby improving the transconductance flatness of the semiconductor structure, and further improving the linearity of the semiconductor structure.
[0070] Step S3 further includes:
[0071] Step S4: Fig.15 As shown, a gate oxide layer 34 is conformally formed on a side of the P-type well region 22 and the JFET region 24 away from the N-type substrate 10 .
[0072] Step S5: Form a source electrode 31 on the side of the N-type source region 23 away from the N-type substrate 10, form a drain electrode 32 on the side of the N-type substrate 10 away from the N-type source region 23, and form a gate electrode 33 on the side of the gate oxide layer 34 away from the N-type substrate 10. Figure 1 The gate 33 fills the groove in the gate oxide layer 34 and covers the surface of the gate oxide layer 34, which effectively increases the gate control area and improves the control ability of the gate 33 on the channel.
[0073] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises an N-type substrate having a plurality of first grooves on a first surface; an epitaxial layer located on the first surface of the N-type substrate, wherein the epitaxial layer comprises an N-type drift region, a P-type well region, an N-type source region, and a JFET region; wherein a surface of the epitaxial layer away from the N-type substrate has a plurality of second grooves, the second grooves correspond to the first grooves one by one, and the second grooves and the first grooves are parallel to the channel length direction of the semiconductor structure. The present disclosure obtains the second grooves of the epitaxial layer by conformal preparation of the first grooves of the N-type substrate, which can effectively increase the channel width, thereby increasing the channel conduction area, and effectively reducing the channel resistance and interface state density; on the other hand, it can prevent the epitaxial layer from being damaged by etching, thereby preventing the introduction of interface impurities.
[0074] It should be understood that the term "including" and its variations used in the present disclosure are open inclusions, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.
[0075] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A semiconductor structure, characterized in that: include: An N-type substrate (10), the N-type substrate (10) comprising a first surface and a second surface opposite to each other, the first surface having a plurality of first grooves (101); An epitaxial layer (20), the epitaxial layer (20) being located on a first surface of the N-type substrate (10), the epitaxial layer (20) comprising an N-type drift region (21), a P-type well region (22), an N-type source region (23) and a JFET region (24), the N-type drift region (21) being located on a side of the epitaxial layer (20) close to the N-type substrate (10), the P-type well region (22) and the JFET region (24) being located on a side of the epitaxial layer (20) away from the N-type substrate (10) and being laterally adjacent, the P-type well region (22) being located on both sides of the JFET region (24), and the N-type source region (23) being located within a surface of the P-type well region (22) away from the N-type substrate (10); The surface of the epitaxial layer (20) away from the N-type substrate (10) has a plurality of second grooves (201), the second grooves (201) correspond to the first grooves (101) one by one, and the second grooves (201) and the first grooves (101) are parallel to the channel length direction of the semiconductor structure.
2. The semiconductor structure according to claim 1, characterized in that: The thickness of the P-type well region (22) below the second groove (201) is smaller than the thickness of the P-type well region (22) between two adjacent second grooves (201).
3. The semiconductor structure according to claim 2, characterized in that: The P-type ion doping concentration of the P-type well region (22) below the second groove (201) away from the surface of the N-type substrate (10) is greater than the P-type ion doping concentration of the P-type well region (22) between two adjacent second grooves (201) away from the surface of the N-type substrate (10).
4. The semiconductor structure according to claim 2, characterized in that: The thickness of the JFET region (24) below the second groove (201) is smaller than the thickness of the JFET region (24) between two adjacent second grooves (201).
5. The semiconductor structure according to claim 1, characterized in that: Along the channel width direction, the thickness of the N-type source region (23) remains constant.
6. The semiconductor structure according to claim 1, characterized in that: Along the channel width direction, the depth variation trend of the plurality of second grooves (201) includes at least one of the following variation trends: periodic variation, gradual increase, gradual decrease, first increase and then decrease, or first decrease and then increase.
7. The semiconductor structure according to claim 6, characterized in that: Along the channel width direction, the thickness variation trend of the P-type well region (22) below the plurality of second grooves (201) is opposite to the depth variation trend of the plurality of second grooves (201).
8. The semiconductor structure according to claim 1, characterized in that: The depth of the second groove (201) is less than the thickness of the N-type source region (23).
9. The semiconductor structure according to claim 1, characterized in that: The bottom surface of the second groove (201) is a (0001) crystal plane, and the sidewall of the second groove (201) includes at least one of a (1100) crystal plane, a (1010) crystal plane, a (1120) crystal plane or a (0338) crystal plane.
10. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the channel length, the cross-sectional shape of the first groove (101) and the second groove (201) includes at least one of a rectangular shape, a trapezoidal shape, a triangle shape, a bowl shape and an arc shape.
11. The semiconductor structure according to claim 1, characterized in that: A second protrusion (202) is located between two adjacent second grooves (201), and the width of the second protrusion (202) is less than or equal to 1 μm.
12. The semiconductor structure according to claim 11, characterized in that: A first protrusion (102) is disposed between two adjacent first grooves (101), and in a direction perpendicular to the length of the channel, the cross-sectional shapes of the first protrusion (102) and the second protrusion (202) include at least one of a rectangular, a trapezoidal, a triangular, a bowl-shaped, and an arc-shaped.
13. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A source electrode (31) is located on a side of the N-type source region (23) away from the N-type substrate (10); A drain electrode (32) is located on a side of the N-type substrate (10) away from the N-type source region (23); A gate (33) located on a side of the P-type well region (22) and the JFET region (24) away from the N-type substrate (10); A gate oxide layer (34) is located on a side of the gate (33) close to the N-type substrate (10).
14. The semiconductor structure according to claim 13, characterized in that: The material of the gate oxide layer (34) includes at least one of aluminum oxide, aluminum nitride and aluminum oxynitride.
15. The semiconductor structure according to claim 1, characterized in that: The materials of the N-type substrate (10) and the epitaxial layer (20) include silicon carbide.
16. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: S1. Providing an N-type substrate (10), wherein the N-type substrate (10) comprises a first surface and a second surface opposite to each other, wherein the first surface has a plurality of first grooves (101); S2. forming an epitaxial layer (20) on the first surface of the N-type substrate (10), wherein a surface of the epitaxial layer (20) away from the N-type substrate (10) has a plurality of second grooves (201), wherein the second grooves (201) correspond to the first grooves (101) one by one, and the second grooves (201) and the first grooves (101) are parallel to the channel length direction of the semiconductor structure; S3. Ion implantation is performed on a side of the epitaxial layer (20) away from the N-type substrate (10) to form a P-type well region (22); ion implantation is performed on a side of the P-type well region (30) away from the N-type substrate (10) to form an N-type source region (23); the epitaxial layer (20) further comprises an N-type drift region (21) and a JFET region (24) that have not been ion implanted; the N-type drift region (21) is located on a side of the epitaxial layer (20) close to the N-type substrate (10); the JFET region (24) is located on a side of the epitaxial layer (20) away from the N-type substrate (10); and the P-type well region (22) is located on both sides of the JFET region (24).
17. The method for manufacturing a semiconductor structure according to claim 16, characterized in that: The second groove (201) of the epitaxial layer (20) is conformally formed on the first groove (101) of the N-type substrate (10).
18. The method for manufacturing a semiconductor structure according to claim 16, characterized in that: The method of forming the P-type well region (22) by ion implantation comprises: A silicon dioxide mask layer (202) is provided on a side of the epitaxial layer (20) away from the N-type substrate (10), and a side of the silicon dioxide mask layer (202) away from the N-type substrate (10) is a plane; Ion implantation forms a planar P-type well region (22) on one side close to the N-type substrate (10); The silicon dioxide mask layer (202) is removed.
19. The method for manufacturing a semiconductor structure according to claim 16, characterized in that: The thickness of the N-type source region (23) formed by ion implantation is constant.
20. The method for manufacturing a semiconductor structure according to claim 16, characterized in that: The step S3 further comprises: S4, conformally preparing a gate oxide layer (34) on a side of the P-type well region (22) and the JFET region (24) away from the N-type substrate (10). S5. Prepare a source electrode (31) on a side of the N-type source region (23) away from the N-type substrate (10), prepare a drain electrode (32) on a side of the N-type substrate (10) away from the N-type source region (23), and prepare a gate electrode (33) on a side of the gate oxide layer (34) away from the N-type substrate (10).