Semiconductor discharge lamp and power supply circuit

Abstract

The application discloses a semiconductor discharge tube and a power supply circuit. The semiconductor discharge tube comprises a first part and a second part of a semiconductor body, wherein each of the first part and the second part comprises a first region, a second region, a third region and a fourth region. The first region and the second region are in the same layer and are arranged with the third region in between. The fourth region comprises a plurality of fourth sub-regions arranged in between. The fourth region is in contact with the third region, and the fourth region is located in the vertical projection of the third region on the fourth region. The first region is in contact with the third region, and the vertical projection of the first region on the third region is located in the third region. The vertical projection of the first region on the fourth region does not overlap with the fourth sub-regions. The second region is in contact with the third region, and the vertical projection of the second region on the fourth region does not overlap with the fourth sub-regions. The first part and the second part are symmetrically arranged, and the vertical projection of the fourth region of the first part on the fourth region of the second part does not overlap with the fourth region of the second part. The application can increase the initial conduction area of the device and improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor discharge tube and a power supply circuit. Background Technology

[0002] A semiconductor discharge tube (TSS) is a PNPN junction four-layer structure device fabricated using semiconductor technology. Its internal structure contains three PN junctions: J1 (N1P1), J2 (P1N2), and J3 (N2P2). When a positive voltage is applied to P2 and a negative voltage to N1, junctions J1 and J3 are forward biased, while junction J2 is reverse biased. Due to the very low breakdown voltage of the heavily doped J1 junction, junction J3 withstands almost the entire external voltage. This structural design allows the TSS to conduct rapidly under overvoltage conditions, protecting downstream circuitry from damage. Figure 1 This is a schematic diagram of the structure of a semiconductor discharge tube in the prior art, for reference. Figure 1 , Figure 1 The TSS in the design adopts an antisymmetric structure, with P region 1 and N+ region 2 being antisymmetric structures. However, the initial conduction area of ​​the existing structure is small, resulting in poor device reliability. Summary of the Invention

[0003] This invention provides a semiconductor discharge tube and power supply circuit, which can increase the initial conduction area of ​​the device and improve the reliability of the device.

[0004] According to one aspect of the present invention, a semiconductor discharge tube is provided, comprising:

[0005] The semiconductor body is of a first conductivity type and includes a first surface and a second surface disposed opposite to each other. Along a first direction, the semiconductor body is divided into a first part and a second part, with the surface of the first part away from the second part being the first surface and the surface of the second part away from the first part being the second surface. Both the first and second parts include a first region, a second region, a third region, and a fourth region. The first and second regions are on the same layer and are separated by a third region. The first region is located on the first surface, and the fourth region is located on the side of the third region away from the first region. The fourth region includes multiple spaced-apart fourth sub-regions, and the fourth region is in contact with the third region. The vertical projection of the fourth region onto the third region lies within the third region; the first region is in contact with the third region, and the vertical projection of the first region onto the third region lies within the third region, while the vertical projection of the first region onto the fourth region does not overlap with the fourth sub-region; the second region is in contact with the third region, and the vertical projection of the second region onto the third region partially overlaps with the third region, while the vertical projection of the second region onto the fourth region does not overlap with the fourth sub-region; the first and second regions are of the first conductivity type, and the third and fourth regions are of the second conductivity type; the first part and the second part are symmetrically arranged, and the vertical projection of the fourth region of the first part onto the fourth region of the second part does not overlap with the fourth region of the second part;

[0006] The first electrode is located on the first surface and is in contact with the first region and part of the third region of the first part. The first electrode is insulated from the second region of the first part.

[0007] The second electrode is located on the second surface and is in contact with the first region and part of the third region of the second part. The second electrode is insulated from the second region of the second part.

[0008] Optionally, the second region includes a first diffusion region, multiple second diffusion regions, and multiple third diffusion regions; along a second direction, the second diffusion region is located between the first diffusion region and the third diffusion region, and the second direction is the direction from the first diffusion region to the third diffusion region;

[0009] The first diffusion region is located at the edge of the first surface of the semiconductor body. The first diffusion region surrounds the first region. The vertical projection of the first diffusion region into the third region does not overlap with the third region.

[0010] Multiple second diffusion zones have a first side and a second side arranged opposite to each other, with the first side contacting the first diffusion zone and the second side contacting the third zone; the vertical projection of the second diffusion zone into the third zone partially overlaps with the third zone.

[0011] Multiple third diffusion zones are spaced apart along the first diagonal direction; the vertical projection of the third diffusion zone onto the third zone is located within the third zone.

[0012] Optionally, the multiple fourth sub-regions include multiple edge fourth sub-regions and multiple other fourth sub-regions, with the multiple edge fourth sub-regions surrounding the other fourth sub-regions; the other fourth sub-regions are located on the side of the edge fourth sub-regions that is far from the vertical projection of the second diffusion region into the fourth region;

[0013] The vertical projection of the second diffusion zone into the fourth zone lies on the perpendicular bisector of the line connecting the centers of the adjacent edge fourth sub-zones.

[0014] Optionally, the multiple fourth sub-regions include multiple fourth diffusion regions and multiple fifth diffusion regions;

[0015] Along the second diagonal direction, multiple fourth diffusion zones are arranged sequentially, each fourth diffusion zone corresponding to a third diffusion zone; the center of the fourth diffusion zone and the center of the vertical projection of the corresponding third diffusion zone in the fourth zone are located on the first straight line; the first straight line is parallel to the second direction.

[0016] The vertical projection of the third diffusion zone of the first part onto the fourth diffusion zone of the second part is located inside the fourth diffusion zone of the second part; the vertical projection of the third diffusion zone of the second part onto the fourth diffusion zone of the first part is located inside the fourth diffusion zone of the first part.

[0017] Optionally, the area of ​​each third diffusion region is smaller than the area of ​​each fourth diffusion region.

[0018] Optionally, the shape of the third diffusion region may include a circle; the diameter of the circle is greater than 100 μm.

[0019] Optionally, the semiconductor discharge tube also includes:

[0020] An insulating layer is located on one side of the first and second surfaces of the semiconductor body; the insulating layer at least covers the third diffusion region, and the vertical projection of the insulating layer into the first region does not overlap with the first region.

[0021] Optionally, the distance between adjacent fourth sub-regions is greater than 200 μm; or the distance between adjacent fourth sub-regions is the same.

[0022] Optionally, the doping concentration of the third region is greater than that of the second region, and the doping concentration of the first region is greater than that of the semiconductor body.

[0023] According to another aspect of the present invention, a power supply circuit is provided, including the semiconductor discharge tube described in any embodiment of the present invention.

[0024] The semiconductor body provided in this embodiment of the invention is of a first conductivity type and includes a first surface and a second surface disposed opposite to each other. Along a first direction, the semiconductor body is divided into a first part and a second part. The surface of the first part away from the second part is the first surface, and the surface of the second part away from the first part is the second surface. Both the first and second parts include a first region, a second region, a third region, and a fourth region. The first and second regions are on the same layer and are separated by a third region. The first region is located on the first surface, and the fourth region is located on the side of the third region away from the first region. The fourth region includes multiple spaced-apart fourth sub-regions. The fourth region is in contact with the third region, and the vertical projection of the fourth region onto the third region is located within the third region. The first region is in contact with the third region, and the vertical projection of the first region onto the third region is located within the third region. The vertical projection of the first region into the fourth region does not overlap with the fourth sub-region; the second region contacts the third region, and the vertical projection of the second region into the third region partially overlaps with the third region, while the vertical projection of the second region into the fourth region does not overlap with the fourth sub-region; the first and second regions are of the first conductivity type, and the third and fourth regions are of the second conductivity type; the first and second parts are symmetrically arranged, and the vertical projection of the fourth region of the first part into the fourth region of the second part does not overlap with the fourth region of the second part; the first electrode is located on the first surface, and it contacts the first region and part of the third region of the first part, while being insulated from the second region of the first part; the second electrode is located on the second surface, and it contacts the first region and part of the third region of the second part, while being insulated from the second region of the second part. In this embodiment of the invention, by setting the portion of the second region that contacts the third region as a breakdown point, the number of breakdown points is increased, resulting in a larger initial conductive area of ​​the device, and a more uniform current flow in the middle of the edges of the breakdown point distribution, thus improving the reliability of the device.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a semiconductor discharge tube in the prior art.

[0028] Figure 2 This is a schematic diagram of the structure of a semiconductor discharge tube provided in an embodiment of the present invention.

[0029] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along section line A1A2.

[0030] Figure 4 This is a schematic diagram of the intermediate structure of a semiconductor discharge tube according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention.

[0034] Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure along section line B1B2. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] This invention provides a semiconductor discharge tube. Figure 2 This is a schematic diagram of the structure of a semiconductor discharge tube provided in an embodiment of the present invention. Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along section line A1A2. Figure 4This is a schematic diagram of the intermediate structure of a semiconductor discharge tube according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention, see reference. Figures 2-7 The semiconductor discharge tube includes:

[0038] The semiconductor body 10 is of a first conductivity type and includes a first surface 01 and a second surface 02 disposed opposite to each other. Along a first direction X, the semiconductor body 10 is divided into a first portion 03 and a second portion 04. The surface of the first portion 03 away from the second portion 04 is the first surface 01, and the surface of the second portion 04 away from the first portion 03 is the second surface 02. Both the first portion 11 and the second portion 12 include a first region 11, a second region 12, a third region 13, and a fourth region 14. The first region 11 and the second region 12 are on the same layer and are separated from each other by the third region 13. The first region 11 is located on the first surface 01, and the fourth region 14 is located on the side of the third region 13 away from the first region 11. The fourth region 14 includes multiple spaced-apart fourth sub-regions 15, and the fourth region 14 and the third region 13... The fourth region 14 is in contact with the third region 13, and its vertical projection is located within the third region 13. The first region 11 is in contact with the third region 13, and its vertical projection is located within the third region 13. The vertical projection of the first region 11 in the fourth region 14 does not overlap with the fourth sub-region 15. The second region 12 is in contact with the third region 13, and its vertical projection partially overlaps with the third region 13. The vertical projection of the second region 12 in the fourth region 14 does not overlap with the fourth sub-region 15. The first region 11 and the second region 12 are of the first conductivity type, and the third region 13 and the fourth region 14 are of the second conductivity type. The first part 03 and the second part 04 are symmetrically arranged, and the vertical projection of the fourth region 14 of the first part 03 does not overlap with the fourth region 14 of the second part 04.

[0039] The first electrode 20 is located on the first surface 01. The first electrode 20 is in contact with the first region 11 and part of the third region 13 of the first part 03. The first electrode 20 is insulated from the second region 12 of the first part 03.

[0040] The second electrode 30 is located on the second surface 02. The second electrode 30 is in contact with the first region 11 and part of the third region 13 of the second part 04. The second electrode 30 is insulated from the second region 12 of the second part 04.

[0041] In this configuration, the first conductivity type is N-type, the second conductivity type is P-type, the first electrode 20 is negatively charged, and the second electrode 30 is positively charged; or, the first conductivity type is P-type, the second conductivity type is N-type, the first electrode 20 is positively charged, and the second electrode 30 is negatively charged. For example, the conductivity type of the semiconductor body is N-type, and the first region 11, the second region 12, the third region 13, and the fourth region 14 are all formed by different ion doping processes in the semiconductor body. The first region 11 and the second region 12 are formed simultaneously, and the conductivity types of the first region 11 and the second region 12 are both N+ type. The conductivity type of the third region 13 is P+ type, and the conductivity type of the fourth region 14 is P-type. The implantation depth of the fourth region 14 is greater than the implantation depth of the third region 13.

[0042] The first direction X is the thickness direction of the semiconductor discharge tube. The semiconductor body 10 is divided into upper and lower parts, namely the first part 03 and the second part 04. The first part 03 and the second part 04 are symmetrically arranged and are flipped 180° to each other. That is, the first part 03 is a structure of the second part 04 flipped 180°, and the second part 04 is a structure of the first part 03 flipped 180°. The first part 03 and the second part 04 are centrally symmetrically arranged. For example, refer to Figure 6 and Figure 7 , Figure 6 This is a top view of the first surface of the semiconductor body 10. Figure 7 This is a top view of the second surface of the semiconductor body, with the first part 03 and the fourth part 04 arranged symmetrically.

[0043] refer to Figure 3 Along the direction from the second surface 02 to the first surface 01, i.e., the first direction X, the semiconductor body 10 is sequentially provided with the first region 11 and the second region 12 of the second part 04, the third region 13 of the second part 04, the fourth region 14 of the second part 04, the fourth region 14 of the first part 03, the third region 13 of the first part, and the first region 11 and the second region 12 of the first part 03; the first part 03 and the second part 04 have the same structure but different positions and are arranged symmetrically.

[0044] Specifically, the first part 03 includes a first region 11, a second region 12, a third region 13, and a fourth region 14, and the second part 04 includes a first region 11, a second region 12, a third region 13, and a fourth region 14. The first region 11, the second region 12, the third region 13, and the fourth region 14 of the second part 04 are obtained by flipping the first region 11, the second region 12, the third region 13, and the fourth region 14 of the first part 03. The vertical projection of the fourth region 14 of the first part 03 onto the fourth region 14 of the second part 04 does not overlap with the fourth region 14 of the second part 04. The vertical projection of each fourth region 14 of the second part 04 onto the fourth region 14 of the first part 03 is located between adjacent fourth sub-regions 15. The parts of the second region 12 that contact the third region 13 are all breakdown points, which increases the area of ​​the breakdown points and increases the initial conduction area of ​​the device. The initial conduction area of ​​the device determines the current withstand capability, which can improve the current withstand capability of the device. This makes the current flow in the middle of the edge of the breakdown point distribution uniform and improves the reliability of the device.

[0045] Existing semiconductor discharge tubes often employ a semi-symmetrical layout. While this structure is simple and intuitive, it struggles to achieve optimal space configuration when faced with size constraints or specific performance requirements. Furthermore, the semi-symmetrical layout can introduce design imbalances, impacting the overall chip performance. This invention proposes a novel drawing method for designing semiconductor discharge tubes, using a matrix-based approach to layout. This matrix arrangement maximizes the utilization of the active region area, resulting in highly efficient space utilization.

[0046] refer to Figure 4 When designing a semiconductor discharge tube, the dimensions of the device's perimeter must be clearly defined as the basis for subsequent layout. The dimensions of the second region 12, i.e., the large blank area along the first diagonal direction Z1, are pre-designed. The range of the fourth region 14 is designed based on the reserved dimensions of the second region 12. The fourth region 14 is designed with a matrix arrangement, and multiple patterns can be removed by equidistant staggering to ensure that the fourth region can effectively utilize space and avoid waste. For example, multiple patterns can be removed by equidistant staggering, which can set multiple fourth sub-regions 15 at equal intervals. The multiple fourth sub-regions 15 include the fourth sub-region 1, the fourth sub-region 2, and the fourth sub-region 3. Under the condition of ensuring the normal operation of the device, the adjacent spacing of the fourth sub-region 1, the fourth sub-region 2, and the fourth sub-region 3 is set to be the same. The fourth sub-region 2 of the first part 03 can be removed. The position of the removed fourth sub-region 2 corresponds to a fourth sub-region 15 of the second part 04, which can ensure effective use of space and set up a symmetrical first part 03 and second part 04.

[0047] In a semiconductor discharge tube, reference Figure 5The third zone 13 covers the fourth zone 14. Both the third zone 13 and the fourth zone 14 are designed with reserved space. The reserved space of the third zone 13 is smaller than that of the fourth zone 14. The second zone 12 will be formed in the reserved space. If the second zone 12 is an N+ zone, electrons can be emitted in the reserved space to form part of the pattern of the second zone 12. The fourth zone 14 and the second zone 12 are separated by the third zone 13 to ensure that each zone does not interfere with each other and the layout is compact, thereby further improving the space utilization rate.

[0048] The semiconductor body 10 provided in this embodiment of the invention is of a first conductivity type. The semiconductor body 10 includes a first surface 01 and a second surface 02 disposed opposite to each other. Along a first direction X, the semiconductor body 10 is divided into a first part 03 and a second part 04. The surface of the first part 03 away from the second part 04 is the first surface 01, and the surface of the second part 04 away from the first part 03 is the second surface 02. Both the first part 11 and the second part 12 include a first region 11, a second region 12, a third region 13, and a fourth region 14. The first region 11 and the second region 12 are on the same layer and are separated by the third region 13. The first region 11 is located on the first surface 01, and the fourth region 14 is located on the side of the third region 13 away from the first region 11. The fourth region 14 includes multiple spaced-apart fourth sub-regions 15. The fourth region 14 is in contact with the third region 13, and the vertical projection of the fourth region 14 onto the third region 13 is located within the third region 13. The first region 11 is in contact with the third region 13, and the vertical projection of the first region 11 onto the third region 13 is located within the third region 13. The vertical projection of region 11 in the fourth region 14 does not overlap with the fourth sub-region 15; the second region 12 is in contact with the third region 13, the vertical projection of the second region 12 in the third region 13 partially overlaps with the third region 13, and the vertical projection of the second region 12 in the fourth region 14 does not overlap with the fourth sub-region 15; the first region 11 and the second region 12 are of the first conductivity type, and the third region 13 and the fourth region 14 are of the second conductivity type; the first part 03 and the second part 04 are symmetrically arranged, and the fourth region 14 of the first part 03 is in the fourth region 1 of the second part 04. The vertical projection of 4 does not overlap with the fourth region 14 of the second part 04; the first electrode 20 is located on the first surface 01, and contacts the first region 11 and part of the third region 13 of the first part 03, and is insulated from the second region 12 of the first part 03; the second electrode 30 is located on the second surface 02, and contacts the first region 11 and part of the third region 13 of the second part 04, and is insulated from the second region 12 of the second part 04. In this embodiment of the invention, by setting the portions of the second region 12 that contact the third region 13 as breakdown points, the number of breakdown points is increased, thereby increasing the initial conduction area of ​​the device and making the current flow more uniform in the middle of the edges of the breakdown point distribution, thus improving the reliability of the device.

[0049] Optional, Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure along section lines B1B2, for reference. Figure 6 and Figure 8 The second region 12 includes a first diffusion region 121, a plurality of second diffusion regions 122 and a plurality of third diffusion regions 123; along the second direction Y, the second diffusion region 122 is located between the first diffusion region 121 and the third diffusion region 123, and the second direction Y is the direction from the first diffusion region 121 to the third diffusion region 123;

[0050] The first diffusion region 121 is located at the edge of the first surface 01 of the semiconductor body 10. The first diffusion region 121 surrounds the first region 11. The vertical projection of the first diffusion region 121 in the third region 13 does not overlap with the third region 13. A plurality of second diffusion regions 122 have a first side and a second side arranged opposite to each other. The first side contacts the first diffusion region 121, and the second side contacts the third region 13. The vertical projection of the second diffusion region 122 in the third region 13 partially overlaps with the third region 13. A plurality of third diffusion regions 123 are arranged at intervals along the first diagonal Z1 direction. The vertical projection of the third diffusion region 123 in the third region 13 is located within the third region 13.

[0051] Wherein, the second direction Y is the length direction of the semiconductor discharge tube; the first diffusion region 121 is in contact with a plurality of second diffusion regions 122, the plurality of second diffusion regions 122 are spaced apart, the pattern formed by the first diffusion region 121 and the plurality of contacting second diffusion regions 122 surrounds the first region, the first diffusion region 121 and the plurality of second diffusion regions 122 are spaced apart from the third diffusion region 123; the spacing between adjacent third diffusion regions 123 is set according to the preset size of the semiconductor discharge tube, and the spacing between adjacent third diffusion regions 123 can be the same or different.

[0052] The first diffusion region 121 can effectively enhance the current diffusion capability, prevent excessive current concentration in local areas, improve the reliability of the device under high current conditions, and prevent device failure due to excessive local temperature due to more uniform current distribution, thus extending the device's service life. When the voltage reaches the break-through voltage or breakdown voltage, the second diffusion region 122 and the third diffusion region 123 are both breakdown points, which can form an initial conduction channel in the device, increasing the initial conduction area of ​​the device. The current flow in the middle of the edge of the breakdown point distribution is uniform, improving the reliability of the device.

[0053] Optional, see reference Figure 4 and Figure 6The multiple fourth sub-regions 15 include multiple edge fourth sub-regions and multiple other fourth sub-regions, with the multiple edge fourth sub-regions surrounding the other fourth sub-regions; the other fourth sub-regions are located on the side of the edge fourth sub-regions away from the vertical projection of the second diffusion region 122 in the fourth region 14; the vertical projection of the second diffusion region 122 in the fourth region 14 is located on the perpendicular line of the line connecting the centers of adjacent edge fourth sub-regions.

[0054] Among them, the outermost ring of fourth sub-regions is the edge fourth sub-region 15. Multiple other fourth sub-regions are located inside the pattern enclosed by multiple edge fourth sub-regions. The reserved area of ​​the fourth region 14 in the first diagonal direction Z1 can be used to form the third diffusion region 123 later. The vertical projection of the second diffusion region 122 on the fourth region 14 is located on the perpendicular bisector of the line connecting the centers of adjacent edge fourth sub-regions. This can make the initial conduction area of ​​the semiconductor discharge tube larger and improve the reliability of the device.

[0055] Optional, see reference Figure 6 and Figure 8 The plurality of fourth sub-regions 15 include a plurality of fourth diffusion regions 151 and a plurality of fifth diffusion regions 152; the plurality of fourth diffusion regions 151 are arranged sequentially along the second diagonal direction Z2, and each fourth diffusion region 151 corresponds to a third diffusion region 123; the center of the fourth diffusion region 151 and the center of the corresponding third diffusion region 123 in the vertical projection of the fourth region 14 are located on the first straight line C1C2; the first straight line C1C2 is parallel to the second direction Y; the third diffusion region 123 of the first part 03 is located inside the fourth diffusion region 151 of the second part 04 in the vertical projection of the fourth diffusion region 151 of the second part 04; the third diffusion region 123 of the second part 04 is located inside the fourth diffusion region 151 of the first part 03 in the vertical projection of the fourth diffusion region 151 of the first part 03.

[0056] The fifth diffusion region 152 has a size of 100μm-200μm, and the spacing between adjacent fifth diffusion regions 152 can be equal, thus enabling the array arrangement of the fifth diffusion regions 152. Space needs to be reserved in the design of the third region 13 and the fourth region 14 to form the third diffusion region 123. The third diffusion region 123 in the first part 03 corresponds to the fourth diffusion region 151 in the second part 04, and vice versa. The area of ​​the fourth diffusion region 151 is larger than the area of ​​the third diffusion region 123. If the third diffusion region 123 is circular, the shape of the fourth diffusion region 151 can be the area of ​​multiple fifth diffusion regions 152 connected together. The area of ​​the third diffusion region 123 is smaller than the maximum circular area included in the fourth diffusion region 151, ensuring that each region does not interfere with each other and the layout is compact. Furthermore, the third diffusion region 123 is a breakdown point, which can increase the initial conduction area of ​​the device and improve its reliability.

[0057] Optionally, the area of ​​each third diffusion region is smaller than the area of ​​each fourth diffusion region.

[0058] The area of ​​each third diffusion zone is smaller than that of each fourth diffusion zone, which ensures that each zone does not interfere with each other and that the layout is compact.

[0059] Optionally, the shape of the third diffusion region may include a circle; the diameter of the circle is greater than 100 μm.

[0060] The third diffusion region can be circular in shape. Circular shapes are regular and have simple manufacturing processes. If the diameter of the circle is less than 100μm, the initial conduction area will be small, which will lead to poor device reliability and easy damage to the device. Therefore, setting the diameter of the circle to be greater than 100μm can ensure that the initial conduction area of ​​the device is large and ensure the reliability of the device.

[0061] Optional, see reference Figure 3 , Figure 6 and Figure 8 The semiconductor discharge tube further includes an insulating layer 40, which is located on one side of the first surface 01 and the second surface 02 of the semiconductor body 10; the insulating layer 40 at least covers the third diffusion region 123, and the vertical projection of the insulating layer 40 on the first region 11 does not overlap with the first region 11.

[0062] The insulating layer 40 is made of silicon nitride or silicon oxide and is used to isolate the first electrode 20 and the second electrode 30 from the second region 12. The insulating layer 40 can be covered on the first surface 01 and the second surface 02. Then, the hole area of ​​the insulating layer 40 is formed by patterning. The electrodes are designed according to the position areas of the first region 11, the second region 12 and the third region 13. The first electrode 20 and the second electrode 30 are electrically connected to the first region 11 through the hole area. The first electrode 20 and the second electrode 30 are both metal electrodes.

[0063] Optionally, the distance between adjacent fourth sub-regions is greater than 200 μm; or the distance between adjacent fourth sub-regions is the same.

[0064] Among them, the distance between adjacent fourth sub-regions is greater than 200μm; the distance between adjacent fourth sub-regions is the same, which can realize the array arrangement of the fourth sub-regions and further improve the space utilization.

[0065] Optionally, the doping concentration of the third region is greater than that of the second region, and the doping concentration of the first region is greater than that of the semiconductor body.

[0066] The doping concentration of the third region is greater than that of the second region, and the doping concentration of the first region is greater than that of the semiconductor body. The doping concentration of each region can be set according to the requirements to adjust the conduction characteristics of the semiconductor discharge tube.

[0067] Based on the above embodiments, this invention provides a power supply circuit, including the semiconductor discharge tube described in any embodiment of this invention.

[0068] The power supply circuit provided by the technical solution of this invention has the same beneficial effects as the semiconductor discharge tube described in any embodiment of this invention.

[0069] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0070] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor discharge tube, characterized in that, include: A semiconductor body, wherein the semiconductor body is of a first conductivity type, and the semiconductor body includes a first surface and a second surface disposed opposite to each other; Along a first direction, the semiconductor body is divided into a first part and a second part. The surface of the first part away from the second part is a first surface, and the surface of the second part away from the first part is a second surface. Both the first part and the second part include a first region, a second region, a third region, and a fourth region. The first region and the second region are on the same layer and are separated from the third region. The first region is located on the first surface, and the fourth region is located on the side of the third region away from the first region. The fourth region includes a plurality of spaced-apart fourth sub-regions. The fourth region is in contact with the third region, and the vertical projection of the fourth region onto the third region is located within the third region. The first region is in contact with the third region, and the vertical projection of the first region in the third region is located within the third region. The vertical projection of the first region in the fourth region does not overlap with the fourth sub-region. The second region is in contact with the third region, and the vertical projection of the second region in the third region partially overlaps with the third region. The vertical projection of the second region in the fourth region does not overlap with the fourth sub-region. The first region and the second region are of a first conductivity type, and the third region and the fourth region are of a second conductivity type. The first part and the second part are symmetrically arranged, and the vertical projection of the fourth region of the first part in the fourth region of the second part does not overlap with the fourth region of the second part. A first electrode is located on the first surface, and the first electrode is in contact with the first region and part of the third region of the first portion, and the first electrode is insulated from the second region of the first portion. The second electrode is located on the second surface and is in contact with the first region and part of the third region of the second portion. The second electrode is insulated from the second region of the second portion.

2. The semiconductor discharge tube according to claim 1, characterized in that, The second region includes a first diffusion region, a plurality of second diffusion regions, and a plurality of third diffusion regions; along a second direction, the second diffusion region is located between the first diffusion region and the third diffusion region, and the second direction is the direction from the first diffusion region to the third diffusion region; The first diffusion region is located at the edge of the first surface of the semiconductor body, the first diffusion region surrounds the first region, and the vertical projection of the first diffusion region in the third region does not overlap with the third region; The plurality of second diffusion zones have a first side and a second side disposed opposite to each other, the first side being in contact with the first diffusion zone and the second side being in contact with the third zone; the vertical projection of the second diffusion zone in the third zone partially overlaps with the third zone; Along the first diagonal direction, a plurality of the third diffusion regions are spaced apart; the vertical projection of the third diffusion region in the third region is located within the third region.

3. The semiconductor discharge tube according to claim 2, characterized in that, The plurality of fourth sub-regions include a plurality of edge fourth sub-regions and a plurality of other fourth sub-regions, the plurality of edge fourth sub-regions surrounding the other fourth sub-regions; the other fourth sub-regions are located on the side of the edge fourth sub-regions away from the vertical projection of the second diffusion region in the fourth region; The vertical projection of the second diffusion region in the fourth region lies on the perpendicular bisector of the line connecting the centers of the adjacent edge fourth sub-regions.

4. The semiconductor discharge tube according to claim 2, characterized in that, The plurality of fourth sub-regions include a plurality of fourth diffusion regions and a plurality of fifth diffusion regions; Along the second diagonal direction, multiple fourth diffusion zones are arranged sequentially, each fourth diffusion zone corresponding to one of the third diffusion zones; the center of the fourth diffusion zone and the center of the vertical projection of the corresponding third diffusion zone in the fourth zone are located on a first straight line; the first straight line is parallel to the second direction. The vertical projection of the third diffusion region of the first part onto the fourth diffusion region of the second part is located inside the fourth diffusion region of the second part; the vertical projection of the third diffusion region of the second part onto the fourth diffusion region of the first part is located inside the fourth diffusion region of the first part.

5. The semiconductor discharge tube according to claim 4, characterized in that, The area of ​​each of the third diffusion regions is smaller than the area of ​​each of the fourth diffusion regions.

6. The semiconductor discharge tube according to claim 5, characterized in that, The third diffusion region has a circular shape; the diameter of the circle is greater than 100 μm.

7. The semiconductor discharge tube according to claim 2, characterized in that, Also includes: An insulating layer is located on one side of the first surface and the second surface of the semiconductor body; The insulating layer at least covers the third diffusion region, and the vertical projection of the insulating layer in the first region does not overlap with the first region.

8. The semiconductor discharge tube according to claim 1, characterized in that, The distance between adjacent fourth sub-regions is greater than 200 μm; the distance between adjacent fourth sub-regions is the same.

9. The semiconductor discharge tube according to claim 1, characterized in that, The doping concentration of the third region is greater than that of the second region, and the doping concentration of the first region is greater than that of the semiconductor body.

10. A power supply circuit, characterized in that, Includes the semiconductor discharge tube according to any one of claims 1-9.

Images