Enhanced power device adopting ferroelectric stacked gate dielectric and preparation method thereof

Abstract

The invention discloses an enhanced power device adopting a ferroelectric stacked gate dielectric and a preparation method of the enhanced power device. The device comprises an AlGaN / GaN heterojunction epitaxial layer, a source electrode, a drain electrode, a ferroelectric stacked gate dielectric passivation layer and a gate electrode. According to the device, a certain depth of etching is carried out on the whole epitaxial barrier layer, the distance from a ferroelectric lamination layer to a channel is shortened, and the enhancement performance is promoted to be realized. The ferroelectric stacked gate dielectric passivation layer is located on the barrier layer, the first layer is a 3-5nm high-k thin layer in contact with a barrier, a hafnium oxide / zirconium oxide multi-layer overlapping structure is arranged on the first layer, the top of the ferroelectric stacked gate dielectric passivation layer is made of a high-k material similar to the overlapping structure in thickness, the top structure has good electric leakage suppression capacity, stress is applied to the overlapping structure in the annealing process, and the thickness of the high-k thin layer is larger than that of the overlapping structure. And formation of a ferroelectric crystal phase in the overlapping structure is facilitated. The gate electric leakage of the enhanced device is reduced, the channel electron mobility is not influenced, the process complexity for realizing the enhanced device is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to an enhanced power device using a ferroelectric stacked gate dielectric and a preparation method thereof. Background Art

[0002] Because of its unique lateral structure and polarization effect, GaN-based HEMT can form a layer of high-concentration, high-mobility two-dimensional electron gas on the side of its channel layer biased against the barrier layer, so that HEMT devices can be used in high-current situations. With the development of electronic circuits, enhanced (normally closed) HEMTs have become a development trend. The number of devices controlling the switch at the front end is reduced, and a single enhanced HEMT device switch can be controlled by simply changing the voltage applied to the gate. The circuit has been greatly simplified and the manufacturing cost can be further reduced. At present, the main ways to realize enhanced devices are gate groove technology, fluorine ion implantation technology, and p-GaN gate technology. In order to achieve a higher threshold voltage, the gate groove technology requires a larger depth of etching of the barrier layer under the gate, which greatly weakens the polarization effect and damages the conductive channel. While the device obtains a higher threshold voltage, the on-current drops seriously, affecting the use of the device in the circuit. Fluorine ion implantation technology, by injecting electronegative fluorine ions into the barrier under the gate to deplete the two-dimensional electron gas in the channel under the gate to achieve a positive shift in the threshold voltage, but fluorine ions are unstable at high temperatures, which will cause threshold voltage degradation. The p-GaN gate technology introduces upward band bending through the p-GaN layer under zero gate bias and depletes the 2-DEG channel, thereby realizing an enhancement-mode device. However, the p-GaN layer needs to be etched during the device preparation process, which places high demands on process control and can easily cause problems such as uneven etching and etching damage.

[0003] In summary, the current technology for realizing enhancement-mode devices has problems such as damage to the barrier under the gate, which reduces the current, poor gate leakage suppression performance, high process complexity and poor repeatability. In order to reduce process complexity and reduce damage to barrier etching, polar gate dielectric technology has been proposed. The channel electron gas density can be enhanced or weakened by polarization in different directions. For example, applying a positive gate voltage to form polarization in the dielectric layer under the gate weakens the polarization effect of the barrier layer under the gate and the channel layer, thereby achieving a positive shift in the threshold voltage. In applications, a large gate voltage needs to be applied to form a strong polarization effect to achieve the depletion of the channel electron gas, and since the oxygen vacancies inside the dielectric layer are prone to form conductive channels after ferroelectric polarization, it is impossible to achieve good gate leakage suppression. Therefore, it is necessary to appropriately thin the barrier layer to promote its weakening effect on the channel polarization, reduce the gate voltage that causes polarization, and combine polar media with non-polar media to improve the gate leakage suppression performance of the device. Summary of the invention

[0004] Based on this, the present invention proposes an enhanced power device using a ferroelectric stacked gate dielectric. By etching the potential barrier to a certain depth, selecting an optimized ferroelectric stacked gate dielectric passivation layer, and performing appropriate annealing, a high-k gate dielectric film with ferroelectricity is formed, and etching damage can be repaired to achieve an enhanced GaN-based HEMT device with high on-current.

[0005] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0006] An enhanced power device using a ferroelectric stacked gate dielectric includes, from bottom to top, a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104, and a ferroelectric stacked gate dielectric passivation layer 105:

[0007] The barrier layer 104 is etched to a certain depth as a whole. The first layer of the ferroelectric stacked gate dielectric passivation layer is a 3-5 nm dielectric layer in contact with the barrier layer, above which is a hafnium oxide / zirconium oxide overlapping structure, and the top is a dielectric layer with a thickness similar to the overlapping structure.

[0008] Furthermore, the enhanced power device using a ferroelectric stacked gate dielectric is characterized in that the non-overlapping structure dielectric layer in the ferroelectric stacked gate dielectric passivation layer 105 is a high-k metal oxide, including but not limited to one or more oxides such as HfO2, ZrO2, Al2O3, etc.

[0009] Furthermore, the enhancement-mode power device using a ferroelectric stacked gate dielectric is characterized in that the HfO2 / ZrO2 overlapping structure in the ferroelectric stacked gate dielectric passivation layer 105 is a five-layer or seven-layer overlapping structure.

[0010] Furthermore, the enhancement-mode power device using a ferroelectric stacked gate dielectric is characterized in that the starting layer of the HfO2 / ZrO2 overlapping structure in the ferroelectric stacked gate dielectric passivation layer 105 is a metal oxide different from the barrier contact dielectric layer.

[0011] Furthermore, the enhancement-mode power device using the ferroelectric stacked gate dielectric is characterized in that the thickness of the ferroelectric stacked gate dielectric passivation layer 105 is 20-40 nm.

[0012] Furthermore, the enhancement-mode power device using a ferroelectric stacked gate dielectric is characterized in that the substrate 101 is silicon, and the buffer layer 102 is C- or Fe-doped GaN.

[0013] Furthermore, the enhancement-mode power device using ferroelectric stacked gate dielectric is characterized in that the channel layer 103 is GaN, and the barrier layer 104 is AlGaN or AlN. The barrier layer has a thickness of 12 to 30 nm, and the barrier layer is etched as a whole to have a thickness of 12 to 20 nm.

[0014] The method of an enhancement mode power device using a ferroelectric stacked gate dielectric is characterized by comprising the following steps:

[0015] S1. Soak the AlGaN / GaN heterojunction epitaxial layer in a solution of H2SO4:H2O2=3:1 (mass ratio) for 10 minutes to remove the unstable epitaxial oxide layer on the surface. Then use acetone and isopropyl alcohol to remove organic matter on the AlGaN / GaN heterojunction epitaxial layer.

[0016] S2. Etching the barrier layer as a whole to make it 12-20 nm thick, reducing the distance from the ferroelectric layer to the channel and promoting the realization of enhanced performance.

[0017] S3, defining the active area pattern by photolithography, removing the barrier layer and the channel layer in the heterojunction by etching isolation to form an independent active area, wherein the etching depth is greater than the thickness of the barrier layer and the channel layer;

[0018] S4, defining the metal position and pattern of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 500° C. to 800° C. in a vacuum or nitrogen atmosphere, so that the source and drain electrodes form ohmic contacts with the barrier layer;

[0019] S5. Deposit a ferroelectric stacked gate dielectric passivation layer by magnetron sputtering, and anneal at 400°C to 600°C for 30s to 60s in a nitrogen atmosphere to form a high-k gate dielectric passivation layer with ferroelectricity, improve the quality of the gate dielectric passivation layer, and repair etching damage.

[0020] S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

[0021] Compared with the prior art, the present invention has the following beneficial effects and advantages:

[0022] The present invention adopts a barrier etching method combined with a ferroelectric stacked gate dielectric method to realize the preparation of an enhanced GaN-based HEMT device, etches the epitaxial barrier layer as a whole to a certain depth, shortens the distance from the ferroelectric stack to the channel, and promotes the realization of enhanced performance. The ferroelectric stacked gate dielectric can well suppress gate leakage and improve the reliability of the enhanced device. The present invention adopts magnetron sputtering to deposit the ferroelectric stacked gate dielectric passivation layer, reduces the process temperature of the dielectric growth, and improves the process compatibility of the dielectric growth. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of a ferroelectric stacked-gate enhancement-mode GaN-based MOS-HEMT device provided in an embodiment;

[0024] Figure 2 It is the experimental test CV curve of the ferroelectric stacked gate enhancement mode GaN-based MOS-HEMT device corresponding to Examples 1 and 2;

[0025] Figure 3 It is the experimental test transfer curve of the ferroelectric stacked gate enhancement mode GaN-based MOS-HEMT device corresponding to Examples 1 and 2.

[0026] Figure 4 This is the experimental test gate leakage curve of the ferroelectric stacked gate enhancement mode GaN-based MOS-HEMT device corresponding to Example 1. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and the features in the embodiments can be combined with each other without conflict.

[0028] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0029] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0030] Embodiment 1:

[0031] In this embodiment, an enhancement-mode power device using a ferroelectric stacked gate dielectric includes, from bottom to top, a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104, and a gate dielectric passivation layer 105, wherein the barrier layer is etched to a thickness of 25 nm, and the channel layer is 200 nm thick;

[0032] Among them, the barrier layer 104 is etched as a whole to a barrier thickness of 18nm, and then a ferroelectric stacked gate dielectric passivation layer is deposited thereon. The first layer is a 3-5nm dielectric layer 115 in contact with the barrier layer, and above it is a hafnium oxide / zirconium oxide overlapping structure 125, and the top is a dielectric layer 135 with a thickness similar to the overlapping structure.

[0033] S1. Soak the AlGaN / GaN heterojunction epitaxial layer in a solution of H2SO4:H2O2=3:1 (mass ratio) for 10 minutes to remove the unstable epitaxial oxide layer on the surface. Then use acetone and isopropyl alcohol to remove organic matter on the AlGaN / GaN heterojunction epitaxial layer.

[0034] S2. Etching the barrier layer 104 as a whole to make it 12-20 nm thick, thereby reducing the distance from the ferroelectric layer to the channel and promoting the realization of enhanced performance.

[0035] S3, defining the active area pattern by photolithography, removing the barrier layer 104 and the channel layer 103 in the heterojunction by etching isolation to form an independent active area, wherein the etching depth is greater than the thickness of the barrier layer and the channel layer;

[0036] S4, defining the metal position and pattern of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 500° C. to 800° C. in a vacuum or nitrogen atmosphere, so that the source and drain electrodes form ohmic contacts with the barrier layer;

[0037] S5, depositing the ferroelectric stacked gate dielectric passivation layer 105 by magnetron sputtering, and annealing at 400°C to 600°C in a nitrogen atmosphere for 30s to 60s to form a high-k gate dielectric passivation layer with ferroelectricity, improve the quality of the gate dielectric passivation layer, and repair etching damage.

[0038] S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

[0039] Embodiment 2:

[0040] In this embodiment, an enhanced power device using a ferroelectric stacked gate dielectric includes, from bottom to top, a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104, and a gate dielectric passivation layer 105, wherein the barrier layer is etched to a thickness of 25 nm, and the channel layer is 200 nm thick;

[0041] Among them, the barrier layer 104 is etched as a whole to a barrier thickness of 20nm, and then a ferroelectric stacked gate dielectric passivation layer is deposited thereon. The first layer is a 3-5nm dielectric layer in contact with the barrier layer, above which is a hafnium oxide / zirconium oxide overlapping structure, and the top is a dielectric layer with a thickness similar to the overlapping structure.

[0042] S1. Soak the AlGaN / GaN heterojunction epitaxial layer in a solution of H2SO4:H2O2=3:1 (mass ratio) for 10 minutes to remove the unstable epitaxial oxide layer on the surface. Then use acetone and isopropyl alcohol to remove organic matter on the AlGaN / GaN heterojunction epitaxial layer.

[0043] S2. Etching the barrier layer 104 as a whole to make it 12-20 nm thick, thereby reducing the distance from the ferroelectric layer to the channel and promoting the realization of enhanced performance.

[0044] S3, defining the active area pattern by photolithography, removing the barrier layer 104 and the channel layer 103 in the heterojunction by etching isolation to form an independent active area, wherein the etching depth is greater than the thickness of the barrier layer and the channel layer;

[0045] S4, defining the metal position and pattern of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 500° C. to 800° C. in a vacuum or nitrogen atmosphere, so that the source and drain electrodes form ohmic contacts with the barrier layer;

[0046] S5, depositing the ferroelectric stacked gate dielectric passivation layer 105 by magnetron sputtering, and annealing at 400°C to 600°C in a nitrogen atmosphere for 30s to 60s to form a high-k gate dielectric passivation layer with ferroelectricity, improve the quality of the gate dielectric passivation layer, and repair etching damage.

[0047] S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

[0048] Figure 2 CV curves of the experimental tests corresponding to Example 1 and Example 2. There are no other differences between Example 1 and Example 2 except that the thickness of the barrier layer is different. Figure 2 It can be seen that the threshold voltages of both Example 1 and Example 2 are positively shifted under the positive gate bias, and the threshold voltage of Example 1 has a larger positive drift under the same gate bias than Example 2. As the operating voltage increases, the device threshold voltage increases, and the threshold voltage is much greater than zero.

[0049] Figure 3 ] are experimental test transfer curves corresponding to Example 1 and Example 2. There are no other differences between Example 1 and Example 2 except that the thickness of the barrier layer is different. Figure 3 It can be seen that the threshold voltages of both Embodiment 1 and Embodiment 2 are positively shifted under the positive gate bias, and the output current does not decrease significantly after the shift.

[0050] Figure 4 The gate leakage curve of the experiment test corresponding to Example 1 is shown in FIG. Figure 4 It can be seen that the gate leakage of the device in Example 1 remains at 10V gate voltage. -7 A / mm level, with good gate leakage suppression performance.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should be included in the scope of the claims of the present invention.

Claims

1. An enhancement-mode power device using a ferroelectric stacked gate dielectric, comprising, from bottom to top, a substrate (101), a buffer layer (102), a channel layer (103), a barrier layer (104), and a ferroelectric stacked gate dielectric passivation layer (105), characterized in that: The barrier layer (104) is deeply etched as a whole. The first layer of the ferroelectric stacked gate dielectric passivation layer is a 3-5 nm dielectric layer in contact with the barrier layer, above which is a hafnium oxide / zirconium oxide overlapping structure, and on top is a dielectric layer with a thickness similar to that of the hafnium oxide / zirconium oxide overlapping structure.

2. An enhancement-mode power device using a ferroelectric stacked gate dielectric according to claim 1, characterized in that The non-overlapping structure dielectric layer in the ferroelectric stacked gate dielectric passivation layer (105) is a high-k metal oxide, including one or more of HfO2, ZrO2, and Al2O3 oxides.

3. The enhancement mode power device using ferroelectric stacked gate dielectric according to claim 1, characterized in that The ferroelectric stacked gate dielectric passivation layer (105) has an HfO2 / ZrO2 overlapping structure.

4. The enhancement mode power device using ferroelectric stacked gate dielectric according to claim 3, characterized in that The HfO2 / ZrO2 overlapping structure in the ferroelectric stacked gate dielectric passivation layer (105) is a five-layer or seven-layer overlapping structure.

5. The enhancement mode power device using ferroelectric stacked gate dielectric according to claim 1, characterized in that The starting layer of the HfO2 / ZrO2 overlapping structure in the ferroelectric stacked gate dielectric passivation layer (105) is a metal oxide different from the barrier contact dielectric layer.

6. The enhancement mode power device using ferroelectric stacked gate dielectric according to claim 1, characterized in that The thickness of the ferroelectric stacked gate dielectric passivation layer (105) is 20-40 nm.

7. The enhancement mode power device using ferroelectric stacked gate dielectric according to claim 1, characterized in that The substrate (101) is silicon, and the buffer layer (102) is C- or Fe-doped GaN.

8. The enhancement mode power device using ferroelectric stacked gate dielectric according to claim 1, characterized in that The channel layer (103) is GaN; the barrier layer (104) is AlGaN or AlN; the barrier layer has a thickness of 12 to 30 nm, and the barrier layer is etched as a whole to have a thickness of 12 to 20 nm.

9. A method for preparing an enhancement mode power device using a ferroelectric stacked gate dielectric as claimed in any one of claims 1 to 8, characterized in that: The steps include: S1. Immerse the AlGaN / GaN heterojunction epitaxial layer in a H2SO4:H2O2 solution to remove the unstable epitaxial oxide layer on the surface; then use acetone and isopropanol to remove organic matter on the AlGaN / GaN heterojunction epitaxial layer; S2, etching the barrier layer (104) as a whole to make it 12-20 nm thick, reducing the distance from the ferroelectric layer to the channel, and promoting the realization of enhanced performance; S3, defining the active region pattern by photolithography, removing the barrier layer (104) and the channel layer (103) in the heterojunction by etching isolation to form an independent active region, wherein the etching depth is greater than the thickness of the barrier layer and the channel layer; S4, defining the metal position and pattern of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 500° C. to 800° C. in a vacuum or nitrogen atmosphere, so that the source and drain electrodes form ohmic contacts with the barrier layer; S5, depositing a ferroelectric stacked gate dielectric passivation layer (105) by magnetron sputtering, and annealing at a temperature of 400° C. to 600° C. in a nitrogen atmosphere for 30 seconds to 60 seconds; A high-k gate dielectric passivation layer with ferroelectricity is formed. S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

10. The method for preparing an enhancement mode power device using a ferroelectric stacked gate dielectric according to claim 8, characterized in that: In S5, magnetron sputtering is used to deposit a gate dielectric passivation layer, and the process conditions are as follows: the substrate temperature is 100° C. to 200° C., the RF power is 120 W, and the reaction chamber pressure is 4 mTorr to 6 mTorr.

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