Methods of forming self-aligned buried power rails in nanosheet-based transistor devices

Abstract

A method of forming a nanosheet-based transistor device includes: forming an STI structure in a substrate; forming a fin-shaped structure from the substrate, the bottom sacrificial layer and the layer stack; forming a dummy gate stack on the channel region of the fin-shaped structure; forming an S / D recess in a source / drain S / D region of the fin-shaped structure, the S / D recess extending through the layer stack and the bottom sacrificial layer; removing the bottom sacrificial layer to form an empty space; depositing a bottom dielectric insulating (BDI) layer in the empty space; extending the S / D recess further into the substrate; depositing a via embedded power rail (VBPR) plug in the extended S / D recess; forming an epitaxial EPI structure to form an S / D feature over the VBPR plug in the S / D recess; removing the dummy gate stack; selectively removing the plurality of sacrificial layers in the channel region; forming a replacement metal gate (RMG) structure around each of the released plurality of channel layers; thinning the substrate from the back surface of the substrate; selectively etching the VBPR plug to expose the S / D feature; and forming a backside S / D electrical contact at the S / D feature.

Description

Technical Field

[0001] The present disclosure pertains to methods of forming self-aligned buried power rails in nanosheet-based transistor devices. Background Art

[0002] The semiconductor industry has recently evolved rapidly with advances in materials and design, resulting in smaller, more complex circuits. The number of circuits per chip area has increased, while geometries have decreased, resulting in increased production efficiency and reduced costs. The complexity of integrated circuit processing and manufacturing has also increased. Multi-gate devices like FinFETs and nanosheet-based transistors have been introduced to enhance gate control and reduce current leakage. Existing backside contact structures, while generally adequate, have limitations due to coverage variations during formation, which can cause device defects.

[0003] US2021 / 0376093A1 discusses a method for forming a back power rail disposed on a bottom dielectric layer and a back source contact disposed between a source feature and the back power rail, wherein the back source contact extends through the bottom dielectric layer. Summary of the invention

[0004] An object of the inventive concept is to provide an improved method of forming a self-aligned buried power rail (BPR) in a nanosheet-based transistor device.

[0005] Another object is to provide a more reliable method for forming self-aligned BPRs in nanosheet-based transistor devices.

[0006] Yet another object is to provide a faster method for forming self-aligned BPRs in nanosheet-based transistor devices.

[0007] Yet another object is to provide a less expensive method of forming a self-aligned BPR in a nanosheet-based transistor device.

[0008] According to a first aspect, a method for forming a nanosheet-based transistor device from a preform is provided, the preform comprising a substrate, a bottom sacrificial layer disposed on a front side of the substrate, and a layer stack disposed on the bottom sacrificial layer, the stack comprising a plurality of channel layers arranged alternately with the plurality of sacrificial layers, the method comprising: forming a shallow trench isolation (STI) structure in the substrate; forming a fin-shaped structure from the substrate, the bottom sacrificial layer and the layer stack; forming a dummy gate stack on a channel region of the fin-shaped structure; forming an S / D recess in a source / drain (S / D) region of the fin-shaped structure, the S / D recess extending through the layer stack and the bottom sacrificial layer; removing the bottom sacrificial layer to form an empty space; and removing a dummy gate stack in the empty space. Depositing a bottom dielectric insulating BDI layer to fill the empty space; extending the S / D recess further into the substrate; depositing a through-hole buried power rail VBPR plug in the extended S / D recess; forming an epitaxial EPI structure to form an S / D feature over the VBPR plug in the S / D recess; selectively removing a plurality of sacrificial layers in the channel region to release the plurality of channel layers; forming a replacement metal gate RMG structure around each of the released plurality of channel layers; thinning the substrate from the back side of the substrate to expose the VBPR plug; selectively etching the VBPR plug to expose the S / D feature; and forming a back side S / D electrical contact at the S / D feature.

[0009] By embedding BDI when processing transistor devices from the front during VBPR formation, it helps to avoid HK (high-k gate dielectric material) defects during thinning or removal of the substrate from the back. When bonding and flipping the transistor device (more precisely, a wafer with a large number of transistor devices thereon) and thinning or removing the substrate from the back of the substrate to expose the VBPR plug, the chemical processing will expose HK in the RMG. Therefore, the presence of BDI according to the present method can prevent plasma or chemical HK defects. Therefore, the present method can provide a more reliable and safe manufacturing method. In addition, the present method can save time in manufacturing nanosheet-based transistor devices.

[0010] The method is in principle applicable to any type of nanosheet-based transistor device, such as finFET devices, CFET devices, fork-sheet devices, etc. Any of these transistor types generally operate based on having one or more channels in which electrons / holes can move when a bias voltage is applied to the channel region, i.e., between the source region and the drain region, controlled by the gate potential. Thus, by changing the potential at the gate structure located between the source region and the drain region, the electron or hole flow is further tuned or turned on / off.

[0011] Therefore, the region where the gate structure is arranged may be referred to as a “channel region” or an “active region” hereinafter.

[0012] A "layer stack" may refer to a stack comprising one or more layers (eg, nanosheets).

[0013] According to the above, "S / D region" may refer to either or both of the source region and the drain region of a nanosheet device.

[0014] Here (and elsewhere) a "wafer" refers to a relatively large, possibly at least partially processed preform on which a relatively large number of nanosheet-based transistor devices have been or will be formed. Such a wafer may have a size of cm 2 Area of ​​magnitude, e.g. 10-1000cm 2 .

[0015] "Substrate" refers throughout to a material that forms the basis for other materials / compounds / structures disposed thereon. Although the etched away portions may be filled with another material (such as an STI structure extending vertically into the substrate), these materials / features generally do not constitute part of the substrate as defined herein.

[0016] Preferably, the steps of removing the bottom sacrificial layer and depositing the BDI layer are performed before the step of extending the S / D recesses.

[0017] According to the above, this embodiment can particularly prevent plasma or chemical HK defects.

[0018] Alternatively, the step of removing the bottom sacrificial layer may be performed after the step of extending the S / D recess, and the steps of depositing the BDI layer and depositing the VBPR plug may be performed simultaneously while depositing the same material.

[0019] Also, according to the above, this embodiment can particularly prevent plasma or chemical HK defects.

[0020] Preferably, the method further comprises, before extending the S / D recess: depositing a mask layer on the front side of the substrate; forming an opening in the mask layer, the opening laterally coinciding with the S / D recess; and selectively etching a spin-on carbon SoC layer present in the S / D region.

[0021] The step of thinning the substrate from the back side of the substrate may include completely removing the substrate.

[0022] This could make it unnecessary to perform backside lithography, helping to save manufacturing time and provide a more flexible manufacturing approach.

[0023] The method may further include, after the step of thinning the substrate, depositing a mask layer on the back side of the substrate; forming an opening in the mask layer that laterally coincides with the exposed VBPR plug; and selectively etching the VBPR plug through the opening in the mask layer to expose the S / D features from the back side of the substrate.

[0024] Preferably, either or both of the openings of the mask are larger than the S / D regions and / or laterally offset from the S / D regions.

[0025] Therefore, there does not have to be an exact match between the opening and the S / D regions, which can save manufacturing time.

[0026] Preferably, the opening of the mask layer is larger than the VBPR plug and / or is laterally offset from the VBPR plug.

[0027] The method may further include etching away portions of the sacrificial layer facing inwardly toward the S / D regions, and depositing an inner spacer layer on the etched away portions.

[0028] The inner spacer can prevent the sacrificial layer from being exposed from the epi structure of the S / D feature, thereby preventing the epi structure from growing next to it. This may sometimes be referred to as inner spacer etch ISP.

[0029] The method may further include depositing a contact layer on the EPI structure.

[0030] The contact layer may be a contact etch stop layer CESL.

[0031] The method may further comprise depositing a buried power rail BPR extending between adjacent stacks on the back side of the substrate, the BPR thereby electrically connecting the adjacent stacks.

[0032] Preferably, one or more of the following apply:

[0033] The substrate includes Si;

[0034] The bottom sacrificial layer includes Si x Ge 1-x , where x belongs to the range of 0.5≤x≤0.7;

[0035] The channel layer includes Si;

[0036] The sacrificial layer includes Si y Ge 1-y , where y belongs to the range of 0.75≤y≤0.90;

[0037] The dummy gate stack includes polysilicon or amorphous silicon aSi;

[0038] The VBPR plug includes one or more of SiN, SiCN, SiOCN, SiOC, SiOBCN and / or is based on a dual dielectric film material such as a SiN liner and a SiO2 filler;

[0039] The BDI layer includes one or more of SiO2, SiN, SiCN, SiOCN, SiOC, and SiOBCN;

[0040] The SoC layer includes polymer methyl silsesquioxane MSQ or hydrogen silsesquioxane HSQ;

[0041] The mask includes a chemically amplified resist CAR or a metal organic resist MOR; and

[0042] The EPI structure includes SiN.

[0043] The upper vertical layer of the STI structure may be located at or above the vertical level of the BDI layer. This helps reduce unnecessary exposure at the metal HK during backside substrate removal.

[0044] The method may further include depositing a second BDI layer on the BDI layer from a back side thereof after the substrate is completely removed.

[0045] This prevents loss of BDI from the front side during etch back and thereby increases the thickness of the dielectric material to further isolate the metal in contact with the RMG.

[0046] Preferably, the EPI structure includes a dopant, the dopant includes one or more of P, As and B, and the VBPR plug preferably does not contain a dopant.

[0047] Preferably, the EPI structure includes SiGe with a B dopant for a p-EPI structure and Si with a p dopant for an n-EPI structure.

[0048] Further scope of application of the present invention will become apparent from the specific embodiments provided below. However, it should be understood that while indicating preferred embodiments of the present invention, the specific embodiments and specific examples are given by way of illustration only, because various changes and modifications within the scope of the present invention will become apparent to those skilled in the art based on the specific embodiments.

[0049] It will be understood, therefore, that the inventive concept is not limited to the specific components of the devices described, or the actions of the methods described, as such devices and methods may vary. It should also be understood that the terms used herein are intended to describe specific embodiments only and are not intended to be limiting. It must be noted that the articles "a", "an", "the" and "said" used in the specification and the appended claims are intended to indicate the presence of one or more elements, unless the context clearly dictates otherwise. Thus, for example, a reference to "a unit" or "the unit" may include several units, and so on. In addition, the words "comprises", "includes", "contains" and similar expressions do not exclude other elements or steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other objects, features and advantages of the inventive concept will be better understood through the following detailed description which is illustrative and non-restrictive with reference to the accompanying drawings. In the accompanying drawings, like reference numerals will be used for like elements unless otherwise specified.

[0051] Figure 1 A flow chart illustrating a method of forming a nanosheet-based transistor device.

[0052] Figure 2-15 Schematically illustrated are cross-sectional profiles of a nanosheet-based transistor device according to a first embodiment during mandatory or optional fabrication steps.

[0053] Figure 16-29 Schematically illustrated are cross-sectional profiles of a nanosheet-based transistor device according to a second embodiment during mandatory or optional fabrication steps.

[0054] Fig.30 Schematic showing a top view of a nanosheet-based transistor device, highlighting the Figure 2-29 The incision locations are depicted in the cross-sectional outline. DETAILED DESCRIPTION

[0055] The inventive concept will now be described more fully below with reference to the accompanying drawings showing currently preferred variations of the inventive concept. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided for thoroughness and completeness and to fully convey the scope of the inventive concept to those skilled in the art.

[0056] The following description of example embodiments is organized as follows. Figure 1 A flow chart of a method 100 of forming a nanosheet-based transistor device is depicted. Figure 2-15 A nanosheet-based transistor device is depicted in detail as seen in mandatory or optional steps undertaken in fabricating the nanosheet-based transistor device according to a first embodiment of the method 100 . Figure 16-29 Detailed description of a nanosheet-based transistor device as seen in the mandatory or optional steps of manufacturing a nanosheet-based transistor device according to a second embodiment of the method 100. Some drawings related to the second embodiment ( Figure 16-29 ) and the corresponding figure of the first embodiment ( Figure 2-15 ) are similar or identical. This should not confuse a person skilled in the art in practicing the inventive concept; on the contrary, the apparent repetition of the drawings helps to understand the inventive concept in a clear manner. In order to avoid unnecessary clutter in the drawings, only the currently relevant reference numerals are included therein. In addition, Figure 2-29, cross-sectional profiles taken along different cuts of a preform are shown, which preform may be processed at least partially according to the method 100 described below. In other words, Figure 2-29 The leftmost vertical column (i) corresponds to the cross-sectional profiles considered at a particular cut, the middle column (ii) corresponds to the cross-sectional profiles considered at another cut, and so on. Fig.30 A top view is schematically shown, including arrows (i), (ii) and (iii), along which the Figure 2-29 Cross-sectional profile in. Although Fig.30 The top view of the current manufacturing step depicted in FIG. 1 is completely covered by a temporary layer, for example, but a person skilled in the art should clearly understand its meaning.

[0057] Preferred options regarding interim or final materials / compounds for fabricating nanosheet-based transistor devices are essentially given at the end of the specification, but some example materials are mentioned elsewhere.

[0058] Those skilled in the art will also appreciate that from a manufacturing perspective, Figure 2-30 The roughly right angles depicted in are highly schematic. In real nanosheet-based transistor device fabrication, these angles are typically smooth / rounded and difficult to control precisely.

[0059] Method 100 starts in a conventional manner. That is, the formation of a nanosheet-based transistor device starts from a preform, which includes a substrate 202, a bottom sacrificial layer 204 disposed on the front side 206 of the substrate 202, and a layer stack 208, 210 disposed on the bottom sacrificial layer 204, wherein the stack 208, 210 includes a plurality of channel layers 208 arranged alternately with a plurality of sacrificial layers 210. The number of layers in the layer stack 208, 210 is preferably four or more, i.e., at least two channel layers 208 and at least two sacrificial layers 210. Preferably, the bottom and top layers of the layer stack 208, 210 include sacrificial layers 210, regardless of how many layers there are between them. Specifically, in the case where Si / SiGe constitutes a pair of a channel layer (Si) and a sacrificial layer (SiGe), the layer stack 208, 210 may include up to seven such pairs. In practice, the best performance can be achieved when there are two or three such pairs.

[0060] The method 100 includes forming 105 a shallow trench isolation (STI) structure 212 in the substrate 202 . The STI structure 212 may be formed / deposited by conventional STI procedures. The STI structure 212 may prevent current leakage between adjacent components on the substrate 202 .

[0061] The method 100 also includes forming 110 a fin structure 214 from the substrate 202 , the bottom sacrificial layer 204 , and the layer stacks 208 , 210 .

[0062] The method 100 further includes forming 115 a dummy gate stack 216 on the channel region of the fin structure 214. The dummy gate stack 216 can be considered as a fixture, thereby allowing the entire structure to be exposed to intermediate processes and subsequently removed and / or replaced by a functional gate structure; Figure 2 .

[0063] The method 100 further includes forming 120 an S / D recess 218 in a source / drain S / D region of the fin structure 214 , the S / D recess 218 extending through the layer stack and the bottom sacrificial layer 204 ; Figure 3 The S / D recess 218 may extend vertically into the substrate 202 to a certain extent. The certain extent may be on the order of the vertical thickness of the sacrificial layer 204.

[0064] The upper vertical level L1 of the STI structure 212 may be located at the vertical level of the bottom sacrificial layer 204 or above the vertical level L2 of the bottom sacrificial layer 204. Figure 2-4 , and is applicable to the entire disclosure. Although not shown in the exemplary figures that follow, the situation may also be as follows: the bottom sacrificial layer 204 has been replaced by the bottom dielectric insulating BDI layer 220, because the space occupied by the BDI layer 200 substantially coincides with the space occupied by the removed bottom sacrificial layer 104. Therefore, explicitly, the upper vertical level L1 of the STI structure can be located at the vertical level L1 of the BDI layer 220 or above the vertical level L2 of the BDI layer 220. This is as shown in FIG. Figure 4 shown, but applies to subsequent figures.

[0065] The method 100 further includes removing 125 the bottom sacrificial layer 204, thereby forming an empty space. Figure 3 and Figure 4 The intermediate steps between.

[0066] The method 100 further includes depositing 130 a bottom dielectric insulating BDI layer 220 in the empty space, thereby filling the empty space; Figure 4 .

[0067] The method 100 also includes extending 135 the S / D recess further into the substrate; Figure 7 This may be accomplished by etching the S / D recess 218 further (vertically) into the substrate 202 relative to the STI structure 212. Hereinafter, the space 218 created by the extension 135 of the S / D recess 218 may be referred to as an extended S / D recess 218.

[0068] The method 100 further includes depositing 140 a through-hole buried power rail VBPR plug 222 in the extended S / D recess 218 ; Figure 8 The VBPR plug 222 may extend above the top surface 206 of the substrate 202 after deposition. The VBPR plug 222 may also extend vertically above the top surface 223 of the STI structure 212 after deposition. In addition, the top surface 223 of the STI structure 212 may protrude vertically relative to the top surface 206 of the substrate 202.

[0069] The method 100 further includes forming 145 an epitaxial EPI structure 224 to form an S / D feature 224 over the VBPR plug 222 in the S / D recess 218 ; Fig.10 The epi structure 224 may preferably be in direct contact with the VBPR plug 222; however, indirect contact through a suitable intermediate layer is possible. The schematically depicted pyramidal / diamond geometry of the epi structure 224 may result from the crystal growth of these materials at the S / D regions and therefore depends on the Miller index of these materials relative to the surface on which they grow (e.g., 110, 111, etc.). However, the depiction of the geometry of the epi structure 224 here is schematic.

[0070] The method 100 also includes removing 150 the dummy gate stack 216 .

[0071] The method 100 also includes selectively removing 155 the plurality of sacrificial layers 210 in the channel region, thereby releasing the plurality of channel layers 208 .

[0072] The method 100 also includes forming 160 a replacement metal gate RMG structure 226 around each of the plurality of released channel layers 208 ; Fig.11 .

[0073] The method 100 also includes thinning 165 the substrate from a back side of the substrate, thereby exposing the VBPR plug 222; Fig.13 .

[0074] The method 100 further includes selectively etching 170VBPR plug 222 to expose S / D feature 224; Fig.14 .

[0075] The method 100 also includes forming 175 a backside S / D electrical contact 238 at the S / D feature 224; Fig.15 As is clear, Figure 2-12 compared to, Figure 13-15 The cross-sectional profile is inverted.

[0076] The step 125 of removing the bottom sacrificial layer 204 and the step 130 of depositing the BDI layer 220 may be performed before the step 135 of extending the S / D recess 218. This particular order of method steps is used throughout the first embodiment, and therefore reference is made to Figure 2-15 (some of them).

[0077] Alternatively, the step 125 of removing the bottom sacrificial layer 204 may be performed after the step 135 of extending the S / D recess 218, and the step 130 of depositing the BDI layer 220 and the step 140 of depositing the VBPR plug 222 may be performed simultaneously while depositing the same material. This alternative procedure is used throughout the second embodiment, and therefore reference is made to Figure 16-29 (some of them).

[0078] According to the first embodiment, the method 100 may further include, before extending 135 the S / D recess, depositing a spin-on carbon SoC layer 228 on the nanosheet-based transistor device, depositing a hard mask layer 230 above the SoC layer 228, depositing a photomask layer 232 above the hard mask layer 230, etching an opening 234 on the photomask, which laterally coincides with the S / D recess 218, etching an opening 234 on the SoC layer 228, which laterally coincides with the opening 218 on the photomask layer 232, and etching away the SoC layer 228 present in the S / D region 218.

[0079] Either or both of the openings of the photomask mask layer and the hard mask layer may be larger than the S / D region 218 and / or laterally offset from the S / D region 218. Figure 6 2, wherein when viewed in the plane of the depicted cross-sectional profile (i.e., column (i)), the width of the photomask layer 232 and the width of the hard mask layer 230 are both greater than the width of the S / D recess 218. As will be appreciated, the width of the above-described openings can vary in many ways along different directions and are therefore difficult to precisely control in practice and are, to a certain extent, unnecessary.

[0080] At a more general level, the steps associated with this (first embodiment) are to deposit a mask layer on the front side of the substrate 202, to form openings in the mask layer that substantially coincide with the S / D recesses in the lateral direction, and to selectively etch the SoC layer present in the S / D regions 218. The etching associated with this may be isotropic (thus, meaning wet etching), but may alternatively or additionally be gaseous.

[0081] Furthermore, according to the first embodiment, the step 165 of thinning the substrate 202 from the back side of the substrate 202 may include completely removing the substrate; Fig.13. Thereafter, the VBPR plug 222 may protrude from the bottom dielectric layer 220 to a first extent E1 at the back side, and may therefore protrude from the STI structure 212 to a second extent E2 that is less than the first extent E1. Therefore, it is understood that the STI structure 212 is not removed in this step. For reference, the vertical thickness of a substrate typically made of Si is 200-800 μm (typically 300 μm Si wafers), while the thickness of the components / layers discussed herein is typically about 50-200 nm.

[0082] However, the deposition / formation of the VBPR plug 222 can be accomplished in a variety of ways. In conjunction with the first embodiment, photolithography can be performed from the front side before the VBPR plug 222 is formed. Afterwards, backside photolithography can be performed to expose the VBPR plug 222 on the back side for power wiring, etc. Alternatively, in conjunction with the second embodiment, the VBPR plug 222 can be formed at the S / D region 218 without performing frontside photolithography. Afterwards, backside photolithography can be performed to expose the VBPR plug 222 on the back side (i.e., from below). This will be further elaborated below.

[0083] Another option involves performing photolithography from the front side before forming the VBPR plug 222. Afterwards, backside photolithography may become unnecessary and thus may be omitted. Instead, exposing the VBPR plug 222 from the back side may include fully grooving the substrate until the VBPR plug 222 protrudes from the back side.

[0084] Therefore, the VBPR plug 222 material may be the same material (eg, SiN) or the same dual material (eg, SiN liner and SiO 2 filler) as the BDI layer 220 material.

[0085] Thus, for the second embodiment, photolithography may be performed differently. For example, the method 100 associated therewith may further include, after step 165 of thinning the substrate 202, depositing a mask layer on the back side of the substrate, forming an opening in the mask layer that laterally coincides with the exposed VBPR plug 222, and selectively etching the VBPR plug 222 through the opening in the mask layer to expose the S / D feature 218 from the back side of the substrate. Masking may be accomplished with any suitable technique. For example, a multi-layer patterned stack is possible in the case of obtaining a smaller critical dimension CD with a straight profile. Thus, a system having a photomask combined with a hard mask or a release layer is possible.

[0086] For the second embodiment, the opening of the mask layer may also be larger than the VBPR plug 222 and / or laterally offset from the VBPR plug 222 .

[0087] The method 100 may further include etching away portions of the sacrificial layer 210 that face inwardly toward the S / D regions, and depositing an inner spacer layer 236 on the etched away portions; Fig. 9 The inner spacer layer 236 may be a single layer or a double layer. Example fabrication materials for the inner spacer are SiOCN, SiO2 / SiOCN, SiOC / SiOCN, SiOC, SiN, and SiCN.

[0088] The method 100 may further include depositing a contact layer 240 on the EPI structure 224 .

[0089] The method 100 may further include depositing a buried power rail BPR extending between adjacent stacks on the back side of the substrate, the BPR thereby electrically connecting the adjacent stacks. This feature is not shown in the drawings, but should be readily understood by those skilled in the art when practicing the inventive concept.

[0090] Here are some sample materials for the above components.

[0091] The substrate 202 may include Si.

[0092] The bottom sacrificial layer 204 may include Si x Ge 1-x , where x belongs to the range of 0.5≤x≤0.7.

[0093] The channel layer 208 may include Si.

[0094] The sacrificial layer 210 may include Si y Ge 1-y , where y belongs to the range of 0.75≤y≤0.90.

[0095] The dummy gate stack 216 may include polysilicon.

[0096] The VBPR plug 222 may include one or more of SiN, SiCN, SiOCN, SiOC, and SiOBCN. The VBPR plug 222 may be formed of a dual dielectric film material, for example, through a SiN liner and a SiO2 filler.

[0097] The BDI layer 220 may include one or more of SiO 2 , SiN, SiCN, SiOCN, SiOC, and SiOBCN.

[0098] The SoC layer may include polymer methyl silsesquioxane MSQ or hydrogen silsesquioxane HSQ.

[0099] The mask may include a chemically amplified resist CAR or a metal organic resist MOR. The MOR may be Si based.

[0100] The EPI structure may include SiN. The EPI structure may include a dopant, and the dopant includes one or more of P, As, and B. The VBPR plug may be free of dopants.

[0101] Thus, in summary, in some of the above variations, a method for forming a nanosheet-based transistor device has been described with an emphasis on power routing with the aid of through-via buried power rail plugs 222 .

[0102] Those skilled in the art will appreciate that the inventive concept is by no means limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. In implementing the claimed inventive concept, other variations of the disclosed embodiments may be understood and implemented by those skilled in the art from a study of the drawings, the present disclosure, and the appended claims.

Claims

1. A method (100) for forming a nanosheet-based transistor device from a preform, the preform comprising a substrate (202), a bottom sacrificial layer (204) disposed on a front side of the substrate (202), a layer stack (208, 210) disposed on the bottom sacrificial layer (204), the stack (208, 210) comprising a plurality of channel layers (208) arranged alternately with a plurality of sacrificial layers (210), the method (100) comprising: forming (105) a shallow trench isolation (STI) structure (212) in the substrate (202); forming (110) a fin structure (214) from the substrate (202), the bottom sacrificial layer (204) and the layer stack; forming (115) a dummy gate stack (216) on the channel region of the fin-shaped structure (214); forming (120) an S / D recess (218) in a source / drain S / D region of the fin structure (214), the S / D recess (218) extending through the layer stack (208, 210) and the bottom sacrificial layer (204); removing (125) the bottom sacrificial layer (204) to form an empty space; depositing (130) a bottom dielectric insulating BDI layer (220) in the empty space, thereby filling the empty space; extending (135) the S / D recess (218) further into the substrate (202); depositing (140) a through-hole buried power rail VBPR plug (222) in the extended S / D recess (218); forming (145) an epitaxial EPI structure (224) to form an S / D feature over the VBPR plug (222) in the S / D recess (218); removing (150) the dummy gate stack (216); Selectively removing (155) the plurality of sacrificial layers (210) in the channel region, thereby releasing the plurality of channel layers (208); forming (160) a replacement metal gate (RMG) structure (226) around each of the released plurality of channel layers (208); Thinning (165) the substrate (202) from a back side thereof to expose the VBPR plug (222); selectively etching (170) the VBPR plug (222) to expose the S / D features (224); and Backside S / D electrical contacts (238) are formed (175) at the S / D features (224).

2. The method (100) according to claim 1, characterized in that: The steps of removing (125) the bottom sacrificial layer (204) and depositing (130) the BDI layer (220) are performed before the step of extending (135) the S / D recess (218).

3. The method (100) according to claim 1, characterized in that: The step of removing (125) the bottom sacrificial layer (204) is performed after the step of extending (135) the S / D recess (218), and wherein the step of depositing (130) the BDI layer (220) and the step of depositing (140) the VBPR plug (222) are performed simultaneously when depositing the same material.

4. The method (100) according to claim 2, characterized in that: Also included is before extending (135) the S / D recess (218): Depositing a mask layer on the front side of the substrate (202); forming an opening in the mask layer, the opening lateraly overlapping the S / D recess; as well as The spin-on carbon SoC layer (228) present in the S / D region (218) is selectively etched.

5. The method (100) according to any one of claims 1, 2 or 4, characterized in that: The step of thinning (165) the substrate from the back side of the substrate (202) includes completely removing the substrate (202).

6. The method (100) according to claim 3, characterized in that: Also included is the step of, after thinning (165) the substrate (202): Depositing a mask layer on the back side of the substrate (202); forming an opening in the mask layer, the opening laterally coinciding with the exposed VBPR plug (222); as well as The VBPR plug (222) is selectively etched through the opening of the mask layer to expose the S / D feature (224) from the back side of the substrate (202).

7. The method (100) according to claim 4, characterized in that: Either or both of the openings of the mask are larger than the S / D regions (218) and / or are laterally offset from the S / D regions (218).

8. The method (100) according to claim 6, characterized in that: The opening of the mask layer is larger than the VBPR plug (222) and / or laterally offset from the VBPR plug (222).

9. The method (100) according to any one of claims 1 to 8, characterized in that: Also includes: Etching away a portion of the sacrificial layer (210) that faces inwardly toward the S / D region (218); as well as An inner spacer layer (236) is deposited over the etched portions.

10. The method (100) according to any one of claims 1 to 9, characterized in that: Also includes: A contact layer is deposited on the EPI structure (224).

11. The method (100) according to any one of claims 1 to 10, characterized in that: Also includes: A buried power rail (BPR) (238) is deposited, the BPR extending between adjacent stacks on the back side of the substrate (202), the BPR (238) thereby electrically connecting adjacent stacks.

12. The method (100) according to any one of claims 1 to 11, characterized in that: The upper vertical level (L1) of the STI structure (212) is located at or above the vertical level (L2) of the BDI layer (220).

13. The method (100) according to claim 5, characterized in that: The method also includes depositing a second BDI layer on the BDI layer (220) from its back side after the complete removal of the substrate (202).

14. The method (100) according to any one of claims 1 to 13, characterized in that: One or more of the following applies: The substrate (202) comprises Si; The bottom sacrificial layer (204) comprises Si x Ge 1-x , where x belongs to the range of 0.5≤x≤0.7; The channel layer (208) includes Si; The sacrificial layer (210) includes Si y Ge 1-y , where y belongs to the range of 0.75≤y≤0.90; The dummy gate stack (216) comprises polysilicon or amorphous silicon (aSi); The VBPR plug (222) comprises one or more of SiN, SiCN, SiOCN, SiOC and SiOBCN; The BDI layer (220) includes one or more of SiO2, SiN, SiCN, SiOCN, SiOC and SiOBCN; The SoC layer (228) includes polymer methyl silsesquioxane MSQ or hydrogen silsesquioxane HSQ; The mask layer (232) includes a chemically amplified resist CAR or a metal organic resist MOR; The EPI structure (224) includes SiN.

15. The method according to any one of claims 1 to 12, characterized in that The EPI structure (224) includes a dopant including one or more of P, As, and B, and wherein the VBPR plug (222) is free of the dopant.

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