Method for depositing stress dielectric layer in trench and shallow trench isolation structure

Abstract

The invention discloses a method for depositing a stress dielectric layer in a trench and a shallow trench isolation structure, and the method comprises the steps: carrying out the first deposition processing, and employing an HARP technology to deposit a first dielectric layer in a first trench based on a set first deposition thickness; first plasma treatment: based on the set first plasma treatment power and first plasma treatment time, plasma containing inert gas is adopted to carry out first plasma treatment on the whole film layer of the first dielectric layer, and the first deposition thickness does not exceed the treatment depth of the first plasma treatment; and based on the set first cycle number, circularly executing the first deposition treatment and the first plasma treatment for multiple times until the first groove is filled, so as to form a pressure stress dielectric layer in the first groove. Compared with the prior art, the unexpected technical effect of the invention is that dielectric layers with different stresses, especially compressive stress dielectric layers, can be selectively deposited in the groove according to needs.

Description

Technical Field

[0001] This application generally relates to the field of shallow trench isolation structure fabrication technology. More specifically, this application relates to a method for depositing a stress medium layer in a trench and a shallow trench isolation structure. Background Technology

[0002] Stress engineering is an important technique in the fabrication of metal-oxide-semiconductor (MOS) devices to improve device performance. By introducing stress into specific regions of the transistor, stress engineering can influence carrier mobility, thereby improving the transistor's electrical characteristics. Specifically, tensile stress can be introduced into the NMOS region. In NMOS transistors, electrons are the dominant carriers, and tensile stress can increase electron mobility. Conversely, compressive stress can be introduced into the PMOS region. In PMOS transistors, holes are the dominant carriers, and compressive stress can increase hole mobility.

[0003] In semiconductor integrated circuit manufacturing processes, shallow trench isolation (STI) structures are typically used to isolate various active regions. Therefore, it is desirable to utilize trench structures to selectively introduce different stresses into different regions.

[0004] For structures with sub-45nm technology nodes and large aspect ratios, HARP (High Aspect Ratio Process) deposition is typically used for trench filling. However, HARP has limited filling capacity and is prone to forming voids.

[0005] Therefore, there is an urgent need to provide a method for preparing stress medium layers by depositing them in trenches, so as to selectively deposit medium layers with different stresses, especially compressive stress medium layers, in trenches as needed. Furthermore, it is desirable to reduce the formation of voids during the deposition process. Summary of the Invention

[0006] In order to at least solve one or more of the technical problems mentioned above, this application proposes a preparation scheme for depositing a stress medium layer in a trench and a corresponding shallow trench isolation structure in several aspects.

[0007] In a first aspect, this application provides a method for depositing a stress medium layer in a trench, comprising: a first deposition process, wherein a first dielectric layer is deposited in a first trench using a HARP process based on a set first deposition thickness; a first plasma process, wherein the entire film of the first dielectric layer is subjected to a first plasma process using a plasma containing an inert gas based on a set first plasma process power and a first plasma process time, wherein the first deposition thickness of the first dielectric layer does not exceed the processing depth of the first plasma process at the first plasma process power and the first plasma process time; and, wherein the first deposition process and the first plasma process are repeatedly performed based on a set first number of cycles until the first trench is filled to form a compressive stress medium layer in the first trench.

[0008] In some embodiments, the compressive stress of the compressive stress medium layer is -100MPa to -50MPa.

[0009] In some embodiments, the method satisfies at least one of the following conditions: the first deposition thickness is 50 Å to 100 Å; the first plasma treatment power is 300 W to 500 W; the first plasma treatment time is 10 s to 15 s; the inert gas is Ar or He; the first number of cycles is 25 to 35; the chamber pressure of the first deposition treatment is 500 torr to 600 torr; and the chamber pressure of the first plasma treatment is 20 torr to 50 torr.

[0010] In some embodiments, the first trench is disposed in the region of the semiconductor structure used to form a PMOS device.

[0011] In some embodiments, the method further includes: a second deposition process, wherein a second dielectric layer is deposited in a second trench using a HARP process based on a set second deposition thickness; a second plasma process, wherein the surface of the second dielectric layer is subjected to a second plasma process using a plasma containing an inert gas based on a set second plasma process power and a second plasma process time, wherein the second deposition thickness of the second dielectric layer exceeds the processing depth of the second plasma process at the second plasma process power and the second plasma process time; and, the second deposition process and the second plasma process are repeatedly performed based on a set second number of cycles until the second trench is filled to form a tensile dielectric layer in the second trench.

[0012] In some embodiments, the tensile stress of the tensile stress medium layer is 100MPa~150MPa.

[0013] In some embodiments, the method satisfies at least one of the following conditions: the second deposition thickness is 150 Å to 200 Å; the second plasma treatment power is 150 W to 250 W; the second plasma treatment time is 5 s to 10 s; the inert gas is Ar or He; the second number of cycles is 10 to 20; the chamber pressure of the second deposition treatment is 500 torr to 600 torr; and the chamber pressure of the second plasma treatment is 20 torr to 50 torr.

[0014] In some embodiments, the second trench is disposed in the region of the semiconductor structure used to form an NMOS device.

[0015] In a second aspect, this application provides a method for depositing a stress dielectric layer in a trench, comprising: providing a semiconductor structure having a first region and a second region, the first region being used to form a PMOS device and having at least one first trench, the second region being used to form an NMOS device and having at least one second trench; forming a compressive stress dielectric layer or a tensile stress dielectric layer at least in the first trench of the first region and the second trench of the second region; removing the compressive stress dielectric layer of the second region or removing the tensile stress dielectric layer of the first region; forming a tensile stress dielectric layer in the second trench of the second region or forming a compressive stress dielectric layer in the first trench of the first region; wherein the compressive stress dielectric layer is formed according to the aforementioned method for forming a compressive stress dielectric layer in the first aspect.

[0016] In some embodiments, the tensile stress medium layer is further formed according to the method for forming a tensile stress medium layer according to the first aspect described above.

[0017] In a third aspect, this application provides a shallow trench isolation structure, wherein the medium layer in the trench of the shallow trench isolation structure is prepared by the preparation method described in any embodiment of the first aspect or the preparation method described in any embodiment of the second aspect.

[0018] Compared with the prior art, the unexpected technical effect of this application is that it can selectively deposit medium layers with different stresses, especially compressive stress medium layers, in the trench as needed.

[0019] This application embodiment introduces a plasma processing technology into HARP (High-Intensity Resin Coefficient) to deposit a dielectric layer in the trench using a deposition-surface treatment cyclic deposition mode. During the deposition process, the thickness of the deposited dielectric layer, the power of the plasma treatment, and the duration of the plasma treatment in each cycle can be set / adjusted to obtain dielectric layers with different stress characteristics, thereby improving device performance. In particular, when forming a compressive stress dielectric layer, by performing multiple cycles of deposition-surface treatment, with the thickness of the film layer deposited each time not exceeding the treatment depth of the plasma treatment, the entire film layer formed can be treated each time, rather than being limited to the surface of the dielectric layer. Therefore, this cyclic treatment mode can change the stress of the dielectric layer to obtain a compressive stress dielectric layer. In addition, since the trench filling after plasma surface treatment reduces the occurrence of overhangs, this improves the filling capability of HARP, ensures that there are no voids in the trench, guarantees product stability, and improves product yield. Furthermore, in some embodiments, dielectric layers with different stresses can be selectively deposited in trenches in different regions (NMOS / PMOS regions), and the deposition of dielectric layers with different stresses and plasma surface treatment can both be completed in the same machine. Attached Figure Description

[0020] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein: Figure 1A An exemplary flowchart of a method for depositing a stress medium layer in a trench according to some embodiments of this application is shown; Figure 1B An exemplary schematic diagram is shown illustrating how this application achieves different stress performances through deposition-surface treatment; Figure 2A The diagram shows a cross-sectional view of a trench formed in a semiconductor structure according to some embodiments of this application. Figure 2B This application shows a schematic cross-sectional view of the deposition medium layer according to some embodiments; Figure 2C This paper shows a cross-sectional structural schematic diagram of a dielectric layer subjected to plasma treatment according to some embodiments of this application; Figure 2D The diagram shows a cross-sectional structural schematic of the stress medium layer formed according to some embodiments of this application; Figure 2E The diagram shows a cross-sectional structure of a stress medium layer planarization process according to some embodiments of this application; Figure 3An exemplary flowchart of a method for depositing a stress medium layer in a trench according to other embodiments of this application is shown; Figure 4A This application shows a cross-sectional schematic diagram of a semiconductor structure having a first region and a second region, according to some other embodiments of the present application. Figure 4B A cross-sectional structural schematic diagram of the formation of the first stress medium layer according to other embodiments of this application is shown; Figure 4C This illustration shows a cross-sectional structural diagram of photoresist formed over a first stress dielectric layer according to some other embodiments of this application; Figure 4D This illustration shows a cross-sectional structural diagram of the photoresist in the second region being dissolved, according to some other embodiments of this application. Figure 4E This paper shows a cross-sectional structural diagram of the first stress dielectric layer and the remaining photoresist layer after removing the second region, according to some other embodiments of this application. Figure 4F A cross-sectional structural schematic diagram of the formation of the second stress medium layer according to other embodiments of this application is shown; Figure 4G This invention provides a cross-sectional structural schematic diagram of a planarization process for a first stress medium layer and a second stress medium layer according to other embodiments of this application. Figure 5 A schematic diagram illustrating the effect of plasma processing power and cycle number on the stress performance of the dielectric layer is shown. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0024] It should also be understood that, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "on" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers.

[0025] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0026] This application provides a method for preparing a stress dielectric layer by depositing it in a trench. By introducing a plasma treatment process into HARP (High-Intensity Reduction Plasma), a dielectric layer is deposited in the trench using a deposition-surface treatment cyclic deposition mode. During the deposition process, dielectric layers with different stress characteristics can be obtained by adjusting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the duration of the plasma treatment in each cycle, thereby improving device performance.

[0027] Figure 1A An exemplary flowchart of a method 100 for depositing a stress medium layer in a trench, according to some embodiments of this application, is shown.

[0028] like Figure 1AAs shown, in step S110, a dielectric layer is deposited in the trench using the HARP process based on the set deposition thickness. Next, in step S120, the dielectric layer is treated with plasma containing an inert gas based on the set plasma treatment power and plasma treatment time. Then, in step S130, the deposition of the dielectric layer and the plasma treatment step are repeated multiple times based on the set number of cycles until the trench is filled, forming a stress dielectric layer in the trench. The stress performance of the stress dielectric layer can be controlled by adjusting the deposition thickness per cycle, the plasma treatment power, the plasma treatment time, and the number of cycles.

[0029] Figure 1B An exemplary schematic diagram is shown, illustrating how this application achieves different stress performances through deposition-surface treatment.

[0030] like Figure 1B As shown in S140, firstly, using the HARP process, an oxide dielectric layer 112, such as silicon oxide (SiO2), is deposited on a substrate 111 (e.g., a silicon substrate) at high temperature. Then, as shown in S150, the HARP oxide dielectric layer is treated with plasma containing an inert gas such as Ar. As indicated by the arrow, the aforementioned deposition-plasma treatment process is repeated multiple times.

[0031] The HARP oxide deposition process is a purely thermal process. HARP oxides themselves contain many functional groups, such as -CH3 and -OH, and are relatively porous. When the thickness of the dielectric layer deposited in a single cycle is relatively thick, for example, exceeding the processing depth of subsequent plasma treatment, the plasma treatment only affects the surface structure of the dielectric layer, while the underlying layer remains relatively porous. Thus, when the device is removed from the high-temperature environment, the HARP oxide will shrink more than the substrate, exhibiting tensile stress (as shown in Figure 160).

[0032] The inventors discovered that if the thickness of the dielectric layer deposited in a single cycle is very thin, for example, not exceeding the processing depth of subsequent plasma treatments, then when the dielectric layer is subjected to high-power, long-duration plasma treatment, the entire film layer can be treated, making the entire film layer denser, rather than just limited to the surface. By repeatedly performing this deposition of a thin film layer followed by high-power, long-duration plasma treatment, each cycle removes functional groups from the oxide dielectric layer, making the entire dielectric layer even denser after multiple cycles. Thus, when the device returns from a high-temperature environment to room temperature, the dielectric layer shrinks less than the substrate, i.e., has a smaller coefficient of thermal expansion, thereby exhibiting compressive stress (as shown in Figure 170).

[0033] Based on the above principles, in this embodiment, a plasma treatment process is introduced into HARP to deposit a dielectric layer in the trench using a cyclic deposition-surface treatment method. During the deposition process, dielectric layers with different stress characteristics can be obtained by adjusting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the duration of the plasma treatment in each cycle, thereby improving device performance. Furthermore, by performing multiple cycles of deposition-surface treatment, it is convenient to control the treatment depth layer by layer when forming a compressive stress dielectric layer, thus allowing the entire formed dielectric layer to be treated, rather than being limited to the surface of the dielectric layer. Therefore, this cyclic treatment mode can effectively change the stress of the dielectric layer.

[0034] In addition, plasma treatment removes the functional groups in the oxide dielectric layer, making the dielectric layer more compact, which helps to reduce the porosity in the dielectric layer.

[0035] Furthermore, as a thermal reaction process for conformal growth, the valence bond concentration on the substrate surface affects the growth rate of HARP, and a lower deposition rate results in better filling capability. Therefore, in the next deposition cycle, the previous plasma treatment reduces the valence bonds on the oxide dielectric layer surface, which can lower the HARP deposition rate and thus achieve better filling performance.

[0036] It is understandable that, since the plasma treatment process is performed from top to bottom, the treatment effect is stronger at the top of the trench, resulting in a greater reduction of valence bonds on the surface of the top oxide layer, while the treatment effect is weaker at the bottom of the trench, resulting in a smaller reduction of valence bonds on the surface of the bottom oxide layer. Therefore, in the next deposition cycle, the deposition rate of HARP oxide at the top of the trench is more significantly affected than at the bottom. The lower deposition rate at the top reduces the occurrence of overhangs at the top of the trench and also helps to reduce porosity in the deposited medium layer, improving the filling effect.

[0037] Furthermore, based on the above principles, it can be seen that the deposition of dielectric layers under different stresses and the surface treatment of plasma can both be completed on the same machine. This helps reduce material transfer and machine changeover time, thereby significantly improving production efficiency and reducing equipment investment and space occupation, thus lowering production costs. In addition, continuously completing steps S110, S120, and S130 on the same machine allows for better control of the production process and reduces errors.

[0038] based on Figure 1A The preparation process of the method for depositing a stress medium layer in a trench is described below, in conjunction with... Figures 2A-2EThe schematic diagram of the semiconductor cross-sectional structure shown describes in detail an exemplary process flow of a method for depositing a stress dielectric layer in a trench using some embodiments of this application.

[0039] Figure 2A A cross-sectional view of a trench formed in a semiconductor structure according to an embodiment of this application is shown.

[0040] like Figure 2A As shown, a semiconductor structure 210 is provided, in which trenches 220 are formed.

[0041] In this embodiment, the semiconductor structure 210 may include a substrate 211, an oxide layer 212 and a nitride layer 213 sequentially stacked on the substrate 211, wherein the oxide layer 212 is located on the upper surface of the substrate 211. In other embodiments, the semiconductor structure 210 may also include only the substrate 211 and the nitride layer located on the substrate, or it may include the substrate 211, multiple oxide layers and multiple nitride layers sequentially stacked on the substrate 211. This embodiment does not limit the scope of the invention.

[0042] Specifically, the substrate 211 is made of a material containing Si, and may be at least one of the following materials: Si, SiGe, SiC, SiGeC, or other compound semiconductors containing Si. The substrate 211 may be a single-layer or multi-layer semiconductor structure made of these materials. The substrate 211 may also be silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), etc.

[0043] Specifically, the nitride layer 213 can be made of silicon nitride, and the oxide layer 212 can be made of silicon dioxide.

[0044] In this embodiment, the trench 220 extends from the surface of the nitride layer 213 away from the substrate 211 toward the substrate 211, penetrates the nitride layer 213 and the oxide layer 212, and extends into the interior of the substrate 211.

[0045] Specifically, the trench 220 is mainly fabricated using photolithography and can be formed using various known processes; the embodiments of this application are not limited in this respect. For example, the trench 220 fabrication process includes: coating photoresist on the semiconductor structure 210, selectively exposing the photoresist using an exposure machine, developing to remove the exposed or unexposed portions of the photoresist, etching or depositing patterns in the exposed areas, removing the remaining photoresist, and continuing to form the desired trench using dry etching or wet etching.

[0046] Specifically, the groove 220 has sidewalls, a bottom, and an upward opening. The shape of the groove 220 can be various shapes such as rectangle, circle, and cross, and there can be multiple grooves 220.

[0047] Specifically, trench 220 can be used as a trench in chip manufacturing processes such as shallow trench isolation (STI) and interlayer dielectric (ILD). In STI, trenches are used to isolate different transistors, prevent current leakage and crosstalk, thereby improving the performance of integrated circuits. In ILD, trenches are used to form conductive paths to connect circuit elements at different levels.

[0048] Figure 2B A cross-sectional structural diagram of the deposition medium layer according to an embodiment of this application is shown.

[0049] like Figure 2B As shown, based on the set deposition thickness, a dielectric layer 230 is deposited in the trench 220 and on the upper surface of the semiconductor structure 210 using the HARP process. In some embodiments of this application, during the deposition of the dielectric layer 230, the dielectric layer may be deposited only in the trench 220 or in the trench 220 and on a portion of the upper surface of the semiconductor structure 210, but the deposited dielectric layer must at least cover the trench 220.

[0050] Specifically, the dielectric layer 230 can be any suitable dielectric material known in the art, such as one or more combinations of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluorosilicone glass, undoped silicate glass (USG), or tetraethyl orthosilicate. This application embodiment does not limit the scope of the invention.

[0051] Specifically, in the HARP process, chemical vapor deposition is carried out through a thermal process, and the process temperature of the HARP process is generally 500℃~600℃.

[0052] In the HARP process, the thickness of the deposited film can typically be controlled by several factors. The HARP process uses a thermochemical reaction between ozone (O3) and tetraethoxysilane (TEOS) to form an oxide film. The thickness of the deposited film can be influenced by precisely controlling the flow rate and ratio of these chemical feedstocks. The temperature during deposition significantly affects the rate of the chemical reaction and the quality and purity of the film. Higher temperatures increase the rate of the chemical reaction, thus affecting the deposition rate and film thickness. The pressure during deposition also affects film growth. Lower pressure generally results in a slower deposition rate but can improve the vertical quality of the film. The reaction time during deposition is a direct method for controlling film thickness. By controlling the reaction time, the thickness of the deposited film can be precisely controlled. Therefore, the desired deposition thickness can be obtained by adjusting one or more of the above-mentioned process parameters of HARP. Figure 2C A cross-sectional structural schematic diagram of plasma treatment of the dielectric layer according to an embodiment of this application is shown.

[0053] like Figure 2C As shown, based on the set plasma processing power and plasma processing time, the aforementioned dielectric layer 230 is processed using plasma 240 containing an inert gas. Specifically, the aforementioned inert gas is Ar or He.

[0054] Specifically, the aforementioned dielectric layer 230 is treated with a plasma 240 containing Ar or He, which removes the -CH3, -H, and -OH valence bonds on the surface of the dielectric layer 230. In the process of removing the valence bonds on the surface of the dielectric layer 230, the plasma 240 simply blows away the valence bonds, resulting in a physical reaction. Compared to removing valence bonds through a chemical reaction, the embodiments of this application do not affect other properties of the dielectric layer 230 during the process of blowing away the valence bonds on the surface of the dielectric layer 230.

[0055] By adjusting the plasma treatment power and plasma treatment time, the treatment depth of the dielectric layer can be controlled, the amount of valence bonds removed from the surface of the dielectric layer can be removed, thereby adjusting the density of the dielectric layer and changing the coefficient of thermal expansion of the dielectric layer to provide different stress performance. Figure 2D A cross-sectional structural schematic diagram of the stress medium layer formed according to an embodiment of this application is shown.

[0056] like Figure 2D As shown, based on the set number of cycles, the aforementioned steps of depositing the dielectric layer and plasma processing are repeated multiple times until the aforementioned trench is filled, and a stress dielectric layer 250 is formed in the aforementioned trench and on the upper surface of the semiconductor structure 210.

[0057] Specifically, the stress performance of the stress dielectric layer 250 can be determined by the number of cycles, the thickness of the dielectric layer deposited each time during the cycle, the plasma processing power during the cycle, and the plasma processing time. The stress dielectric layer 250 can be a tensile stress dielectric layer or a compressive stress dielectric layer. When the stress dielectric layer 250 is a tensile stress dielectric layer, the aforementioned trench 220 is disposed in the region of the semiconductor structure 210 used for forming an NMOS device. When the stress dielectric layer 250 is a compressive stress dielectric layer, the aforementioned trench 220 is disposed in the region of the semiconductor structure 210 used for forming a PMOS device.

[0058] In some embodiments of this application, during multiple cycles, a dielectric layer may be deposited only in the trench 220 or in the trench 220 and on a portion of the upper surface of the semiconductor structure 210, but at least the deposited dielectric layer must cover the trench 220.

[0059] Specifically, in the repeated cycles of the aforementioned deposition medium layer step and plasma treatment step, the medium layer is treated with plasma 240 containing Ar or He, and then the medium layer is deposited again. Because the medium layer is treated with plasma containing Ar or He, this removes the valence bonds on the surface of the medium layer, reducing the number of valence bonds on the surface of the medium layer at the top of the trench 220, thereby weakening the deposition rate when depositing the medium layer again at the top of the trench. Since the treatment effect at the bottom of the trench 220 is weaker, the deposition rate is less affected, thus reducing the occurrence of top hanging in the trench 220 and preventing premature sealing of the trench 220, thereby reducing the porosity formed during the deposition of the medium layer using the HARP process.

[0060] Figure 2E A cross-sectional structural diagram of a stress medium layer planarization process according to an embodiment of this application is shown.

[0061] like Figure 2E As shown, the stress medium layer 250 in the aforementioned trench and on the upper surface of the semiconductor structure 210 is planarized so that the upper surface of the retained stress medium layer 250 is flush with the upper surface of the semiconductor structure 210.

[0062] Specifically, chemical mechanical polishing (CMP) can be used in the planarization process.

[0063] The above describes the process flow for selectively depositing media layers with different stress performances in trenches.

[0064] In an embodiment of forming a compressive stress dielectric layer, when forming a compressive stress dielectric layer using the method 100 of the present application embodiment of depositing a stress dielectric layer in a trench, the trench is provided in the region of the semiconductor structure for forming a PMOS device.

[0065] The method for forming a compressive stress medium layer includes: a first deposition process, wherein a first medium layer is deposited in a first trench using a HARP process based on a set first deposition thickness; a first plasma process, wherein the entire film of the first medium layer is subjected to a first plasma process using a plasma containing an inert gas based on a set first plasma process power and a first plasma process time, wherein the first deposition thickness of the first medium layer does not exceed the processing depth of the first plasma process at the first plasma process power and the first plasma process time; and the first deposition process and the first plasma process are repeatedly performed based on a set first number of cycles until the first trench is filled to form a compressive stress medium layer in the first trench.

[0066] Specifically, during the formation of the compressive stress medium layer, a first medium layer with a first deposition thickness is deposited in the first trench using the HARP process. Considering that the maximum processing depth of plasma treatment under high power and long duration conditions is approximately 100 Å, the aforementioned first deposition thickness is set to no more than 100 Å, preferably 50 Å to 100 Å, and exemplary values ​​include 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, and 100 Å. Other values ​​within the aforementioned range are also possible and are not limited here. In some embodiments, during the first deposition process, the pressure in the chamber can be set to 500 torr to 600 torr.

[0067] Next, the dielectric layer is treated with plasma containing an inert gas, wherein the inert gas is Ar or He. The first plasma treatment power is 300W~500W, and can be 300W, 320W, 340W, 360W, 380W, 400W, 420W, 440W, 460W, 480W, 500W, etc., or other values ​​within the above range, which are not limited here. The first plasma treatment time is 10s~15s, and can be 10s, 11s, 12s, 13s, 14s, 15s, etc., or other values ​​within the above range, which are not limited here. The chamber pressure of the first plasma treatment is 20 torr~50 torr, and can be 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc., or other values ​​within the above range, which are not limited here. In plasma processing, lower chamber pressure results in more stable plasma and more uniform processing. However, when the first deposition process and the first plasma process are performed in the same chamber, frequent switching between their respective required pressures is necessary because the two processes are executed cyclically. This pressure switching can have several negative effects, such as causing deposits to peel off from the chamber walls or components, leading to particulate contamination; since pressure switching is usually achieved through gas extraction, when high-flow-rate gas extraction is used to save time, the airflow may agitate particles on semiconductor devices, causing contamination, and so on. Therefore, in some embodiments of this application, the chamber pressure of the plasma process can be increased to minimize the pressure difference between the deposition process and the plasma processing process, thereby reducing the adverse effects of pressure switching.

[0068] Then, the first deposition process and the first plasma process are cycled 25 to 35 times, for example, 25, 26, 27, 28, 30, 31, 33, 35, etc., until the aforementioned trench is filled. A compressive stress dielectric layer with a compressive stress of -100 MPa to -50 MPa is formed in the aforementioned trench. It is understood that the number of cycles may depend on the depth of the trench to be filled and the thickness of the dielectric layer obtained after a single cycle.

[0069] In an embodiment of forming a tensile stress dielectric layer, when forming a tensile stress dielectric layer using the method 100 of the present application embodiment of depositing a stress dielectric layer in a trench, the trench is provided in the region of the semiconductor structure for forming an NMOS device.

[0070] The method for forming a tensile stress dielectric layer includes: a second deposition process, wherein a second dielectric layer is deposited in a second trench using a HARP process based on a set second deposition thickness; a second plasma process, wherein the surface of the second dielectric layer is subjected to a second plasma process using a plasma containing an inert gas based on a set second plasma process power and a second plasma process time, wherein the second deposition thickness of the second dielectric layer exceeds the processing depth of the second plasma process under the second plasma process power and the second plasma process time; and the second deposition process and the second plasma process are performed repeatedly based on a set second cycle number until the second trench is filled to form a tensile stress dielectric layer in the second trench.

[0071] Specifically, during the formation of the tensile stress dielectric layer, a second dielectric layer with a second deposition thickness is deposited in the second trench using the HARP process. Considering that the maximum processing depth of plasma treatment under high power and long duration conditions is approximately 100 Å, the aforementioned second deposition thickness is set to exceed 100 Å, preferably 150 Å to 200 Å. Exemplary values ​​include 150 Å, 160 Å, 170 Å, 180 Å, 190 Å, and 200 Å, and other values ​​within the aforementioned range are also possible and are not limited here. In some embodiments, the pressure in the chamber during the second deposition process can be set to 500 torr to 600 torr.

[0072] Next, the dielectric layer is treated with plasma containing an inert gas, wherein the inert gas is Ar or He. The second plasma treatment power is 150W~250W, and can be 150W, 160W, 170W, 180W, 190W, 200W, 210W, 220W, 230W, 240W, 250W, etc., or other values ​​within the above range, which are not limited here. The second plasma treatment time is 5s~10s, and can be 5s, 6s, 7s, 8s, 9s, 10s, etc., or other values ​​within the above range, which are not limited here. The chamber pressure of the second plasma treatment is 20 torr~50 torr, and can be 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc., or other values ​​within the above range, which are not limited here. The reason for setting the chamber pressure is the same as above and will not be repeated here.

[0073] Then, the second deposition process and the second plasma process are cycled 10 to 20 times, for example, 10, 11, 12, 14, 15, 16, 18, 20 times, etc., until the aforementioned trench is filled. A tensile stress dielectric layer with a tensile stress of 100 MPa to 150 MPa is formed in the aforementioned trench. It is understood that the number of cycles may depend on the depth of the trench to be filled and the thickness of the dielectric layer obtained after a single cycle.

[0074] In the two embodiments described above, since chemical vapor deposition is performed through a thermal process in the HARP process, the surface of the dielectric layer deposited by the HARP process has more -CH3, -H, and -OH equivalent bonds, which are relatively loose. After the dielectric layer is deposited by the HARP process, that is, after the dielectric layer comes out of the high temperature environment, the dielectric layer will shrink more than the semiconductor structure containing Si elements, exhibiting tensile stress.

[0075] In the aforementioned embodiment for forming a tensile stress dielectric layer, the dielectric layer deposited in a single cycle is relatively thick, for example, exceeding the processing depth of subsequent plasma treatment. Since the processing time for treating this dielectric layer with a low-power plasma containing Ar or He is short, the plasma treatment only affects the surface structure of the dielectric layer, leaving the underlying layer relatively porous. A tensile stress dielectric layer can still be obtained by performing the dielectric layer deposition and plasma treatment steps multiple times. Compared to the embodiment for forming a compressive stress dielectric layer, fewer cycles are required to fill trenches of the same depth because the dielectric layer obtained in a single cycle is thicker. Furthermore, plasma treatment of the dielectric layer reduces the voids formed during the HARP process, resulting in a denser tensile stress dielectric layer.

[0076] In the aforementioned embodiment for forming a compressive stress dielectric layer, the thickness of the dielectric layer deposited in a single cycle is relatively thin, for example, not exceeding the processing depth of the subsequent plasma treatment. The processing time for treating this dielectric layer with a high-power plasma containing Ar or He is longer, allowing the plasma treatment to penetrate the entire film layer, thus making the entire film layer denser, not just limited to the surface. When the steps of depositing the dielectric layer and the plasma treatment are performed through multiple cycles, the resulting stress dielectric layer shrinks less compared to a semiconductor structure containing Si, thus obtaining a compressive stress dielectric layer. Compared to the embodiment for forming a tensile stress dielectric layer, because the dielectric layer obtained in a single cycle is thinner, more cycles are required to fill trenches of the same depth. Similarly, by treating the dielectric layer with plasma, the voids formed during the deposition of the dielectric layer using the HARP process can be reduced, resulting in a denser compressive stress dielectric layer.

[0077] CMOS technology typically combines NMOS and PMOS transistors to achieve complementary functions. Therefore, embodiments of this application also provide a method for simultaneously forming stress dielectric layers in NMOS and PMOS regions to meet the stress requirements of different regions, while improving the performance of both NMOS and PMOS devices.

[0078] Figure 3 An exemplary flowchart of a method 300 for depositing a stress medium layer in a trench, according to other embodiments of this application, is shown.

[0079] like Figure 3 As shown, in step S310, a semiconductor structure is provided, having a first region and a second region. The first region is used to form a PMOS device and has at least one first trench. The second region is used to form an NMOS device and has at least one second trench. Next, in step S320, a compressive or tensile dielectric layer is formed, at least in the first trench of the first region and in the second trench of the second region. In step S330, the compressive dielectric layer in the second region is removed, or the tensile dielectric layer in the first region is removed. Then, in step S340, a tensile dielectric layer is formed in the second trench of the second region, or a compressive dielectric layer is formed in the first trench of the first region.

[0080] Specifically, the aforementioned steps S320 and S340 can be completed on the same machine, which can reduce material transfer and machine changeover time, thereby significantly improving production efficiency, reducing equipment investment and space occupation, and thus reducing production costs. In addition, completing steps S320 and S340 on the same machine can better control the production process and reduce errors.

[0081] based on Figure 3 The preparation process of method 300 for depositing stress medium layer in trench is described below in conjunction with Figures 4A-4G The schematic diagram of the semiconductor cross-sectional structure illustrates an exemplary process flow for depositing a stress dielectric layer in a trench using some embodiments of this application. Note that only one implementation of the aforementioned method is described here, namely, forming the dielectric layer of the first trench first, and then forming the dielectric layer of the second trench. Those skilled in the art can similarly deduce the process flow implementation of another implementation, which will not be elaborated here.

[0082] Figure 4A A cross-sectional structural schematic diagram of a semiconductor structure having a first region and a second region is shown in an embodiment of this application.

[0083] like Figure 4AAs shown, a semiconductor structure 410 is provided, having a first region 420 and a second region 430. The first region 420 has a first trench 440, and the second region 430 has a second trench 450. The first region is used to form a PMOS device, and the second region is used to form an NMOS device.

[0084] In the embodiments of this application, the first region 420 may have one or more grooves, and the second region 430 may also have one or more grooves, but it is guaranteed that at least one groove is present in each of the first region 420 and the second region 430.

[0085] In the embodiments of this application, the semiconductor structure 410 may include a substrate 411, an oxide layer 412 and a nitride layer 413 sequentially stacked on the substrate 411. The semiconductor structure 410 may have the same structure and materials as the aforementioned semiconductor structure 210, which will not be repeated here.

[0086] In the embodiments of this application, the first trench 440 and the second trench 450 extend from the surface of the nitride layer 413 away from the substrate 411 toward the substrate 411, penetrate the nitride layer 413 and the oxide layer 412, and extend into the interior of the substrate 411. The process used to form the first trench 440 and the second trench 450 is the same as the process used to form the trench 220, and the shape of the first trench 440 and the second trench 450 can be the same as the shape of the trench 220, which will not be described in detail here.

[0087] Figure 4B A cross-sectional structural diagram of the formation of the first stress medium layer according to an embodiment of this application is shown.

[0088] like Figure 4B As shown, a first stress medium layer 460 is formed in the first trench of the first region 420, the upper surface of the first region 420, the second trench of the second region 430, and the upper surface of the second region 430. In some embodiments of this application, the first stress medium layer may also be formed only in the first trench of the first region 420 and the second trench of the second region 430, or the first stress medium layer may be formed in the first trench of the first region 420, a portion of the upper surface of the first region 420, the second trench of the second region 430, and a portion of the upper surface of the second region 430, but at least the deposited first stress medium layer must cover the first trench of the first region 420 and the second trench of the second region 430. In this embodiment, the first stress medium layer is a compressive stress medium layer.

[0089] Figure 4C A cross-sectional structural diagram of photoresist formed over a first stress dielectric layer according to an embodiment of this application is shown.

[0090] like Figure 4CAs shown, a photoresist layer 470 is deposited above the first stress dielectric layer 460. The photoresist layer 470 can be either positive or negative photoresist.

[0091] Figure 4D This diagram shows a cross-sectional structure of the photoresist layer in the second region being dissolved according to an embodiment of this application.

[0092] like Figure 4D As shown, when the photoresist layer 470 is a positive resist, the photoresist layer in the second region 430 is exposed. After exposure, the properties of the photoresist layer in the second region 430 change, and it becomes easier to dissolve. Then, the photoresist layer 470 is developed. After development, the photoresist layer in the second region 430 is dissolved, leaving only the photoresist layer in the first region 420.

[0093] When the photoresist layer 470 is a negative resist, the photoresist layer in the first region 420 is exposed. After exposure, the properties of the photoresist layer in the first region 420 change, and it becomes less soluble. Then, the photoresist layer 470 is developed. After development, the photoresist layer in the second region 430 is dissolved, leaving only the photoresist layer in the first region 420.

[0094] The photoresist layer of the second region 430 is removed by exposure and development processes, so that the surface of the first stress dielectric layer of the second region 430 is exposed.

[0095] Figure 4E A cross-sectional structural diagram of the first stress dielectric layer after removing the second region and the remaining photoresist layer according to an embodiment of this application is shown.

[0096] like Figure 4E As shown, the first stress dielectric layer 460 in the second trench of the second region 430 is removed by an etching process using the photoresist layer in the first region. Then, the photoresist layer in the first region is removed.

[0097] Specifically, the aforementioned etching process can be a dry etching process, a wet etching process, or a combination of dry and wet etching processes. When using a dry etching process, the etching gas can be a gas containing fluorine, chlorine, or bromine. When using a wet etching process, the wet etching solution can be hydrofluoric acid. When using a combination of dry and wet etching processes, dry etching can be performed first using plasma containing fluorine, chlorine, or bromine gas, followed by cleaning with hydrofluoric acid solution, thereby completely removing the first stress medium layer 460 in the second trench of the second region 430.

[0098] Figure 4F A cross-sectional structural diagram of the formation of the second stress medium layer according to an embodiment of this application is shown.

[0099] like Figure 4FAs shown, a second stress medium layer 480 is formed on the upper surface of the first stress medium layer 460, in the second trench of the second region 430, and on the upper surface of the second region 430. In some embodiments of this application, the second stress medium layer may also be formed only in the second trench of the second region 430, or in the upper surface of the first stress medium layer 460 and the second trench of the second region 430, or in a portion of the upper surface of the first stress medium layer 460 and the second trench of the second region 430, or in a portion of the upper surface of the first stress medium layer 460, the second trench of the second region 430, and a portion of the upper surface of the second region 430, but at least the deposited second stress medium layer must cover the second trench of the second region 430. In this embodiment, the second stress medium layer is a tensile stress medium layer.

[0100] Figure 4G This illustration shows a cross-sectional structural diagram of a first stress medium layer and a second stress medium layer planarized according to an embodiment of this application.

[0101] like Figure 4G As shown, the aforementioned first stress dielectric layer 460 and second stress dielectric layer 480 are planarized so that the upper surfaces of the retained first stress dielectric layer 460 and second stress dielectric layer 480 are flush with the upper surface of the semiconductor structure 410.

[0102] Specifically, chemical mechanical polishing (CMP) can be used in the planarization process.

[0103] In the above embodiments, by forming stress dielectric layers of different types of stress in the trenches of the first region 420 and the second region 430 respectively, when the first region 420 and the second region 430 are used to form different MOS devices, stress dielectric layers that help improve the performance of the MOS device can be purposefully filled in the trenches, thereby improving the performance of the formed device.

[0104] Figure 5 A schematic diagram illustrating the effect of plasma processing power and cycle number on the stress performance of the dielectric layer is shown. In this diagram, the final dielectric layer thickness is the same for all cases, for example, 1500 Å. The figure shows the dielectric layer stress performance under four different conditions: At point A, the plasma processing power is 150W, the cycle is 15 times, and the dielectric layer stress is 137MPa. At point B, the plasma processing power is 200W, the cycle is 15 times, and the dielectric layer stress is 110MPa. At point C, the plasma processing power is 300W, the cycle is 30 times, and the dielectric layer stress is -48MPa. At point D, the plasma processing power is 500W, with 30 cycles, and the dielectric layer stress is -90MPa.

[0105] Therefore, since the final dielectric layer thickness is the same, fewer cycles result in a larger film thickness deposited per cycle. With lower plasma processing power, only the surface of the film is treated, resulting in a more porous dielectric layer. Consequently, when returning from a high-temperature environment to room temperature, the dielectric layer shrinks more than the substrate, exhibiting tensile stress. Conversely, with the same final dielectric layer thickness, more cycles result in a smaller film thickness deposited per cycle. Increased plasma processing power removes more functional groups from the dielectric layer, treating the entire layer and making it denser with a lower coefficient of thermal expansion. Consequently, when returning from a high-temperature environment to room temperature, the dielectric layer shrinks less than the silicon substrate, exhibiting compressive stress.

[0106] Therefore, embodiments of this application can deposit a dielectric layer in the trench by introducing a plasma treatment process into HARP, using a deposition-surface treatment cyclic deposition mode. During the deposition process, dielectric layers with different stress performances can be obtained by adjusting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the plasma treatment time in each cycle, thereby improving device performance.

[0107] In summary, compared with the prior art, the unexpected technical effect of this application is that it can selectively deposit medium layers with different stresses in the trench as needed.

[0108] This application embodiment controls the stress performance of the stress dielectric layer by setting or adjusting the number of cycles, deposition thickness, plasma processing power, and plasma processing time. Different stress dielectric layers can be selectively deposited in the trenches as needed. Thus, a tensile stress dielectric layer is formed in the trenches used to form NMOS devices, and a compressive stress dielectric layer is formed in the trenches used to form PMOS devices, improving the carrier mobility in the corresponding regions and thereby enhancing the performance of the corresponding devices.

[0109] This application also provides a shallow trench isolation structure. The dielectric layer in the trench of the shallow trench isolation structure can be prepared by the aforementioned method 100 for depositing a stress dielectric layer in the trench or by the method 300 for depositing a stress dielectric layer in the trench. The specific structure of the shallow trench isolation structure can be referred to the preceding description of the process flow and corresponding semiconductor cross-sectional structure in conjunction with the accompanying drawings, and will not be repeated here.

[0110] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for depositing a stressed dielectric layer in a trench, characterized in that: include: A first deposition process, based on a set first deposition thickness, depositing a first dielectric layer in the first trench by using a HARP process; A first plasma treatment, based on a set first plasma treatment power and a set first plasma treatment time, using a plasma containing an inert gas to perform a first plasma treatment on the entire film layer of the first dielectric layer, wherein the first deposition thickness of the first dielectric layer does not exceed a treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; Based on the set first cycle number, the first deposition process and the first plasma process are performed for multiple cycles until the first trench is filled to form a compressive stress dielectric layer in the first trench.

2. The method according to claim 1, characterized in that The compressive stress of the compressive stress medium layer is -100MPa~-50MPa.

3. The method according to claim 1, characterized in that The method satisfies at least one of the following conditions: The first deposition thickness is 50Å~100Å; The first plasma treatment power is 300W~500W; The first plasma treatment time is 10s to 15s; The inert gas is Ar or He; The first cycle number is 25 to 35 times; The chamber pressure of the first deposition process is 500 torr to 600 torr; and The chamber pressure of the first plasma treatment is 20 torr~50 torr.

4. The method according to claim 1, characterized in that: The first trench is disposed in a region of the semiconductor structure for forming a PMOS device.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: a second deposition process, depositing a second dielectric layer in the second trench by using a HARP process based on a set second deposition thickness; second plasma treatment, based on the set second plasma treatment power and second plasma treatment time, using plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds the treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; Based on the set second cycle number, the second deposition process and the second plasma process are performed for multiple cycles until the second trench is filled to form a tensile stress dielectric layer in the second trench.

6. The method according to claim 5, characterized in that The tensile stress of the tensile stress medium layer is 100MPa-150MPa.

7. The method according to claim 5, characterized in that The method satisfies at least one of the following conditions: The second deposition thickness is 150Å~200Å; The second plasma treatment power is 150W~250W; The second plasma treatment time is 5s to 10s; The inert gas is Ar or He; The second cycle number is 10 to 20 times; The chamber pressure of the second deposition process is 500 torr to 600 torr; and The chamber pressure of the second plasma treatment is 20 torr~50 torr.

8. The method according to claim 5, characterized in that The second trench is disposed in a region of the semiconductor structure for forming an NMOS device.

9. A method for depositing a stressed dielectric layer in a trench, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure has a first region and a second region, wherein the first region is used to form a PMOS device and has at least one first trench, and the second region is used to form an NMOS device and has at least one second trench; forming a compressive stress dielectric layer or a tensile stress dielectric layer at least in the first trench of the first region and in the second trench of the second region; removing the compressive stress dielectric layer in the second region or removing the tensile stress dielectric layer in the first region; forming a tensile stress dielectric layer in the second trench of the second region or forming a compressive stress dielectric layer in the first trench of the first region; in: The compressive stress dielectric layer is formed according to the method according to any one of claims 1 to 3.

10. The method according to claim 9, characterized in that The tensile stress dielectric layer is formed according to the following method: A second deposition process, based on the set second deposition thickness, depositing a second dielectric layer in the groove by using a HARP process; A second plasma treatment, based on a set second plasma treatment power and a set second plasma treatment time, using a plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds a treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; Based on the set second cycle number, the second deposition process and the second plasma process are performed for multiple cycles until the trench is filled to form a tensile stress dielectric layer in the trench.

11. A shallow trench isolation structure, characterized in that: The dielectric layer in the trench of the shallow trench isolation structure is prepared by the method according to any one of claims 1 to 10.

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