Transistor device with edge termination structure and method

Abstract

The invention discloses a transistor device with an edge termination structure and a method.

Description

Technical Field

[0001] The present disclosure relates generally to transistor devices and, more particularly, to vertical transistor devices having edge termination structures. Background Art

[0002] A vertical transistor device is a transistor device in which the source region of the transistor cell is spaced apart from the drain region of the transistor device in the longitudinal direction of the semiconductor body. The source region may be positioned proximate to a first surface of the semiconductor body, and the drain region may be positioned proximate to a second surface opposite to the first surface. The side surface (sidewall) of the semiconductor body is a surface that terminates the semiconductor body in a lateral direction perpendicular to the first surface and the second surface.

[0003] The transistor unit can be arranged in an inner region of the semiconductor body, wherein the inner region is surrounded by an edge region in a lateral direction. Typically, a vertical transistor device is designed so that an edge region in a section close to the sidewall is connected to a drain region. In this case, an edge termination structure arranged in the edge region absorbs a voltage that may appear between the drain region and the source region when the transistor device is in an off state. The voltage blocking capability is the maximum voltage that the transistor device can withstand in the off state. The edge termination structure can be configured to absorb a voltage that is at least equal to or higher than the voltage blocking capability.

[0004] Each transistor cell includes a gate electrode, which is dielectrically insulated from the semiconductor body by a gate dielectric and is configured to control the operating state of the transistor device. Typically, the gate-controlled transistor device can be operated in a reverse operating mode (diode mode). This is an operating mode in which a body diode formed between the body region and the drift region of the transistor cell is turned on. Operating the transistor device in diode mode is associated with a charge carrier plasma, which is formed in the drift region and includes a first type (e.g., electrons) and a second type (e.g., holes) of charge carriers. When the transistor device changes from diode mode to an off state, the charge carriers that form the charge carrier plasma must be removed from the inner region of the semiconductor body and the drift region in the edge region.

[0005] An example of an edge termination structure is disclosed in US 2020 / 0105918 A1. Summary of the invention

[0006] There is a need for an edge termination structure that can withstand voltages that may develop between the interior region and the edge region of a transistor device and that can efficiently remove charge carriers from the edge region after the transistor device has been operated in a diode mode.

[0007] One example relates to a transistor device. The transistor device includes: a semiconductor body, which includes an inner region and an edge region; a drain region of a first doping type, which is arranged in the inner region and the edge region; a plurality of transistor units, which are at least partially integrated in the inner region of the transistor device; and an edge termination structure. The edge termination structure includes an edge trench, which extends from a first surface of the semiconductor body into the edge region and includes a trench bottom and an inner trench sidewall facing the inner region. The edge termination structure also includes: a first insulating layer, which covers the trench bottom and the inner trench sidewall; a first edge region of a second doping type complementary to the first doping type, which is arranged adjacent to the inner trench sidewall and connected to the source node of the transistor device; a first field electrode, which is arranged above the first insulating layer, connected to the gate node of the transistor device, and at least partially overlaps with the inner trench sidewall in a first lateral direction of the semiconductor body.

[0008] Another example relates to a transistor device. The transistor device includes: a semiconductor body, which includes an inner region and an edge region; a drain region of a first doping type, which is arranged in the inner region and in the edge region; a plurality of transistor cells, which are at least partially integrated in the inner region of the transistor device; and an edge termination structure. The edge termination structure includes an edge trench, which extends from a first surface of the semiconductor body into the edge region and includes a trench bottom and an inner trench sidewall facing the inner region; a first insulating layer, which covers the trench bottom and the inner trench sidewall; a first edge region of a second doping type complementary to the first doping type, which is connected to a source node of the transistor device and extends from the trench bottom to the first surface of the semiconductor body adjacent to the inner trench sidewall; and a first field electrode, which is arranged above the first insulating layer and connected to a gate node of the transistor device.

[0009] Yet another example relates to a method. The method includes: forming an edge termination structure of a transistor device. Forming the edge termination structure includes: forming an edge trench in an edge region of a semiconductor body, such that the edge trench includes a trench bottom and an inner trench sidewall facing an inner region of the semiconductor body; and forming a first edge region of a second doping type adjacent to the inner trench sidewall. Forming the first edge region includes implanting dopant atoms of the second doping type into at least the inner trench sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and only the aspects necessary for understanding these principles are shown. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent the same features.

[0011] Figure 1 schematically illustrates a vertical cross-sectional view of a portion of a transistor device including a semiconductor body having an inner region and an edge region, a transistor cell in the inner region, and an edge termination structure;

[0012] Figure 2-5 Shows Figure 1 Different modifications of the edge termination structure shown in;

[0013] Figure 6 shows transistor cells according to an example, each transistor cell including a gate electrode;

[0014] Figure 7 An example of a gate electrode is shown in more detail;

[0015] Figure 8 Shows Figure 1 a more detailed vertical cross-sectional view of a portion of a transistor device of the type shown in;

[0016] Fig. 9 Shows Figure 8 A modification of the edge termination structure shown in;

[0017] Figures 10A-10B 10 respectively show a top view of a transistor device according to an example;

[0018] Fig.11 In with Figure 8 The vertical cross-sections shown in the different vertical cross-sections are shown in Figure 8 a vertical cross-sectional view of a transistor device of the type shown;

[0019] Fig.12 Shown based on Figure 3-Figure 5 The edge termination structure of any of and including the edge termination structure of the additional features;

[0020] Figure 13-15 and Figures 16A-16D Various examples of methods for forming doped regions of edge termination structures are shown; and

[0021] Fig.17 Shows Figures 16A-16C A modification of the method shown in . DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of the specification and show examples of how the invention may be used and implemented for illustrative purposes. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically noted.

[0023] Figure 1Schematically illustrates a transistor device according to an example. More specifically, Figure 1 A vertical cross-sectional view of a portion of a transistor device is schematically shown.The transistor device comprises a semiconductor body 100 having a first surface 101 and a second surface 102 opposite to the first surface. Figure 1 The transistor device is shown in a vertical cross section substantially perpendicular to the first surface 101 and the second surface 102 .

[0024] According to one example, the semiconductor body 100 includes a single-crystalline semiconductor material, such as silicon (Si) or silicon carbide (SiC).

[0025] refer to Figure 1 , the semiconductor body 100 includes an inner region 130 and an edge region 140. The edge region 140 surrounds the inner region 130 in a lateral direction, which is a direction substantially parallel to the first surface 101 and the second surface 102. In the following, “the inner region of the transistor device” refers to those regions of the transistor device including the inner region 130 of the semiconductor body 100 and the sections of the transistor device adjacent to the first surface 101 in the vertical direction z and adjacent to the second surface 102 in the vertical direction z. In addition, “the edge region of the transistor device” refers to those regions of the transistor device including the edge region 140 of the semiconductor body 100 and the sections of the transistor device adjacent to the first surface 101 and the second surface 102 in the vertical direction z. The vertical direction z is a direction perpendicular to the first surface 101 and the second surface 102.

[0026] refer to Figure 1 , the transistor device comprises a drain region 13 of the first doping type. The drain region 13 is arranged in the inner region 130 and the edge region 140 of the semiconductor body 100 and may adjoin the second surface 102 .

[0027] Furthermore, the transistor device comprises a plurality of transistor cells 10 at least partially integrated in the inner region 130 of the semiconductor body 100. “At least partially integrated” includes that at least parts of the transistor cells are integrated in the semiconductor body and other parts may be arranged on top of the first surface 101. The transistor cells 10 are not Figure 1 Alternatively, the transistor unit 10 is represented by a circuit symbol of a transistor.

[0028] For illustrative purposes only, Figure 1 The circuit symbol shown in represents an N-type transistor device, in particular an N-type enhancement (normally closed) MOSFET. However, this is only an example. The transistor device is not limited to being implemented as an N-type transistor device, but may also be implemented as a P-type transistor device. In addition, the transistor device is not limited to being implemented as a normally closed device, but may also be implemented as a normally open device.

[0029] refer to Figure 1 , the transistor device further comprises an edge termination structure 20. The edge termination structure 20 comprises an edge trench 6 extending from the first surface 101 of the semiconductor body 100 into the edge region 140. The edge trench comprises a trench bottom 61 and an inner trench sidewall 62, the inner trench sidewall 62 being the sidewall of the edge trench facing the inner region 130. The edge trench further comprises an outer trench sidewall opposite to the inner trench sidewall 62. The outer trench sidewall is not Figure 1 and are further explained below.

[0030] The edge termination structure 20 further comprises a first insulating layer 51 covering the trench bottom 61 and the inner trench sidewalls 62. According to an example, the first insulating layer 51 completely fills the edge trench 6.

[0031] The edge termination structure 20 further comprises a first edge region 71 of a second doping type complementary to the first doping type. The first edge region 71 is arranged adjacent to the inner trench sidewall 62 and is connected to the source node S of the transistor device. According to an example, the first edge region 71 extends along the entire inner trench sidewall 62 from the trench bottom 61 to the first surface 101 of the semiconductor body 100.

[0032] Furthermore, the edge termination structure 20 comprises a first field electrode 31. The first field electrode 31 is arranged above the first insulating layer 51 and is connected to the gate node G of the transistor device. The first field electrode 31 at least partially overlaps with the inner trench sidewall 62 of the edge trench 6. That is, the projection of the first field electrode 31 on the edge trench 6 in the vertical direction z overlaps with the inner trench sidewall 62. Figure 1 In FIG. 5 , ovl represents the overlap amount between the first field electrode 31 and the inner trench sidewall 62 .

[0033] The first field electrode 31 comprises, for example, doped polysilicon.

[0034] At least part of the inner surface 62 is inclined relative to the vertical direction z, so that the inner groove sidewall 62 has a specific width w62 that is not zero in the first lateral direction x. The first lateral direction x is substantially parallel to the first surface 101 and the second surface 102. According to an example, the edge groove 6 is elongated in the second lateral direction y perpendicular to the first lateral direction x. The width w62 of the inner groove sidewall 62 in the first lateral direction x is, for example, between 0.5 micrometers and 2 micrometers, in particular between 0.8 micrometers and 1.2 micrometers.

[0035] The source node S is a circuit node of the transistor device connected to the source region of the transistor cell 10. The gate node G of the transistor device is a circuit node connected to the gate electrode of the transistor cell 10. An example of a transistor cell including a source region and a gate electrode is further explained below. In addition to the source node S and the gate node G, the transistor device also includes a drain node D. The drain node D is a circuit node connected to the drain region 13 or formed by the drain region 13.

[0036] The first field electrode 31 is, for example, a planar electrode. According to an example, the first field electrode 31 is arranged in a horizontal plane, which is spaced apart from the first surface 101 of the semiconductor body 100 in the vertical direction z. To this end, the first field electrode 31 may be arranged on top of the second insulating layer 52, wherein a portion of the second insulating layer 52 is arranged on top of the first insulating layer 51, and other portions may be formed on top of the first surface 101.

[0037] The second insulating layer 52 is only Figure 1 The second insulating layer 52 and the first insulating layer 51 filling the edge trench 6 may be formed by the same process, so that the first insulating layer 51 and the second insulating layer 52 may be part of a continuous insulating layer formed by the same manufacturing process.

[0038] Referring to the above, at least a portion of the inner groove sidewall 62 is inclined relative to the vertical direction z, so that the edge groove widens toward the first surface 101. For illustration purposes only, Figure 1 The inner groove sidewall 62 shown in FIG. 1 is curved so that different inclination angles relative to the vertical direction z exist at different positions of the inner groove sidewall 62 . However, this is only an example. Figure 2 In another example shown, the inner groove sidewall 62 is substantially straight. In each of the examples explained above, an edge groove 8 having a curved inner groove sidewall 62 or a substantially straight inner groove sidewall 62 can be used.

[0039] Forming the edge trench 6 may include an isotropic etching process using an etching mask formed on top of the first surface 101. In the process, portions of the semiconductor body 100 are removed in a direction perpendicular to the first surface 101 and in a lateral direction under the etching mask, thereby obtaining inclined inner and outer trench sidewalls. This type of method is well known, so no further explanation is needed in this regard.

[0040] Figure 3-5 Shows Figure 1 and Figure 2 Various modifications of the edge termination structure 20 are shown. For illustrative purposes only, Figure 3-5In the example shown, the inner groove sidewalls 62 are curved.

[0041] refer to Figure 3 , the edge termination structure 20 may further include a second edge region 81 of the first doping type. The second edge region 81 is arranged adjacent to the trench bottom 61 in the vertical direction z and adjacent to the first edge region 71 in the first lateral direction x. In addition, the edge termination structure 20 may include a third edge region 72 of the second doping type. The third edge region 72 is adjacent to the first edge region 71 and the second edge region 82 in the vertical direction z.

[0042] refer to Figure 4 , the first field electrode 31 may completely overlap the inner trench sidewall 62. In this example, the overlap amount ovl is equal to the width w62 of the inner trench sidewall in the first lateral direction x. In the first lateral direction x, the first field electrode 31 may extend beyond the inner trench sidewall 62 in the direction of the inner region 130. In this example, Figure 4 As shown, the first field electrode 31 overlaps a portion of the first edge region 71 adjoining the inner trench sidewall 62. According to an example (not shown), the first field electrode 31 extends beyond the first edge region 71 in the direction of the inner region 130 in the first lateral direction x.

[0043] refer to Figure 5 , the first edge region 71 may include three parts (segments): a first part 711, which extends along the inner groove sidewall 62; a second part 712, which extends in the first lateral direction x in the direction of the inner region 130 and along the first surface 101 away from the inner groove sidewall 62; and a third part 713, which extends in the lateral direction x away from the inner region 130 along a portion of the groove bottom 61. The dimension d1 of the second part 712 in the first lateral direction x is, for example, between 1 micron and 15 microns, in particular, between 3 microns and 10 microns. The dimension d2 of the third part 713 in the first lateral direction x is, for example, between 1 micron and 15 microns, in particular, between 2 microns and 5 microns.

[0044] Referring to the above, the transistor device includes a plurality of transistor cells 10 at least partially integrated in the inner region 130 of the semiconductor body 100 . Figure 6 Schematically shows a transistor unit 10 according to an example. More specifically, Figure 6 A vertical cross-sectional view of a portion of a semiconductor body 100 is shown in which the transistor cell 10 is formed.

[0045] refer to Figure 6Each transistor cell 10 includes a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, is dielectrically insulated from the body region 12 by a gate dielectric 22, and is arranged in a gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0046] refer to Figure 6 , the source region 11 and the body region 12 of two adjacent transistor cells 10 can be arranged in the mesa region between adjacent gate trenches 120. In this example, the body region 12 of the two adjacent transistor cells 10 can be formed by one continuous doping region of the second doping type. In addition, the two (other) adjacent transistor cells can share the gate electrode 21. That is, the gate electrode 21 of the two adjacent transistor cells can be formed by one continuous electrode arranged in one gate trench 120.

[0047] The gate electrode 21 includes a conductive material. Examples of the conductive material include doped polysilicon or metals such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), etc. The gate dielectric 22 includes, for example, an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0048] Referring to the above, the source region 11 of the transistor cell 10 is connected to the source node S of the transistor device. Figure 6 , the transistor device may include a source electrode 41, wherein the source electrode 41 forms a source node S or is connected to the source node S. The source electrode 41 includes a conductive material, such as aluminum (Al), copper (Cu), or aluminum-copper alloy (AlCu).

[0049] The source electrode 41 is electrically connected to the source region 11 and the body region 12 of the transistor cell 10. Figure 6 The connection between the source electrode 41 and the source region 11 and the body region 12 is only schematically shown in FIG. Such connection can be realized using conductive vias extending from the source electrode 41 through the insulating layer 53 to the source region 11 and the body region 12. This is well known and therefore no further explanation is needed in this regard.

[0050] The insulating layer 53 is formed on top of the first surface 101 and the gate electrode 21, and separates the source electrode 41 from the semiconductor body 100 and the gate electrode 21. The insulating layer 53 may include a portion of the second insulating layer 52 explained heretofore.

[0051] refer to Figure 6The transistor device further comprises a drift region 14 of the first doping type. The drift region 14 is adjacent to the body region 12 of the transistor cell 10, so that a PN junction is formed between the body region 12 and the drift region 14. In addition, in the vertical direction, the drift region 14 is arranged between the body region 12 and the drain region 13.

[0052] Optionally, a buffer region 16 of the first doping type is arranged between the drift region 14 and the drain region 13 , and a doping concentration of the buffer region 16 is higher than a doping concentration of the drift region 14 and lower than a doping concentration of the drain region 13 .

[0053] refer to Figure 6 , the gate trenches with the gate electrode 21 are spaced apart from each other in the third lateral direction x1. The third lateral direction x1 is perpendicular to the vertical direction z of the semiconductor body 100 and may correspond to the first lateral direction x explained above. According to one example, the gate electrode 21 is implemented as a strip electrode (long strip electrode). In this example, the gate electrode 21 is long in a fourth lateral direction y1 perpendicular to the third lateral direction x1. The fourth lateral direction y1 may correspond to the second lateral direction y explained above.

[0054] Figure 7 An example of the long gate electrode 21 is shown in FIG. Figure 7 Shown in Figure 6 A portion of the semiconductor body 100 is shown in a first horizontal cross section BB which cuts through a gate trench 120 with a gate electrode 21 and a gate dielectric 22. The horizontal cross section BB is substantially parallel to the first surface 101 and the second surface 102.

[0055] According to one example, the transistor device is implemented as a super junction transistor device. In this example, the transistor device comprises a plurality of compensation regions 15 (shown in dashed lines) spaced apart from each other in a lateral direction of the semiconductor body 100. Each compensation region 15 is adjacent to a corresponding portion of the drift region 14.

[0056] For illustrative purposes only, Figure 6 In the example shown, the compensation regions 15 are spaced apart from one another in the third lateral direction x1. According to another example (not shown), the compensation regions 15 are spaced apart from one another in the fourth lateral direction y1.

[0057] The transistor device can be operated in an on state or an off state. In the on state, a conductive path exists along the gate dielectric in the body region 12 between the source region 11 and the drift region 14. To this end, the drift region 14 adjoins the gate dielectric 22 and the body region 12 of at least one transistor cell 10.

[0058] Furthermore, each optional compensation region 15 is adjacent to at least a portion of the drift region 14 and is connected to the source electrode 41. Figure 6 In the example shown, each compensation region 15 adjoins the body region 12 of at least one transistor cell and is connected to the source electrode 41 via the respective body region 12 .

[0059] The transistor device can be operated in a conventional manner by applying a driving voltage (gate-source voltage) between the gate electrode 21 and the source electrode 41. The transistor device is in an on-state (conducting state) when the driving voltage causes a conductive path to be generated in the body region 12 along the gate dielectric 22 between the source region 11 and the drift region 14. When the conductive path is interrupted, the transistor device is in an off-state (blocking state).

[0060] The transistor device can be implemented as an N-type transistor device or a P-type transistor device. For example, when the driving voltage is higher than a predefined positive threshold voltage, the N-type transistor device is in an on state, and when the driving voltage is lower than the threshold voltage, the N-type transistor device is in an off state.

[0061] In an N-type transistor device, the doped region of the first doping type is an N-type region, and the doped region of the second doping type is a P-type region. In a P-type transistor device, the doped region of the first doping type is a P-type region, and the doped region of the second doping type is an N-type region.

[0062] The source region 11, the body region 12, the drift region 14, the compensation region 15, the buffer region 16 and the drain region 13 may also be referred to as active device regions. In an N-type transistor device, the doping concentration of the active device region is selected from the following ranges, for example:

[0063] Source region 11: 5E19 cm -3 -5E20 cm -3 ;

[0064] Body area 12: 3E19 cm -3 -3E20 cm -3 ;

[0065] Drain area 13: 5E18 cm -3 -5E20 cm -3 ;

[0066] Drift region 14: 7E15 cm -3 -7E16 cm -3 ;

[0067] Compensation area 15: 7E15 cm -3 -7E16 cm -3 ;

[0068] Buffer area 16: 5E15 cm -3 -5E16 cm -3 ;

[0069] Body contact area 17: 1E20 cm -3 -1E21 cm -3 .

[0070] Figure 8 Shown in more detail Figure 1 An example of a transistor device of the type shown. More specifically, Figure 8 A vertical cross-sectional view of a portion of a semiconductor body 100 is shown, wherein Figure 8 The portion of the semiconductor body 100 shown in illustrative figures includes portions of an inner region 130 and an edge region 140 .

[0071] Figure 8 The transistor device shown includes Figure 6 A transistor cell of the type shown. In addition, Figure 8 The transistor device shown includes Figure 5 The edge termination structure 20 of the type shown is, however, only an example. Figure 8 Any other types of edge termination structures explained previously herein may also be implemented in the transistor device.

[0072] Figure 8 The transistor cell shown is a superjunction transistor cell which, in addition to the drift region 14, also comprises a compensation region 15. According to one example, Figure 8 As shown, the drift region and the compensation region are arranged not only in the inner region 130 but also in the edge region 140. Hereinafter, the drift region arranged in the edge region 140 is referred to as the edge drift region 14', and the compensation region arranged in the edge region 140 is referred to as the edge compensation region 15'. In the vertical direction z, the edge drift region 14' and the edge compensation region 15' may be spaced farther from the first surface 101 than the drift region 14 and the compensation region 15 in the inner region 130.

[0073] Referring to the above, the source region 11 and the body region 12 of the transistor cell are connected to the source electrode 41. Figure 8 In one example shown, the source region 11 and the body region 12 are connected to the source electrode 41 through a conductive via 42, and the conductive via 42 extends from the source electrode 41 through the insulating layer 53 into the semiconductor body 100 to the source region 11 and the body region 12. Optionally, each transistor cell includes a body contact region 17 of the second doping type, which provides an ohmic contact between the body region 12 and the corresponding conductive via 42. The body contact region 17 has a higher doping concentration than the body region 12.

[0074] Referring to the above, the first edge region 71 is connected to the source node S of the transistor device. Figure 8 In the example shown, the first edge region 71 is connected to the source electrode 41 by at least one conductive via 43. Optionally, a contact region 18 of the second doping type adjoins the via and provides an ohmic contact between the via 43 and the first edge region 71. The contact region 18 has a higher doping concentration than the first edge region 71.

[0075] refer to Figure 8 , the transistor device further comprises a gate runner 44 which is spaced apart from the first field electrode 31 in the vertical direction z and is electrically connected to the first field electrode 31. The gate runner 44 is arranged on top of the insulating layer 5. Portions of the insulating layer 5 separate the gate runner 44 from the first field electrode 31. The insulating layer 5 is arranged between the first surface 101 on one side and the gate runner 44 and the source electrode 41 on the other side. The third insulating layer 53 and the second insulating layer 52 described heretofore are part of the insulating layer 5.

[0076] Referring to the above, the first field electrode 31 is connected to the gate node G. As further explained below, the gate runner 44 is connected to the gate node G. Figure 8 In the example of , to connect the first field electrode 31 to the gate node G, the first field electrode 31 is connected to the gate runner 44 through a conductive via 45 extending from the gate runner 44 down to the first field electrode 31 in the insulating layer 5 .

[0077] The semiconductor body 100 forming the transistor device may include several epitaxially grown epitaxial layers, which are stacked on top of each other and into which dopant atoms are implanted before forming the next epitaxial layer. In particular, drift regions 14, 14', compensation regions 15, 15' and third edge regions 72 may be formed in this manner. The source region 11 and the body region 12 may be formed by implanting dopant atoms into the semiconductor body 100 via the first surface 101 after each epitaxial layer has been formed. The drain region 13 may be formed by a semiconductor substrate on top of which an epitaxial layer is grown.

[0078] The epitaxial layer has a (low) basic doping, for example as low as intrinsic. After forming the various device regions explained before, regions with basic doping including the epitaxial layer may remain in the semiconductor body 100. Examples of those regions with basic doping are Figure 8 BD and is labeled with reference characters BD.

[0079] refer to Figure 8The plurality of transistor cells include an edge transistor cell, which is one of the transistor cells closest to the edge region 140. The edge transistor cell may include a source region 11 (at Figure 8 Alternatively, the source region 11 is omitted in the edge transistor unit.

[0080] According to an example, the body region 12 of the edge transistor unit extends in the lateral direction to the first edge region 71. Figure 8 In the example shown, the third lateral direction x3 in which the gate electrodes 21 of the transistor cells 10 are spaced apart from one another corresponds to the first lateral direction x of the edge termination structure 20. In the present example, the body region 12 extends to the first edge region 71 in the first lateral direction x and in the third lateral direction x1.

[0081] exist Figure 8 In the example shown, the first field electrode 31 completely overlaps the inner trench sidewall 62 and partially overlaps the first edge region 71. However, the first field electrode 31 does not completely overlap the first edge region 71, so that the first edge region 71 can be directly connected to the source electrode 41 through the conductive via 43.

[0082] Fig. 9 Shown according to Figure 8 A modification of the transistor device. Fig. 9 In the example shown, the first field electrode 31 completely overlaps the first edge region 71. In this example, the conductive via 43 connects the source electrode 41 to the body region 12 of the edge transistor cell and in this way connects the first edge region 71 adjoining the body region 12 to the source electrode 41.

[0083] Fig. 10A and Fig. 10B 1 and 2 show a top view of a transistor device according to an example. More specifically, Fig. 10A and Fig. 10B Both show a top view of a semiconductor body 100 in which a source electrode 41 and a gate runner 44 are formed on top of an insulating layer 5. Fig. 10A and 10B The gate runner 44 surrounds the source electrode 41 in a lateral direction of the semiconductor body 100 .

[0084] The transistor device further includes a gate pad 45 connected to the gate runner 44. The gate pad 45 forms a gate node G of the transistor device or is connected to the gate node G of the transistor device. Fig. 10A and 10B As shown, the gate pad 45 may abut the gate runner 44. Alternatively, the gate pad 45 is spaced apart from the gate runner 44, and a resistor (gate resistor) is connected between the gate pad 45 and the gate runner 44.

[0085] exist Fig. 10A In the example shown, the gate pad 45 is arranged at a position substantially in the middle between two opposite side walls 103, 106 of the semiconductor body 100. Fig. 10B In the example shown in FIG. 4 , the gate pad 45 is arranged at a position close to a corner formed by two adjacent side walls 105 , 106 of the semiconductor body 100 .

[0086] Transistor unit in Fig. 10A and 10B For illustration purposes, the positions of the three gate electrodes 21 relative to the source electrode 41 and the gate runner 44 are shown in FIG. Fig. 10A and 10B In the figure, the thick line is shown. Fig. 10A and Fig. 10B In the example shown, the gate electrodes 21 are elongated electrodes, wherein the longitudinal directions of these gate electrodes 21 correspond to the second lateral direction y and the fourth lateral direction y1 explained previously herein. Figure 6 A vertical cross-sectional view of a transistor cell is shown. Fig. 10A and 10B The cross-sectional view in section AA is shown. For example, Figure 8 and 9 A vertical cross-sectional view of an edge transistor cell and an adjacent portion of an edge region is shown. Fig. 10A and 10B Cross-sectional view in section CC shown.

[0087] The edge termination structure 20 surrounds the inner region 130 of the semiconductor body 100 in the lateral direction. Figure 8 and Fig. 9 , a portion of the edge termination structure 20 arranged adjacent to the inner region 130 in a first lateral direction x is shown, wherein the first lateral direction x is equivalent to a third lateral direction x3, wherein the gate electrodes 21 of the respective transistor units are spaced apart from each other in the third lateral direction x3, and the third lateral direction x3 is perpendicular to the longitudinal direction of the gate electrode 21. Figure 8 and Fig. 9 The edge termination structure 20 shown in FIG. 1 is arranged between the inner region 130 of the semiconductor body 100 and the inner region 130 of the semiconductor body 100. Fig. 10A and Fig. 10B On the opposite side, that is, between the inner region 130 and the opposite side wall 105, the edge termination structure is Figure 8 and Fig. 9 Same as shown in .

[0088] According to an example, the edge termination structure 20 includes, around the inner region 130, at least an edge trench 6 and a first insulating layer 51, a first edge region 71 and a first field electrode 31 surrounding the inner region 130 in a lateral direction. That is, the edge trench 6, the first insulating layer 51, the first edge region 71 and the first field electrode 31 all form a closed loop around the inner region 130. According to an example, the second edge region 81 and the third edge region 72 also form corresponding closed loops around the inner region 130.

[0089] Fig.11 1 shows a vertical cross-sectional view of an edge termination structure 20 arranged between the longitudinal ends of the gate trench 21 and the sidewalls of the semiconductor body 100. In addition to the edge termination structure 20, Fig.11 The gate electrode 21 of a transistor unit is also shown. For example, Fig.11 The vertical cross-section shown is Figures 10A-10B The cross-sectional view is shown in section DD. In this example, Fig.11 The edge termination structure shown in FIG is arranged between the inner region and the second side wall 104 which is perpendicular to the first side wall 103. On the opposite side, that is, between the inner region 130 and the opposite side wall 106, the edge termination structure is arranged between the inner region 130 and the second side wall 104 which is perpendicular to the first side wall 103. Fig.11 Same as shown in .

[0090] According to one example, each gate electrode 21 is connected to a gate runner 44 at at least one longitudinal end. Fig.11 The diagram shows the Fig.11 4 is an example of a gate electrode 21 connected to a gate runner 44. In this example, the gate electrode 21 is connected to the first field electrode 31 via a contact finger 32 extending from the first field electrode 31 to the gate electrode 21. The first field electrode 31 and the contact finger can be formed by the same process, so that the first field electrode 31 and the contact finger 32 are formed by one continuous electrode layer. The electrode layer is a conductive layer, such as a doped polysilicon layer.

[0091] Referring to the above, the first edge region 71 is connected to the source electrode 41. Fig.11 In the example shown, the source electrode 41 is connected to the first edge region 71 at a position spaced apart from the contact finger 32, so that Fig.11 The connection between the source electrode 41 and the first edge region 71 is not shown.

[0092] The figures explained heretofore show a part of the edge termination structure 20 in a section of the edge region 140 adjoining the inner region 130. The rest of the edge termination structure is not shown in these figures. Fig.12 A vertical cross-sectional view of the entire edge termination structure 20 according to one example is shown in FIG. Fig.12The edge termination structure shown is based on Figure 4 and Figure 5 An edge termination structure of one of the following. For example, Fig.12 The cross-sectional view shown in Fig. 10A and Fig. 10B The cross-sections CC and DD shown in FIG. Fig.12 The edge termination structure 20 is shown as a portion arranged between the inner region 130 and the first surface 103 or between the inner region 130 and the second surface 104. The edge termination structure 20 may be arranged between the inner region 130 and the third and fourth surfaces 105, 106. Fig.12 The same method is shown.

[0093] refer to Fig.12 , the edge trench 6 comprises an outer trench sidewall 63, which is a trench sidewall facing the corresponding sidewall 103, 104 of the semiconductor body 100. According to an example, the edge termination structure 20 further comprises a second field electrode 32 arranged above the first insulating layer 51. According to an example, the second field electrode 32 at least partially overlaps the outer trench sidewall 63. The other trench sidewall 63 may have the same shape as the inner trench sidewall 62. According to an example, the second field electrode 32 is connected to the drain runner 46. The drain runner 46 is arranged on top of the insulating layer 5 and is spaced apart from both the source electrode 41 and the gate runner 44 in the lateral direction. The drain runner 46 comprises a conductive material, such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu) or an alloy of one or more of these materials.

[0094] According to an example, the drain runner 46 is connected to the second field electrode 32 through a conductive via 47 , which extends from the drain runner 46 through a portion of the insulating layer 5 to the second field electrode 32 .

[0095] The drain runner 46 is arranged between the gate runner 44 and the sidewalls 103, 104, 105, 106 of the semiconductor body 100. According to one example, the drain runner 46 forms a closed loop around the source electrode 41, the gate runner 44 and the gate pad 45. Fig. 10A and Fig. 10B In FIG. 4 , the drain channel 46 is not shown.

[0096] refer to Fig.12 , the edge termination structure 20 may further include a field stop region 73 of the first doping type. The field stop region 73 extends along the sidewalls 103, 104 between the first surface 101 and the buffer region 16 (as shown) or the drain region 13. The field stop region 73 surrounds the inner region 120. That is, the field stop region 73 forms a closed loop around the inner region 130. According to an example, the drain runner 46 is electrically connected to the field stop region 73.

[0097] The drain runner 46 may be connected to the field stop region 73 at one or more locations. The drain runner 46 may be connected to the field stop region 73 through a conductive via 48 extending from the drain runner 46 through the insulating layer 52 to a portion of the field stop region 73. According to one example, the drain runner 46 is connected to the field stop region 73 only in the region of the four corners of the semiconductor body 100.

[0098] refer to Fig.12 , the edge termination structure 20 may further include a third field electrode 33, which is arranged in a trench extending from the first surface 101 into the field stop region 73. The third field electrode 33 is dielectrically insulated from the semiconductor body 100 by a field electrode dielectric 53. The third field electrode 33 includes a conductive material such as doped polysilicon. The field electrode dielectric 53 includes, for example, an oxide. The third field electrode 33 is electrically connected to the drain runner 46, for example, through a conductive via 49.

[0099] refer to Fig.12 The second and third edge regions 81 , 72 may extend beyond the edge trench 6 and the third field electrode 33 in the first lateral direction x in a direction away from the inner region 130 . Fig.12 According to another example (shown in solid lines), the second and third edge regions 81 , 72 end below the edge groove 6 in the first lateral direction x.

[0100] The transistor device explained previously herein can be operated in diode mode. This is an operating mode in which a voltage is applied between the drain node D and the source node S, which forward biases the PN junction between the drift region 14 and the body region 12 of the transistor cell 10. For example, when a positive voltage is applied between the drain node D and the source node S, and when the transistor cell is driven so that the conductive path along the gate dielectric 22 in the body region 12 is interrupted, the N-type transistor device is in diode mode.

[0101] In the described operating mode, a charge carrier plasma comprising charge carriers of a first type (e.g. electrons) and a second type (e.g. holes) is generated in the drift region 14. When the transistor device switches from the diode mode to the off state, i.e. the operating mode in which the PN junction is reverse biased and the conducting channel in the transistor cell 10 is interrupted, the charge carrier plasma must be removed from the drift region 14, 14'. When the transistor device switches from the diode mode to the off state, the majority charge carriers, which are electrons in an N-type transistor device, are collected by the drain region 13 and the optional buffer region 16. The minority charge carriers, which are holes in an N-type transistor device, are collected by the body region 12 of the transistor cell 10 in the inner region 130 of the transistor device. In the edge regions of the transistor device, the first edge region 71 and the optional third edge region 72 efficiently collect the minority charge carriers and thus provide an increased robustness of the transistor device in the transition between the diode mode and the off state.

[0102] Furthermore, the edge termination structure 20 with the first insulating layer 51 and the optional second and third edge regions 81, 72 efficiently absorbs the drain-source voltage in the edge region of the transistor device. The drain-source voltage is the voltage applied between the drain node D and the source node S. Due to the field stop region 73 connected to the drain region 13, the voltage applied between the drain node D and the source node S also appears between the edge surfaces 103-106 of the transistor device and the inner region 130. The first electrode 31 connected to the gate node G and overlapping the inner trench sidewall 62 forms the electric field in the edge region in an advantageous manner, so that the edge termination structure 20 can withstand the voltage occurring between the sidewall and the inner region.

[0103] The maximum voltage that may occur between the sidewall and the inner region 130 depends on the voltage blocking capability of the transistor device. The voltage blocking capability of the transistor device is, for example, 600 V or higher.

[0104] The first edge region 71, the second edge region 81 and the third edge region 72 can be produced in different ways. Fig.13 , Fig.14 , Fig.15 and Figure 16A-16B An example for forming these edge regions 71 , 81 , 72 is explained. The figures each show a portion of a semiconductor body 100 during a corresponding manufacturing process.

[0105] according to Fig.13 In one example shown, forming the first edge region 71 includes implanting the second type of dopant atoms into at least the inner trench sidewall 62 of the edge trench 6. The second type of dopant atoms are implanted into the inner trench sidewall 62 to form the first segment 711 of the first edge region 71 (see Figure 5According to one example, the second type dopant atoms are also implanted into the section of the first surface 101 adjacent to the inner trench sidewall 62 and into the section of the trench bottom 61 adjacent to the trench sidewall to form the second and third sections 712, 713 of the first edge region 71 (see Figure 5 ).

[0106] The implantation process uses an implantation mask having openings defining regions of the semiconductor body 100 where dopant atoms are to be implanted. The implantation mask 301 is a mask formed on top of the semiconductor body 100 (as shown) or a metal mask spaced apart from the first surface 101 of the semiconductor body.

[0107] according to Fig.13 In one example shown, the direction of implanting the second type of dopant atoms is substantially equal to the vertical direction z. In this case, the implantation angle relative to the vertical direction z is 0.

[0108] according to Fig.14 In another example shown, the implantation process is a tilted implantation process. The implantation angle relative to the vertical direction z is selected, for example, between 2° and 10°. In addition, the implantation angle makes the implantation direction tilted toward the inner trench sidewall 62, thereby Fig.13 The implant dose into the trench sidewalls 62 is increased compared to the example shown.

[0109] Referring to the above, the edge trench 6 surrounds the inner region 130 in the lateral direction of the semiconductor body 100. In this example, the edge trench 6 includes four different inner trench sidewalls, so that the tilted implantation process can include four tilted implantation processes, each for implanting the second type dopant atoms into one of the four different inner trench sidewalls.

[0110] The implantation dose is selected, for example, from 1E13 cm -2 and 5E13 cm -2 According to one example, the implantation dose is a dose of doping atoms implanted in a region perpendicular to the implantation direction. The implantation energy is selected between 120 keV and 180 keV. The doping atoms are, for example, boron atoms.

[0111] The second type dopant atoms are implanted to produce a first implanted region 71' in the semiconductor body 100. In addition to implanting the second type dopant atoms, forming the first edge region 71 may include an annealing process in which the implanted second type dopant atoms are activated (and may diffuse in the semiconductor body 100).

[0112] The optional third edge region 72 may be formed before forming the first edge region 71. According to one example, Fig.13 and Fig.14Prior to the implantation process shown, doping atoms for forming the third edge region 72 are introduced into the semiconductor body 100. In the present example, the implanted atoms forming the first and third edge regions 71, 72 may be activated using the same annealing process or different annealing processes.

[0113] according to Fig.15 In one example shown, forming the second edge region 81 may include implanting first type dopant atoms into the trench bottom 61 using another implantation mask 302. In addition to implanting the first type dopant atoms, forming the second edge region 81 may include an annealing process to activate the implanted first type dopant atoms. The first type dopant atoms used to form the second edge region 81 may be implanted into the semiconductor body before or after implanting the second type dopant atoms used to form the first edge region 71. The same annealing process or different annealing processes may be used to activate the second type dopant atoms implanted to form the first edge region 71 and the first type dopant atoms implanted to form the second edge region 81.

[0114] Referring to the above, the semiconductor body 100 may include a plurality of epitaxial layers formed one above the other, the uppermost of which forms a first surface 101 in which edge trenches 6 are formed and into which doping atoms may be implanted to form source regions 11 and body regions 12 of the transistor cell 10 .

[0115] Fig.16A The epitaxial layer 100 is schematically shown n-1 The epitaxial layer 100 is a portion of the uppermost epitaxial layer grown on top of the epitaxial layer. n-1 According to one example, forming the third edge region 72 includes implanting the second type of dopant atoms into the penultimate epitaxial layer 100 using the implantation mask 303. n-1 In the embodiment, the implantation mask 303 defines the epitaxial layer 100 n-1 The second type of doping atoms are implanted to generate an implantation region 72' comprising the second type of doping atoms. In addition to implanting the second type of doping atoms, forming the third edge region 72 also includes an annealing process to activate the implanted doping atoms.

[0116] Referring to the above, forming the second edge region 81 may include implanting dopant atoms into the trench bottom 61. Alternatively, Fig. 16B As shown, forming the second edge region 81 includes implanting first type dopant atoms into the penultimate epitaxial layer using another implantation mask 304. Implanting the first type dopant atoms produces an implantation region 81', wherein forming the second edge region 81 includes an annealing process to activate (and diffuse) the implanted first type dopant atoms.

[0117] refer to Fig. 16C and Fig.16D The method further comprises forming a second-to-last epitaxial layer 100 n-1 The uppermost epitaxial layer 100 is formed on the top of n , and forming an edge trench 6 in the semiconductor body 100. According to one example, the edge trench 6 is formed only in the uppermost epitaxial layer 100. n According to another example (not shown), the edge trench 6 extends through the uppermost epitaxial layer 100 n Enter the penultimate epitaxial layer 100 n-1 part.

[0118] exist Fig.16A and Fig. 16B The annealing process for activating the implanted dopant atoms in the illustrated process may be performed after implanting the dopant atoms for forming the first edge region 71 .

[0119] exist Figures 16A-16D In the method shown, the doping concentration of the third edge region 72 is substantially determined by Fig.16A The implant dose definition in the implant process is shown.

[0120] According to an example, the third edge region 72 is formed such that the doping concentration in the third edge region 72 decreases in the first lateral direction x in a direction away from the inner region 130 . Fig.16A In another implantation process before or after the implantation process shown, the second type of dopant atoms are implanted into the penultimate epitaxial layer 100. n-1 In this case, a third edge region 72 of this type can be formed. Fig.17 Shown in.

[0121] Fig.17 The penultimate epitaxial layer 100 is shown during another implantation process. n-1 A vertical cross-section of Fig.17 The dashed line shows the process of implanting the Fig.16A The implantation process shown forms implanted regions 72'.

[0122] exist Fig.17 In another implantation process shown, the second type of dopant atoms are implanted into the second to last epitaxial layer 100 using an implantation mask 305. n-1 In the embodiment, the implantation mask 305 includes a plurality of openings 306 spaced apart from each other in the lateral direction x. In another implantation process, the second type dopant atoms are implanted into the penultimate epitaxial layer 100 through the openings 306. n-1 to form another implantation region 72'' which locally increases the Fig.16A The implantation process shown provides the implantation dose.

[0123] The width and mutual distance of the openings 306 in the first lateral direction x define a gradient of doping concentration in the finished third edge region 72. According to an example, the width and / or mutual distance increase from opening to opening 306 in a direction away from the inner region 130. According to an example, the further implantation mask 305 is such that in a further implantation process, the second type of doping atoms are implanted only into those regions of the finished device that are located below the first edge region 71, so as to provide a gradient of doping concentration in the third edge region 72 in the region below the first edge region 71.

Claims

1. A transistor device, comprising: A semiconductor body (100) comprising an inner region (130) and an edge region (140); a drain region (13) of a first doping type, arranged in the inner region (130) and the edge region (140); A plurality of transistor cells (10) at least partially integrated in an inner region (130) of the transistor device; as well as edge termination structure (20), Wherein, the edge termination structure (20) comprises: an edge trench (6) extending from a first surface (101) of the semiconductor body (100) into the edge region (140) and comprising a trench bottom (61) and an inner trench sidewall (62) facing the inner region (130); A first insulating layer (51) covering the trench bottom (61) and the inner trench sidewalls (62); a first edge region (71) of a second doping type complementary to the first doping type, disposed adjacent to the inner trench sidewall (62) and connected to a source node (S) of the transistor device; and A first field electrode (31) is arranged above the first insulating layer (51), connected to a gate node (G) of the transistor device and at least partially overlaps the inner trench sidewall (62) in a first lateral direction (x) of the semiconductor body (100).

2. The transistor device according to claim 1, in, The first edge region (71) extends along the inner trench sidewall (62) from the trench bottom (61) to a first surface (101) in the semiconductor body (100).

3. A transistor device comprising: A semiconductor body (100) comprising an inner region (130) and an edge region (140); a drain region (13) of a first doping type, arranged in the inner region (130) and in the edge region (140); A plurality of transistor cells (10) at least partially integrated in an inner region (130) of the transistor device; as well as edge termination structure (20), Wherein, the edge termination structure (20) comprises: an edge trench (6) extending from a first surface (101) of the semiconductor body (100) into the edge region (140) and comprising a trench bottom (61) and an inner trench sidewall (62) facing the inner region (130); A first insulating layer (51) covering the trench bottom (61) and the inner trench sidewalls (62); a first edge region (71) of a second doping type complementary to the first doping type connected to a source node (S) of the transistor device and extending from the trench bottom (61) to a first surface (101) of the semiconductor body (100) adjacent to the inner trench sidewalls (62); and A first field electrode (31), which is arranged above the first insulating layer (51), is connected to a gate node (G) of the transistor device.

4. The transistor device according to claim 3, in, The first field electrode (31) at least partially overlaps the inner trench sidewall (62) in a first lateral direction (x) of the semiconductor body (100).

5. The transistor device according to any one of claims 2 to 4, in, The first edge region (71) extends along the first surface (101) by a first distance (d1) in the first lateral direction (x).

6. The transistor device according to claim 5, in, The first distance (d1) is between 1 micrometer and 15 micrometers.

7. A transistor device according to any one of the preceding claims, in, The first field electrode (31) completely overlaps the inner trench sidewall (62) in the first lateral direction (x).

8. The transistor device according to claim 7, in, The first field electrode (31) extends beyond the inner trench sidewall (62) in the first lateral direction (x).

9. A transistor device according to any one of the preceding claims, in, The first edge region (71) extends along the groove bottom (61) by a second distance (d2) in the first lateral direction (x).

10. The transistor device according to claim 9, in, The second distance (d2) is between 1 micrometer and 15 micrometers.

11. A transistor device according to any one of the preceding claims, in, The edge termination structure (20) further comprises a second edge region (81) of the first doping type, The second edge region (81) is arranged adjacent to the trench bottom (61) in the vertical direction (z) of the semiconductor body (100), and is arranged adjacent to the first edge region (71) in the first lateral direction (x).

12. A transistor device according to any one of the preceding claims, in, The edge termination structure (20) further comprises a third edge region (72) of the second doping type, Wherein, the third edge region (72) is adjacent to the first edge region (71) in the vertical direction (z).

13. The transistor device according to any one of the preceding claims, further comprising: A gate runner (44) is connected to the first field electrode and is spaced apart from the first surface (101) in a vertical direction (z).

14. A transistor device according to any one of the preceding claims, wherein: The edge termination structure (20) further comprises: a field stop region (73) of the first doping type adjoining a side wall of the semiconductor body (100), A second field electrode (32) is arranged above the first insulating layer (51) and connected to the field stop region (73).

15. The transistor device according to claim 14, further comprising: A drain runner (46) is connected to the second field electrode (32) and the field stop region (73) and is spaced apart from the first surface (101) in a vertical direction (z).

16. The transistor device according to claim 15, wherein: The edge termination structure (20) further comprises: a third field electrode (33), The third field electrode (33) is arranged in a field electrode trench extending from the first surface (101) into the semiconductor body (100), is dielectrically insulated from the semiconductor body (100) by a field electrode dielectric (53), and is connected to the drain channel (46).

17. The transistor device according to any one of claims 13 to 16, in, Each of the transistor cells (10) comprises a gate electrode (21) connected to the gate runner (44).

18. The transistor device according to claim 17, in, The transistor device also includes a source electrode (41), and Each of the transistor units (10) comprises a source region connected to the source electrode (41).

19. The transistor device according to any one of claims 13 to 18, in, The gate runner (44) and the source electrode (41) are arranged above a first surface (101) of the semiconductor body (100).

20. A transistor device according to any one of the preceding claims, in, The drain region (13) is arranged adjacent to a second surface (102) of the semiconductor body (100) opposite to the first surface (101).

21. The transistor device according to any one of the preceding claims, further comprising: a plurality of drift regions (14, 14') of the first doping type in the inner region (130) and the edge region (140), and A plurality of compensation regions (15, 15') of the second doping type in the inner region (130) and the edge region (140).

22. A transistor device according to any one of the preceding claims, in, The semiconductor body (100) further comprises sidewalls, and Wherein, the edge region (140) is arranged between the inner region (130) and the side wall.

23. A transistor device according to any one of the preceding claims, in, At least a portion of the inner trench sidewall (62) is inclined relative to a vertical direction (z).

24. A method comprising: forming an edge termination structure (20) of a transistor device, Wherein, forming the edge termination structure (20) comprises: forming an edge trench (6) in an edge region (140) of a semiconductor body (100), such that the edge trench (6) comprises a trench bottom (61) and an inner trench sidewall (62) facing an inner region (130) of the semiconductor body (100); and forming a first edge region (71) of a second doping type adjacent to the inner trench sidewall (62), Wherein, forming the first edge region (71) comprises implanting doping atoms of the second doping type at least into the inner trench sidewall (62).

25. The method according to claim 24, further comprising: forming a first insulating layer (51) covering the inner trench sidewalls (62) and the trench bottom (61), and A first field electrode (31) is formed which is arranged above the first insulating layer (51) and at least partially overlaps the inner trench sidewall (62) in a first lateral direction (x) of the semiconductor body (100).

26. The method according to claim 24 or 25, in, Implanting dopant atoms of the second doping type includes a tilted implantation process.

27. The method according to claim 26, in, The tilt angle during the implantation process is between 1° and 10° relative to a vertical direction (z) of the semiconductor body (100).

28. The method according to claim 27, in, The implantation dose in the implantation process is selected from 1E13 cm -2 and 5E13 cm -2 between.

29. The method according to claim 27 or 28, in, The implantation energy in the implantation process is selected from between 100 keV and 200 keV, in particular, between 120 keV and 180 keV.

30. The method according to any one of claims 24-29, further comprising: A second edge region (81) of a first doping type complementary to the second doping type is formed, so that the second edge region (81) is arranged adjacent to the trench bottom (61) in a vertical direction (z) of the semiconductor body (100) and adjacent to the first edge region (71) in a first lateral direction (x).

31. The method according to claim 30, in, Forming the second edge region (81) includes implanting doping atoms of the first doping type into the trench bottom (61).

32. The method according to claim 30, in, Forming the second edge region (81) includes implanting doping atoms into the first semiconductor layer (100 n-1 )middle, Wherein, in the first semiconductor layer (100 n-1 ) is formed on top of a second semiconductor layer (100 n ),and Wherein, in the second semiconductor layer (100 n ) is formed in the edge groove (6).

33. The method according to claim 32, further comprising: forming a third edge region (72) of the second doping type such that the third edge region (72) is adjacent to the first edge region (71) in a vertical direction (z) of the semiconductor body (100), Wherein, forming the third edge region (72) comprises implanting dopant atoms of the second doping type into the first semiconductor layer (100 n-1 )middle.

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