Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The cell comprises a silicon substrate, a semiconductor structure layer and a transparent conductive oxide layer, the semiconductor structure layer and the transparent conductive oxide layer are sequentially stacked on the two opposite sides of the silicon substrate, copper seed layers are distributed on the transparent conductive oxide layer at intervals, and copper grid line electrodes are arranged on the surfaces, away from the transparent conductive oxide layer, of the copper seed layers; a mixed layer is further arranged between the copper seed layer and the transparent conductive oxide layer opposite to the copper seed layer, and a light trapping structure layer with a pit structure on the surface is arranged on the area, not covered by the mixed layer, of the transparent conductive oxide layer; the mixed layer contains a metal material and a transparent conductive oxide, and the light trapping structure layer contains the same transparent conductive oxide as the mixed layer. The binding force between the transparent conductive oxide layer and the copper seed layer can be improved by means of the mixed layer, the contact resistance is reduced, the reflectivity of the cell to incident light can be reduced by means of the light trapping structure layer, and the photoelectric conversion efficiency of the cell can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Heterojunction solar cells have become a research hotspot in the photovoltaic field due to their advantages such as high open circuit voltage, high conversion efficiency, low temperature coefficient, low attenuation rate, and low stability in preparation process. In addition to semiconductor structure layers formed on the opposite sides of the silicon substrate for generating photogenerated electrons, this type of solar cell also includes grid electrodes located on each semiconductor structure layer to conduct the generated photogenerated electrons. In order to reduce the manufacturing cost of heterojunction solar cells, copper grid electrodes are highly praised by industry researchers.

[0003] The preparation process of copper grid electrodes in solar cells is generally as follows: first, a layer of transparent conductive oxide (TCO) is deposited on the semiconductor structure layer on both sides of the silicon substrate, and then a copper seed layer is deposited on the TCO layer by physical vapor deposition technology, and then a photoresist pattern layer is formed on the copper seed layer to define the grid pattern, and then the copper grid electrode is formed by electroplating; then the photoresist material and the copper seed layer not covered by the copper grid electrode are removed. However, the bonding force between the copper seed layer and the TCO layer is poor, and the contact resistance is high, which affects the stable operation of the solar cell and reduces the photoelectric conversion efficiency. Summary of the invention

[0004] In view of this, the present application provides a solar cell, a preparation method thereof, and a photovoltaic module, wherein a mixed layer containing TCO and a metal material is introduced between the copper seed layer and the TCO layer of the solar cell to enhance the pull-out force therebetween and reduce the interface contact resistance, thereby facilitating the stable operation of the solar cell and improving the photoelectric conversion efficiency. Furthermore, in the etching back stage after removing the photoresist layer, the surface of the mixed layer not covered by the copper grid electrode can be transformed into a light-trapping structure layer with a pit structure, thereby further improving the photoelectric conversion efficiency of the cell.

[0005] Specifically, the first aspect of the present application provides a solar cell, comprising: a silicon substrate, and a semiconductor structure layer and a transparent conductive oxide (TCO) layer stacked in sequence on opposite sides of the silicon substrate, wherein a copper seed layer is spaced apart on the TCO layer, and a copper grid electrode is provided on the surface of the copper seed layer facing away from the TCO layer; wherein a mixed layer is further provided between the copper seed layer and the TCO layer opposite thereto, and a light-trapping structure layer having a surface with a pit structure is provided on the area of ​​the TCO layer not covered by the mixed layer, wherein the mixed layer comprises a metal material and a transparent conductive oxide (TCO), and the light-trapping structure layer contains the same transparent conductive oxide as the mixed layer.

[0006] In the solar cell, the mixed layer containing TCO and metal material is arranged between the copper seed layer and the TCO layer located therebelow, and the mixed layer can be used to realize a smooth transition of the composition from the TCO layer to the copper seed layer, which is conducive to improving the bonding force between them and reducing the contact resistance, so that the copper grid electrode formed on the copper seed layer is not easy to peel off, and the contact resistance between the copper grid electrode and the TCO layer is low, which is conducive to the overall solar cell having a more stable structure and improving the photoelectric conversion efficiency. The TCO layer not covered by the copper grid electrode is provided with a light-trapping structure layer with a pit structure, which can reduce the reflectivity of the incident light, improve the utilization rate of light, and also help to improve the photoelectric conversion efficiency of the solar cell.

[0007] A second aspect of the present application provides a method for preparing a solar cell, comprising:

[0008] Providing a silicon substrate with a semiconductor structure layer and a transparent conductive oxide layer formed on two opposite surfaces;

[0009] forming a mixed layer of a metal-containing material and a transparent conductive oxide on the transparent conductive oxide layer;

[0010] forming a copper seed layer on the mixed layer and covering the mixed layer;

[0011] forming a copper gate electrode in a partial area on the copper seed layer;

[0012] The copper seed layer and the metal material in the mixed layer that are not covered by the copper gate electrode are removed.

[0013] In the process of preparing the solar cell, the present application introduces a mixed layer containing TCO and metal material between the TCO layer and the copper seed layer, which can improve the pull-out force between them, reduce the contact resistance, and facilitate the stable operation of the solar cell and improve the photoelectric conversion efficiency; and in the process of removing the copper seed layer not covered by the copper grid electrode, the metal material in the mixed layer not covered by the copper grid electrode can also be etched and converted into a light-trapping structure layer with a pit structure, further improving the photoelectric conversion efficiency of the cell. The preparation method of the solar cell is novel, the process is simple, and a solar cell with excellent performance can be prepared.

[0014] The third aspect of the present application provides a photovoltaic module, including the solar cell described in the first aspect of the present application, or the solar cell prepared by the preparation method described in the second aspect of the present application. Since the photovoltaic module has the above-mentioned solar cell with stable structure and high photoelectric conversion efficiency provided by the present application, the photovoltaic module has good market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A schematic structural diagram of a heterojunction solar cell in the prior art is shown.

[0016] Figures 2 to 7 This is a schematic structural diagram corresponding to each step in a method for preparing a solar cell provided in an embodiment of the present application.

[0017] Figure 8 A schematic diagram of the structure of a mixed layer formed in a method for preparing a solar cell provided in some embodiments of the present application. DETAILED DESCRIPTION

[0018] The technical solution of the embodiment of the present application is described in detail below.

[0019] The common structures of heterojunction solar cells are as follows: Figure 1 As shown in the figure, the preparation process is generally as follows: a TCO layer 3 is formed on a silicon substrate 1 having semiconductor structure layers 2 formed on opposite sides of the silicon substrate 1; a copper seed layer covering the TCO layer 3 is then deposited on the TCO layer 3 by physical vapor deposition technology; a photoresist pattern layer is then formed on the copper seed layer to define a gate line pattern; then, in the presence of the photoresist pattern layer, a copper gate line electrode 5 is formed by electroplating on the copper seed layer; finally, the photoresist pattern layer is removed and the copper seed layer is then etched back (referred to as "film stripping and back etching") to form a structure as shown in the figure. Figure 1 The patterned copper seed layer 4 shown completes the preparation of the copper grid electrode 5. However, the bonding force between the copper seed layer 4 and the TCO layer 3 is usually poor, and the contact resistance is high, which will affect the stable operation of the solar cell, reduce the photoelectric conversion efficiency, etc. Therefore, in order to improve the reliability and performance of the solar cell, the present application provides a solar cell and a preparation method thereof.

[0020] Specifically, the method for preparing a solar cell provided in the embodiment of the present application may include the following steps S01 to S06. Figures 2 to 7 This is a schematic diagram of the structures corresponding to each step in the solar cell preparation method provided in one embodiment of the present application.

[0021] Step S01, such as Figure 2 As shown, a silicon substrate 10 is provided, on both opposite surfaces of which semiconductor structure layers and transparent conductive oxide layers 30 (hereinafter referred to as TCO layers 30 ) are sequentially stacked.

[0022] Figure 2In the embodiment, a first semiconductor structure layer 20 is formed on one side surface (which may be referred to as the "front side") of the silicon substrate 10, and a second semiconductor structure layer 20' is formed on the other side surface (which may be referred to as the "reverse side"). The first semiconductor structure layer 20 may include a first intrinsic amorphous silicon layer 21a and a first doped amorphous silicon layer 22a arranged in a stacked manner; the second semiconductor structure layer 20' may include a second intrinsic amorphous silicon layer 21b and a second doped amorphous silicon layer 22b arranged in a stacked manner, and the first doped amorphous silicon layer 22a and the second doped amorphous silicon layer 22b contain different types of doping elements. The doping type of amorphous silicon may be N-type doping or P-type doping. That is, one of the first doped amorphous silicon layer 22a and the second doped amorphous silicon layer 22b is a P-type doped amorphous silicon layer, and the other is an N-type doped amorphous silicon layer. N-type doping refers to a semiconductor material with an N-type doping type and used for electron transmission, for example, the doping element is phosphorus. P-type doping refers to a semiconductor material whose doping type is P-type and is used for hole transport, for example, the doping element is boron.

[0023] In the present application, the silicon substrate 10 is a light absorption area, which improves the light absorption rate of the solar cell, provides support and growth environment for the subsequent film layer, and can form a heterojunction with the semiconductor structure layer thereon to realize the photoelectric conversion of the solar cell. Among them, the silicon substrate 10 can be an N-type crystalline silicon substrate or a P-type crystalline silicon substrate. In some embodiments of the present application, the silicon substrate 10 can be an N-type crystalline silicon substrate, the first doped amorphous silicon layer 22a is an N-type doped amorphous silicon layer, and the second doped amorphous silicon layer 22b is a P-type doped amorphous silicon layer. In this case, the silicon substrate 10 forms a PN heterojunction with the second doped amorphous silicon layer 22b as an emitter. The surface of the silicon substrate provided with the first semiconductor structure layer 20 is the main light-receiving surface of the silicon substrate 10, and the surface provided with the second semiconductor structure layer 20' is the backlight surface of the silicon substrate 10. Among them, N-type crystalline silicon has a good absorption capacity for sunlight. Under sunlight, hole-electron pairs are generated in N-type crystalline silicon. Under the action of the two semiconductor structure layers on its upper and lower sides, holes and electrons can be separated and current can be generated. Subsequently, the current can be derived with the help of gate line electrodes arranged on the semiconductor structure layers. In some other embodiments of the present application, the silicon substrate 10 is a P-type crystalline silicon substrate, the first doped amorphous silicon layer 22a is a P-type doped amorphous silicon layer, and the second doped amorphous silicon layer 22b is an N-type doped amorphous silicon layer.

[0024] In the embodiment of the present application, the silicon substrate 10 is a textured silicon substrate, and the surface has an inverted pyramid-shaped texture. The presence of the intrinsic amorphous silicon layer on the surface of the silicon substrate can play a passivation role, mainly passivating the surface defects of the silicon substrate 10, reducing the recombination of photogenerated electrons, and helping to improve the photoelectric conversion efficiency of the battery.

[0025] Figure 2In the embodiment of the present invention, the TCO layer 30 covers the surface of each semiconductor structure layer away from the silicon substrate 10. The TCO layer 30 can be formed by physical vapor deposition (PVD), and the specific PVD method can include but is not limited to sputtering (such as magnetron sputtering), evaporation plating, ion plating, or rapid plasma deposition (RPD). In the embodiment of the present application, the TCO layer 30 can be selected from one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), cerium-doped indium oxide (ICO), tungsten-doped indium oxide (IWO), phosphorus-doped tin dioxide (PTO), fluorine-doped tin dioxide (FTO), etc., but is not limited thereto. The thickness of the TCO layer 30 can be in the range of 60-100nm, for example, specifically 70nm, 75nm, 80nm, 85nm, 90nm or 95nm.

[0026] In some embodiments of the present application, the TCO layer 30 is an ITO layer. The sputtering target used to form the ITO layer may contain indium oxide (In2O3) and tin oxide (SnO2) at the same time, and the exemplary mass ratio of the two may be 97:3, 95:5, 90:10, etc. Wherein, forming the TCO layer includes: the pressure in the sputtering chamber where the substrate to be plated is placed is 0.1-0.5Pa, the argon flow rate is 100-300sccm, the oxygen flow rate is 1-15sccm, the rotation speed of the sample tray containing the substrate to be plated is 0.2-0.6m / min, the sputtering power of the magnetron sputtering target is controlled to be 2-6kW, and the target is sputtered at 100-200°C for a period of time to deposit and form a TCO layer on the substrate to be plated.

[0027] Step S02, depositing a mixed layer 40 containing a metal material and a transparent conductive oxide on the TCO layer 30, such as Figure 2 shown.

[0028] Figure 2 In the embodiment, the mixed layer 40 covers the surface of the TCO layer 30 facing away from the silicon substrate 10. The transparent conductive oxide (TCO) contained in the mixed layer 40 can be independently selected from one or more of ITO, AZO, ICO, IWO, PTO, FTO, etc. The metal material contained in the mixed layer 40 can include one or more of copper, silver, tin, indium, copper-nickel alloy, etc.

[0029] In the present application, a copper seed layer 50 is formed after a mixed layer 40 is formed on the TCO layer 30. Both the mixed layer 40 and the TCO layer 30 contain TCO, and both the mixed layer 40 and the copper seed layer 50 contain metal materials. In this way, the composition transition from the TCO layer 30 to the copper seed layer 50 can be smoothly achieved with the help of the mixed layer 40, thereby facilitating the improvement of the pull-out force (i.e., bonding force) and bonding strength between them, and reducing the difference in thermal expansion coefficients between the three, facilitating the stability of their stacked structure, and reducing the contact resistance between the TCO layer 30 and the copper seed layer 50. In addition, in the subsequent process of etching back the copper seed layer 50 after removing the photoresist pattern layer, the metal material in the mixed layer 40 not covered by the copper grid electrode 5 can also be etched to form a light trapping structure with a pit-like morphology, thereby reducing light reflection and improving the photoelectric conversion efficiency of the cell.

[0030] In some embodiments of the present application, the TCO material contained in the mixed layer 40 is the same as that in the TCO layer 30, and the metal material contained in the mixed layer 40 is copper (Cu). In this case, the bonding force between the mixed layer 40 and the TCO layer 30 located thereunder is stronger and the contact resistance is smaller, and the bonding force between the mixed layer 40 and the copper seed layer 50 formed thereon is stronger and the contact resistance is smaller. In addition, compared with other metal materials, copper is cheap and has a lower electrical conductivity, so the conductive performance of the mixed layer 40 can be better.

[0031] In the embodiment of the present application, in the mixed layer 40, the mass proportion of the metal material is 40%-70%, and the mass proportion of the TCO is 30%-60%. Controlling the mass proportion of the metal material in the mixed layer within an appropriately high range can ensure that the conductive performance of the mixed layer 40 is significantly better than that of the TCO layer 30, and the bonding force between the mixed layer 40 and the copper seed layer 50 is strong, the interface resistance is low, and in the subsequent film stripping and etching process, enough metal material in the mixed layer 40 can be etched away to form a light trapping structure. At the same time, the mixed layer 40 also contains more TCO, and the bonding strength between the mixed layer 40 and the TCO layer 30 is also high. Exemplarily, the mass proportion of the metal material in the mixed layer 40 can be 42%, 45%, 50%, 55%, 60%, 65%, or 68%, etc. The mass proportion of the TCO in the mixed layer 40 can be 32%, 35%, 40%, 45%, 50%, 55%, or 58%, etc.

[0032] The mixed layer 40 may be deposited by PVD. As mentioned above, the specific PVD method may include but is not limited to sputtering, evaporation, ion plating, or RPD, etc. Among them, the sputtering method for preparing the mixed layer 40 has high controllability and a wide process parameter window.

[0033] In some embodiments of the present application, forming the mixed layer 40 includes: first sputtering on the TCO layer 30 to form a discontinuously distributed metal material; and then sputtering on the TCO layer 30 to form a TCO distribution area filling the gaps of the metal material. In this case, the formed mixed layer 40 may include a TCO distribution area 41 and a metal material distribution area 42 distributed at intervals (see Figure 8 ). The TCO distribution area 41 and the metal material distribution area 42 are arranged alternately along the thickness direction of the vertical mixed layer 40. Among them, the TCO distribution area 41 contains only TCO material, and the metal material distribution area 42 contains only metal material. The alternating distribution of metal material and TCO material is more conducive to etching the metal material in part of the mixed layer 40 (i.e., the part of the mixed layer not covered by the copper grid electrode) in the subsequent film stripping and etching process to form a pit-shaped morphology that is more conducive to reducing light loss, and the light trapping effect is better.

[0034] Further, in some embodiments of the present application, in the mixed layer 40, the thickness of the TCO material (that is, the thickness of the TCO distribution area) is smaller than the grain size of the metal material. Accordingly, the thickness of the TCO distribution area 41 is smaller than the thickness of the metal material distribution area 42 (see Figure 8 ). Among them, the thickness of the TCO material is less than the grain size of the metal material, so that the TCO material prepared later can effectively fill the gaps of the discontinuously distributed metal material and will not cover / block the metal material grains, so that the metal material in the mixed layer 40 in the predetermined area can be easily removed during the subsequent film stripping and back etching; at the same time, the mixed layer 40 is formed by the staggered arrangement of TCO material areas and metal material areas of unequal thickness, and the upper surface of the mixed layer 40 (that is, the surface away from the TCO layer 30) is undulating. With the help of such a mixed layer 40, it is more conducive to increasing the contact area between it and the copper seed layer 50 formed thereon, thereby improving the bonding force between them and reducing the contact resistance of the two, thereby improving the pulling force between the subsequently formed copper grid line electrode and the TCO layer 30. In addition, the presence of such a mixed layer 40 can reduce the potential barrier between the TCO layer 30 and the copper seed layer 50, thereby reducing the contact resistance between the TCO layer 30 and the copper seed layer 50. In some other embodiments of the present application, the thickness of the TCO distribution area can also be equal to the thickness of the metal material distribution area.

[0035] Among them, a transmission electron microscope (TEM) is used to take pictures, and the grain size of the metal material can be measured from the cross section of the mixed layer 40. The TCO distribution area 41 of the mixed layer 40 has an interlayer interface with the underlying TCO layer 30. From the cross-sectional TEM picture of the mixed layer 40, the distance between the bottom (the surface in contact with the TCO layer 30) and the top of the TCO distribution area 41 can be measured, thereby obtaining the thickness of the TCO distribution area 41.

[0036] In some embodiments of the present application, in the metal material distribution area 42, the grain size (specifically the grain diameter) of the metal material is greater than 40nm, for example, it can be in the range of greater than 40nm to less than or equal to 100nm, specifically 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 90nm, or 95nm. The thickness of each TCO distribution area 41 is less than 40nm, for example, in the range of greater than or equal to 20nm to less than 40nm, specifically 20nm, 22nm, 25nm, 30nm, 35nm or 38nm. Among them, the larger grain size of the metal material formed by sputtering can be achieved by controlling the sputtering power or sputtering current of the metal material target in a higher range. Exemplarily, the sputtering power of the metal material target can be in the range of 6-10kW. In addition, controlling the sputtering time and power of the metal target and the TCO target can adjust the thickness of the metal material and TCO in the mixed layer and the composition ratio of the metal material and TCO in the mixed layer.

[0037] In some other embodiments of the present application, the mixed layer 40 can be deposited by sputtering using a mixed target containing a metal material and TCO. In this case, the mixed layer 40 formed can also contain TCO and metal material. The composition of the mixed layer 40 can be adjusted by adjusting the composition of the metal material and TCO in the mixed target.

[0038] Step S03, depositing a copper seed layer 50 on the mixed layer 40 to cover the mixed layer 40, such as Figure 3 shown.

[0039] The presence of the copper seed layer 50 can facilitate the formation of electroplated copper during subsequent electroplating, and it can also serve as a transitional bonding layer between the mixed layer 40 and the copper grid electrode 60 formed by subsequent electroplating. The copper seed layer 50 can be formed by PVD. As described above in the present application, the specific PVD method may include but is not limited to sputtering, evaporation plating, ion plating, or RPD. In the embodiment of the present application, the thickness of the copper seed layer 50 is 250nm-450nm, for example, specifically 300nm, 350nm, 400nm, 420nm, etc. In one embodiment of the present application, a sputtering method is used to form a copper seed layer 50, specifically including: the pressure in the sputtering chamber where the substrate to be plated is placed is 0.1-0.5 Pa, the argon gas flow rate is 100-300 sccm, the rotation speed of the sample tray containing the substrate to be plated is 0.2-0.6 m / min, the sputtering power of the copper target is 2-6 kW, and the copper target is sputtered at a temperature of 100-200° C. for a period of time to form a copper seed layer 50 on the substrate to be plated.

[0040] Step S04 , forming a copper gate electrode 60 in a partial area on the copper seed layer 50 .

[0041] In some implementations of the present application, step S04 may specifically include the following step S041, step S042 and step S043.

[0042] Step S041, as Figure 4 As shown, a photoresist pattern layer 80 is formed on the copper seed layer 50 to define the position of the electrode pattern.

[0043] Figure 4 In the figure, the photoresist pattern layer 80 does not completely cover the surface of the copper seed layer 50 away from the silicon substrate 10, and the gaps (indicated by the arrows) of the photoresist material of the photoresist pattern layer 80 correspond to the positions of the electrode patterns to be formed.

[0044] In some embodiments of the present application, “forming a photoresist pattern layer 80 on the copper seed layer 50 ” specifically includes: 1) coating the copper seed layer 50 to form a photoresist material layer covering the copper seed layer 50 ; 2) exposing and developing the photoresist material layer to form a photoresist pattern layer 80 .

[0045] The thickness of the photoresist material layer may be 10-20 μm, for example, 10-12 μm, or 12-15 μm, etc. The exposure may be performed through a mask having a desired pattern, or directly exposed. In some embodiments of the present application, the exposure is laser direct writing (Laser Direct Imaging, LDI), which can directly write a preset electrode pattern on the photoresist material layer. The photoresist material directly written by the laser can undergo a certain degree of denaturation, and its solubility in the subsequent developer solution differs from that of the material not directly written by the laser. For example, the photoresist material directly written by the laser can be dissolved by the developer, and the copper seed layer underneath it is exposed; while the unexposed photoresist material will not be dissolved by the developer and will remain, thereby forming a structure such as the following on the copper seed layer 50. Figure 4 The photoresist pattern layer 80 is shown in FIG. In some embodiments of the present application, the developer used for development is an alkaline aqueous solution, such as an aqueous solution containing at least one of sodium carbonate, potassium carbonate, sodium hydroxide, potassium hydroxide, tetramethylammonium hydroxide (TMAH), and the like.

[0046] Step S042, forming a copper gate electrode 60 on the copper seed layer 50 not covered by the photoresist pattern layer 80 by electroplating process, such as Figure 5 shown.

[0047] Wherein, forming the copper grid line electrode 60 by the electroplating process may include: first electroplating to form a copper grid line layer 61, and then electroplating to form a copper grid line protection layer 62 on the copper grid line layer 61. The copper grid line electrode 60 obtained in this way includes a copper grid line layer 61 and a copper grid line protection layer 62 which are stacked. The copper grid line protection layer 62 covers the copper grid line layer 61 and is away from the copper seed layer 50. In the subsequent film stripping and etching back stage, the copper grid line protection layer 62 can protect the copper grid line layer 61 from being etched. Generally, the thickness (or "height") of the copper grid line layer 61 is greater than the thickness (or "height") of the copper grid line protection layer 62. Exemplarily, the thickness of the copper grid line layer 61 is 8-10μm, and the thickness of the copper grid line protection layer 62 is 2-3μm. In some embodiments of the present application, the copper grid line protection layer 62 is a tin layer. Tin is also a metal material with good conductivity, and the presence of the tin layer will not reduce the conductive performance of the copper grid line layer 61.

[0048] Step S043, removing the photoresist pattern layer 80 (obtaining Figure 6 structure shown).

[0049] In some embodiments of the present application, the photoresist pattern layer 80 can be removed by using an alkaline solution. For example, the alkaline solution can be at least one of a NaOH solution, a KOH solution, etc. It is understood that the alkaline solution used to remove the photoresist pattern layer 80 should try not to corrode the copper grid electrode 60. In addition, in other embodiments of the present application, the photoresist pattern layer 80 can also be removed by ashing.

[0050] Step S05, removing the copper seed layer 50 and the metal material in the mixed layer 40 that are not covered by the copper grid electrode 60, and obtaining Figure 7 The structure shown.

[0051] In the embodiment of the present application, the metal material in the copper seed layer 50 and the mixed layer 40 can be removed by using an acidic etching solution. The acidic etching solution can include at least one of sulfuric acid, hydrochloric acid, nitric acid, phosphoric acid, acetic acid, etc. In some embodiments of the present application, the acidic etching solution is a dilute sulfuric acid solution with a concentration of 0.01-0.03 mol / L.

[0052] Among them, in step S05, the mixed layer 40 covered by the copper grid electrode 60 hardly changes, and its various parameters can refer to the relevant description of the mixed layer in step S02 of the previous text of this application. In the process of removing the copper seed layer 50 not covered by the copper grid electrode 60, the metal material in the mixed layer 40 not covered by the copper grid electrode 60 is removed, and the TCO material is retained, and it is transformed into a light-trapping structure layer 70 with a pit structure on the surface (specifically, the surface of the light-trapping structure layer 70 facing away from the TCO layer 30 has a pit structure). That is, the light-trapping structure layer 70 is the same material as the mixed layer 40, after removing the metal material therein. It can be understood that the light-trapping structure layer 70 contains the same TCO material as that in the mixed layer 40.

[0053] In the implementation mode of this application, Figure 7 , the thickness of the light trapping structure layer 70 is less than the thickness of the retained mixed layer 40. Here, the thickness of the mixed layer 40 refers to the thickness of the area with the largest thickness, and is precisely the thickness of the metal material distribution area (the aforementioned label 42). In some embodiments of the present application, the thickness of the light trapping structure layer 70 is less than 40nm, and can further be in the range of greater than or equal to 20nm to less than 40nm, for example, specifically 20nm, 22nm, 25nm, 30nm, 35nm or 38nm. The thickness of the light trapping structure layer 70 refers to the distance between its top and the top of the TCO layer 30. The thickness of the light trapping structure layer 70 can be known from the TEM photograph of the cross section of the light trapping structure layer 70 perpendicular to the TCO layer 30.

[0054] In the embodiment of the present application, in the light trapping structure layer 70, the depth D and the opening width W of the pit structure are both below 100 nm, that is, the pit is at the nanometer level. The size of the pit structure is relatively small, at the nanometer level, which is conducive to having a large number of pits on the surface of the light trapping structure layer, thereby further helping to reduce the light reflectivity. In the present application, the opening width W of the pit specifically refers to the maximum opening width of the pit, which refers to the distance between the two farthest points on the maximum cross section (parallel to the TCO layer 30) at the opening end of the pit (e.g. Figure 7 The depth D of the pit structure refers to the vertical distance from the opening end of the pit to the lowest point of the pit (e.g. Figure 7 ). The opening width W of the pit can be obtained from a transmission electron microscope photograph of the surface of the light trapping structure layer 70 with the pit. The depth D of the pit can be obtained from a transmission electron microscope photograph of a cross section (perpendicular to the TCO layer 30) of the light trapping structure layer 70.

[0055] In some embodiments of the present application, the depth D of the pit structure is less than the opening width W of the pit structure. This helps to ensure that the light-trapping structure layer 70 can achieve a better light-trapping effect and reduce the reflectivity of light. Because the pit structure is obtained by removing the metal material from the mixed layer 40 that is not covered by the copper grid electrode 60, when the mixed layer 40 includes the TCO distribution area 41 and the metal material distribution area 42 that are distributed alternately, the depth of the pit in the light-trapping structure layer 70 is substantially consistent with the thickness of the TCO distribution area 41 in the aforementioned mixed layer, and the opening width of the pit is substantially consistent with the width of the metal material distribution area 42 in the aforementioned mixed layer. The opening width of the pit can be equal to the grain size of one or more metal materials.

[0056] In some embodiments, the depth of each pit structure may be less than 40 nm, and may further be in the range of greater than or equal to 20 nm to less than 40 nm, for example, specifically 20 nm, 22 nm, 25 nm, 30 nm, 35 nm or 38 nm, etc. In some embodiments, the opening width of each pit structure may be in the range of greater than 40 nm and less than or equal to 100 nm.

[0057] In some embodiments of the present application, the plurality of pits of the light trapping structure layer 70 are distributed discontinuously. The surface of the light trapping structure layer 70 away from the TCO layer is non-planar, having protruding TCO materials and pits between the TCO materials. The pits are sunken toward the TCO layer 30.

[0058] In some embodiments of the present application, after the above-mentioned step S05, step S06 is also included. Step S06: Perform light injection on the solar cell obtained after the step S05. During the manufacturing process of heterojunction solar cells, the boron or phosphorus atoms inside the battery may be in an inactive state due to various reasons, that is, these doped atoms do not correctly participate in the formation of the PN junction. When strong light is irradiated (light injection), these weakly bound H atoms obtain enough energy to diffuse or jump in the lattice, thereby reactivating the B (boron) or P (phosphorus) atoms and restoring their doping effect in the solar cell. Light injection can improve the photoelectric conversion efficiency of heterojunction solar cells. Through light injection, the activation of doped atoms in the battery material can be promoted, defects can be reduced, and the overall performance of the battery can be improved. It can be understood that light injection generally does not produce a new structure, but only partially increases the effective doping concentration of the doped atoms in the original doping layer.

[0059] The present application also provides a solar cell. Figure 7As shown, the solar cell 100 includes a silicon substrate 10, and semiconductor structure layers (respectively represented by code numbers 20 and 20') and a TCO layer 30 stacked in sequence on opposite sides of the silicon substrate 10, wherein copper seed layers 50 are spaced apart on each TCO layer 30, and a copper grid electrode 60 is provided on the surface of the copper seed layer 50 facing away from the TCO layer; wherein a mixed layer 40 is further provided between the copper seed layer 50 and the TCO layer 30 opposite thereto, and a light trapping structure layer 70 having a pit structure on the surface is further provided on the area of ​​the TCO layer 30 not covered by the mixed layer 40, wherein the mixed layer 40 includes a metal material and a transparent conductive oxide (TCO), and the light trapping structure layer 70 contains the same TCO material as the mixed layer 40.

[0060] It can be understood that the copper seed layer 50, the copper grid electrode 60, and the mixed layer 40 do not completely cover the surface of the TCO layer 30 away from the silicon substrate 10. The mixed layer 40 is arranged at intervals on the TCO layer 30, and the copper seed layer 50 and the copper grid electrode 60 are stacked in sequence on the surface of the mixed layer 40 away from the TCO layer 30. In other words, the TCO layer 30 is provided with a stacked structure in which the mixed layer 40, the copper seed layer 50, and the copper grid electrode 60 are stacked in sequence at intervals, wherein the mixed layer 40 is close to the TCO layer 30, and the copper seed layer 50 is located between the mixed layer 40 and the copper grid electrode 60. The shapes of the mixed layer 40 and the copper seed layer 50 are basically the same as those of the copper grid electrode 60. A light trapping structure layer 70 is arranged on the area of ​​the TCO layer 30 that is not covered by the stacked structure. Specifically, a light trapping structure layer 70 is arranged on the area of ​​the TCO layer 30 that is not covered by the mixed layer 40. The mixed layer 40 and the light trapping structure layer 70 are arranged crosswise in the same layer, and their bottom surfaces (the surfaces in contact with the TCO layer 30 ) are generally coplanar.

[0061] The light trapping structure layer 70 can be obtained by etching the metal material of the same material as the mixed layer 40. In the present application, the material of the light trapping structure layer 70 is only TCO, and the difference between it and the TCO layer 30 located below it is that the surface of the light trapping structure layer 70 away from the silicon substrate 10 is not a plane, but has a pit structure, while the surface of the TCO layer 30 away from the silicon substrate 10 is usually flat and has no pit structure. Among them, the specific structural characteristics of the light trapping structure layer 70 and other layers can be found in the previous description of this application. No further details will be given here.

[0062] In the solar cell 100 of the present application, by adding the above-mentioned mixed layer 40 containing TCO and metal material between the copper seed layer 50 and the TCO layer 30 opposite thereto, the mixed layer 40 can be used to realize a smooth transition of the composition from the TCO layer 30 to the copper seed layer 50, which is conducive to improving the bonding force between them and reducing the difference in thermal expansion coefficients, so that the copper grid electrode 60 formed on the copper seed layer 50 is not easy to peel off; in addition, the contact resistance between the TCO layer 30 and the copper seed layer 50 can also be reduced by means of the mixed layer 40, and the contact resistance between the copper grid electrode 60 and the TCO layer can also be reduced accordingly, which is conducive to reducing electrical loss, and is conducive to the overall solar cell 100 having a stable structure and a higher photoelectric conversion efficiency. The TCO layer 30 not covered by the copper grid electrode 60 is provided with a light trapping structure layer 70 with a pit structure, and the bonding force between the light trapping structure layer 70 and the TCO layer 30 is also high, and the light trapping structure layer 70 can reduce the reflectivity of the light incident on the solar cell, reduce light loss, improve the utilization rate of light, and is also conducive to improving the photoelectric conversion efficiency of the solar cell 100. The solar cell 100 can be applied to various photovoltaic power stations, solar cars and other fields.

[0063] In the embodiment of the present application, in the solar cell 100, the bonding force between the copper grid electrode 60 and the TCO layer 30 is greater than 1.0 N. Since the mixed layer 40 is present between the copper seed layer 50 and the TCO layer 30, the bonding force between the copper grid electrode 60 on the copper seed layer 50 and the TCO layer is also improved to a certain extent and can be greater than 1.0 N. When there is no mixed layer 40 between the copper seed layer 50 and the TCO layer 30, the bonding force between the copper grid electrode 60 and the TCO layer 30 is only about 0.7 N.

[0064] In the embodiment of the present application, the average reflectivity of the solar cell 100 to incident light with a wavelength in the range of 400nm-1000nm is below 3.5%, and can further be below 3.45%. Figure 7 The average reflectivity of the solar cell 100 for incident light of 400nm-1000nm is compared with that without Figure 7 The reduction percentage of the existing solar cell with the mixed layer 40 and the light trapping structure layer 70 is above 4%, for example, it is specifically reduced by 4.2%, 5.0%, 5.9%, 8.7%, 10%, 13.7%, etc. This shows that after the solar cell provided by the present application introduces the above-mentioned mixed layer 40 and the light trapping structure layer 70, the light reflectivity can be effectively reduced, thereby facilitating the improvement of the photoelectric conversion efficiency of the solar cell.

[0065] In the implementation mode of this application, Figure 7 The photoelectric conversion efficiency of the solar cell 100 shown may be above 24.80%.

[0066] The embodiment of the present application further provides a photovoltaic assembly, which includes the solar cell of the embodiment of the present application. In addition, the photovoltaic assembly may also include a protective component for protecting the solar cell.

[0067] Since the photovoltaic module is provided with the solar cell with stable structure and high photoelectric conversion efficiency provided by the present application, the photovoltaic module has good market competitiveness.

[0068] The technical solution of the present application is further described below in conjunction with a number of specific embodiments.

[0069] Example 1

[0070] A method for preparing a solar cell comprises the following steps:

[0071] (1) Preparing a silicon substrate with a semiconductor structure layer: After cleaning an M6 specification N-type single crystal silicon wafer (length 166 mm, width 166 mm, thickness 150 μm), a textured surface is formed to form an inverted pyramid-shaped textured surface; then, a plasma enhanced chemical vapor deposition (PECVD) technique is used to sequentially form a first intrinsic silicon layer (can be called an N-side intrinsic silicon layer) and an N-type phosphorus-doped amorphous silicon layer on one side surface (can be called the front side) of the textured silicon wafer, and a second intrinsic silicon layer (can be called a P-side intrinsic silicon layer) and a P-type boron-doped amorphous silicon layer are sequentially formed on the other side surface (can be called the back side) of the textured silicon wafer.

[0072] (2) Deposition of TCO layer: The silicon wafer with the semiconductor structure layer is placed on a sample tray in the sputtering chamber of a horizontal magnetron sputtering coating machine. A target A (specifically an ITO target material, wherein the mass ratio of In2O3 to SnO2 is 97:3) is placed in the sputtering chamber. The deposition temperature is set to 150°C, the sputtering power of target A is less than 3kW, the argon flow rate into the sputtering chamber is 288sccm, the oxygen flow rate is 12sccm, the pressure in the sputtering chamber is 0.23Pa, and the rotation linear speed of the sample tray is 0.3m / min. Target A is sputtered at 150°C for a period of time to form a TCO layer with a single-sided thickness of 75nm.

[0073] (3) Deposition of mixed layer: The silicon wafer with TCO layer formed on both sides is placed on a sample tray in the sputtering chamber of a horizontal magnetron sputtering coating machine, wherein the aforementioned target A and target B (specifically, a copper target with a purity of 99.99%) are placed in the sputtering chamber, and the deposition temperature is set to 150°C. First, the target B is sputtered to form a discontinuously distributed copper film on the TCO layer, wherein the power of the target B is 8 kW, the argon flow rate is 300 sccm, the pressure in the sputtering chamber is 0.23 Pa, and the rotation linear speed of the sample tray is 6.4 m / min; then the target A is sputtered to form an ITO material filling the gaps in the copper film, wherein the power of the target A is 3 kW, the argon flow rate is 300 sccm, the pressure in the sputtering chamber is 0.23 Pa, and the rotation linear speed of the sample tray is 2 m / min. Among them, the thickness of the copper film is 75nm, the particle size of the copper grains in the copper film is 75nm, and the thickness of the ITO material is 36nm; in the mixed layer, the mass proportion of copper is 57%, and the mass proportion of the ITO material is 43%.

[0074] (4) Deposition of copper seed layer: The silicon wafer with the mixed layer formed on both sides is placed on a sample tray in the sputtering chamber of a horizontal magnetron sputtering coating machine. The deposition temperature is set to 150°C, the power of target B is 6kW, the argon flow rate is 300sccm, the pressure in the sputtering chamber is 0.23Pa, and the rotation linear speed of the sample tray is 1.5m / min. Target B is sputtered at 150°C for a period of time to form a copper seed layer with a thickness of 350nm.

[0075] (5) Forming a photoresist pattern layer: First, a photoresist is coated on the surface of the front copper seed layer and the back copper seed layer of the silicon wafer, and a photoresist material layer with a thickness of 10-12 μm is formed after removing the solvent; a preset gate line pattern is directly written by laser on the photoresist material layer, so that the portion of the photoresist material subjected to the laser direct writing is denatured; then, a developer is used to dissolve the photoresist material subjected to the laser direct writing, and a photoresist pattern layer is formed on the copper seed layer, so that the copper seed layer in the preset pattern area is exposed.

[0076] (6) Electroplating of copper gate electrodes: First, copper is electroplated on the exposed copper seed layer using a copper plating solution to form a copper gate layer, and then a tin-containing plating solution is used to electroplate a tin layer as a copper gate protective layer; wherein the height of the copper gate layer is about 8-10 μm, and the height of the tin layer is 2-3 μm.

[0077] (7) De-filming and etching: First, use a NaOH solution to remove the above-mentioned photoresist pattern layer, and then use a dilute sulfuric acid solution to remove the copper seed layer in the non-gate line area, and remove the copper in the mixed layer in the non-gate line area, leaving only the TCO material, so as to form a light-trapping structure layer with a pit structure on the surface of the TCO layer in the non-gate line area.

[0078] (8) Light injection: Light is injected into the cell after the film removal and re-engraving.

[0079] Example 2

[0080] The difference between Example 2 and Example 1 is that the process parameters for forming the mixed layer are different. In Example 2, when sputtering to form the ITO material filling the gaps in the copper film, the power of target A is 2kW. In the mixed layer of Example 2, the thickness of the copper film is 75nm, the diameter of the copper grains is 75nm, the mass proportion of copper is 59%, the mass proportion of the ITO material is 41%, and the thickness of the ITO material is 24nm.

[0081] Example 3

[0082] The difference between Example 3 and Example 1 is that the process parameters for forming the mixed layer are different. In Example 3, when the discontinuously distributed copper film is formed by sputtering, the power of the B target is 10 kW. In the mixed layer of Example 3, the thickness of the copper film is 96 nm, the copper grain size is 96 nm, the mass proportion of copper in the mixed layer is 65%, the mass proportion of the ITO material is 35%, and the thickness of the ITO material is 36 nm.

[0083] Example 4

[0084] The difference between Example 4 and Example 1 is that the process parameters for forming the mixed layer are different. In Example 4, when the discontinuously distributed copper film is formed by sputtering, the power of the B target is 6 kW. In the mixed layer of Example 4, the thickness of the copper film is 47 nm, the diameter of the copper grains is 47 nm, the mass proportion of copper in the mixed layer is 48%, the mass proportion of the ITO material is 52%, and the thickness of the ITO material is 36 nm.

[0085] Example 5

[0086] The difference between Example 5 and Example 1 is that the process parameters for forming the mixed layer are different. In Example 5, when sputtering to form a discontinuously distributed copper film, the power of target B is 6 kW; when sputtering to form an ITO material filling the gaps in the copper film, the power of target A is 2 kW.

[0087] Among them, in the mixed layer of Example 5, the thickness of the copper film is 47nm, the copper grain size is 47nm, the mass proportion of copper in the mixed layer is 53%, the mass proportion of ITO material is 47%, and the thickness of ITO material is 24nm.

[0088] Example 6

[0089] The difference between Example 6 and Example 1 is that the process parameters for forming the mixed layer are different. In Example 6, when sputtering to form a discontinuously distributed copper film, the power of target B is 10 kW; when sputtering to form an ITO material filling the gaps in the copper film, the power of target A is 2 kW.

[0090] Among them, in the mixed layer of Example 6, the thickness of the copper film is 96nm, the particle size of the copper grains is 96nm, the mass proportion of copper in the mixed layer is 68%, the mass proportion of the ITO material is 32%, and the thickness of the ITO material is 24nm.

[0091] In order to highlight the beneficial effects of the technical solution of the present application, the following comparative example 1 is set.

[0092] Comparative Example 1

[0093] The difference between Comparative Example 1 and the above-mentioned Embodiment 1 is that: no mixed layer is formed on the TCO layer; accordingly, in the etching back process after removing the photoresist pattern layer, only the copper seed layer in the non-gate line area is removed.

[0094] In order to strongly support the beneficial effects of the embodiments of the present application, the average reflectivity of the light-receiving surface of the solar cell of each embodiment and comparative example 1 to the incident light in the wavelength range of 400nm-1000nm was tested by a spectrophotometer from Agilent Technology, and the pull-out force between the copper grid electrode and the TCO layer was measured by an electronic universal testing machine (Suzhou Yuhong Optoelectronic Instrument Co., Ltd.). The results are shown in Table 1 below. In addition, the photoelectric conversion efficiency of each solar cell was also tested. Specifically, the current-voltage (IV) curve of each solar cell was measured by the steady-state light source method under standard test conditions (STC), and the photoelectric conversion efficiency (η) of the solar cell was obtained from the obtained IV curve. The relevant results are summarized in Table 1 below.

[0095] Table 1

[0096] Average reflectivity (%) Pull-out force(N) Photoelectric conversion efficiency (%) Example 1 3.09 1.2 25.07 Example 2 3.26 1.1 24.96 Example 3 3.21 1.3 24.99 Example 4 3.42 1.0 24.81 Example 5 3.36 1.0 24.87 Example 6 3.39 1.2 24.83 Comparative Example 1 3.57 0.7 24.72

[0097] It can be seen from Table 1 that, compared with the cell of Comparative Example 1 in which no mixed layer is formed between the TCO layer and the copper seed layer, the silicon heterojunction solar cell produced in the embodiment of the present application has a higher bonding strength between the copper grid electrode and the TCO layer, and the pull-out force is increased by 0.3N-0.6N; the average reflectivity of the incident light of 400-1000nm is reduced by more than 4.0%, and the photoelectric conversion efficiency is increased by about 0.36%-1.41%.

[0098] The above is an exemplary embodiment of the present application, and its description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to it, and these improvements and modifications also belong to the protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, and a semiconductor structure layer and a transparent conductive oxide layer stacked in sequence on opposite sides of the silicon substrate, wherein a copper seed layer is spaced apart on the transparent conductive oxide layer, and a copper grid electrode is provided on the surface of the copper seed layer facing away from the transparent conductive oxide layer; wherein a mixed layer is further provided between the copper seed layer and the transparent conductive oxide layer opposite thereto, and a light-trapping structure layer having a surface with a pit structure is further provided on the area of ​​the transparent conductive oxide layer not covered by the mixed layer, wherein the mixed layer comprises a metal material and a transparent conductive oxide, and the light-trapping structure layer contains the same transparent conductive oxide as the mixed layer.

2. The solar cell according to claim 1, wherein: In the mixed layer, the metal material accounts for 40%-70% by mass, and the transparent conductive oxide accounts for 30%-60% by mass.

3. The solar cell according to claim 1 or 2, characterized in that: Along a thickness direction perpendicular to the mixed layer, the mixed layer includes metal material distribution areas and transparent conductive oxide distribution areas that are distributed at intervals.

4. The solar cell according to claim 3, characterized in that The depth of the pit structure is smaller than the opening width of the pit structure.

5. The solar cell according to claim 4, characterized in that The depth of the pit structure is less than 40 nm.

6. The solar cell according to claim 4, characterized in that The opening width of the pit structure is greater than 40 nm and less than or equal to 100 nm.

7. The solar cell according to any one of claims 1 to 6, characterized in that: In the mixed layer, the metal material is copper.

8. The solar cell according to any one of claims 1 to 7, characterized in that: The thickness of the light trapping structure layer is smaller than the thickness of the mixed layer.

9. The solar cell according to any one of claims 1 to 8, characterized in that: The transparent conductive oxides in the mixed layer and the light trapping structure layer are selected from one or more of indium tin oxide, aluminum-doped zinc oxide, cerium-doped indium oxide, tungsten-doped indium oxide, phosphorus-doped tin dioxide, and fluorine-doped tin dioxide; the transparent conductive oxide layer is selected from one or more of indium tin oxide, aluminum-doped zinc oxide, cerium-doped indium oxide, tungsten-doped indium oxide, phosphorus-doped tin dioxide, and fluorine-doped tin dioxide.

10. The solar cell according to any one of claims 1 to 9, characterized in that: The copper seed layer has a thickness of 250 nm-450 nm; and / or the transparent conductive oxide layer has a thickness of 60 nm-100 nm.

11. The solar cell according to any one of claims 1 to 10, characterized in that: Each of the semiconductor structure layers independently includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked in sequence, wherein the doped amorphous silicon layer is close to the transparent conductive oxide layer; of the two doped amorphous silicon layers, one is a P-type amorphous silicon layer and the other is an N-type amorphous silicon layer.

12. The solar cell according to any one of claims 1 to 11, characterized in that: The average reflectivity of the solar cell to incident light within the wavelength range of 400nm-1000nm is below 3.5%; and / or, the average reflectivity of the solar cell to incident light within the wavelength range of 400nm-1000nm is reduced by more than 4% compared with a conventional solar cell not containing the mixed layer and the light trapping structure layer.

13. A method for preparing a solar cell, characterized in that: The following steps are involved: Providing a silicon substrate with a semiconductor structure layer and a transparent conductive oxide layer formed on two opposite surfaces; forming a mixed layer of a metal-containing material and a transparent conductive oxide on the transparent conductive oxide layer; forming a copper seed layer on the mixed layer and covering the mixed layer; forming a copper gate electrode in a partial area on the copper seed layer; The copper seed layer not covered by the copper gate electrode and the metal material in the mixed layer are removed.

14. The preparation method according to claim 13, characterized in that: In the mixed layer, the metal copper accounts for 40%-70% by mass, and the transparent conductive oxide accounts for 30%-60% by mass.

15. The preparation method according to claim 13 or 14, characterized in that: Forming the mixed layer comprises: First, sputtering a discontinuously distributed metal material is formed on the transparent conductive oxide layer; Then, a plurality of transparent conductive oxide distribution regions are formed by sputtering to fill the gaps between the metal materials.

16. The preparation method according to claim 15, characterized in that: The thickness of the transparent conductive oxide distribution area is smaller than the grain size of the metal material.

17. The preparation method according to claim 16, characterized in that: The thickness of the transparent conductive oxide distribution area in the mixed layer is less than 40 nm; the grain size of the metal material is greater than 40 nm and less than or equal to 100 nm.

18. The preparation method according to any one of claims 13 to 17, characterized in that: The copper seed layer and the metal material in the mixed layer are removed, specifically by using an acidic etching solution.

19. The preparation method according to any one of claims 13 to 18, characterized in that: The forming of a copper gate electrode in a partial area on the copper seed layer comprises: forming a photoresist pattern layer on the copper seed layer to define the position of the electrode pattern; On the copper seed layer not covered by the photoresist pattern layer, forming a copper gate line electrode by an electroplating process; The photoresist pattern layer is removed.

20. A photovoltaic module, characterized in that: The invention comprises a solar cell as claimed in any one of claims 1 to 12, or a solar cell prepared by the preparation method as claimed in any one of claims 13 to 19.

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