Light emitting diode chip and preparation method thereof

Abstract

The invention relates to the field of semiconductor photoelectric devices, and particularly discloses a light-emitting diode chip and a preparation method thereof. The light emitting diode chip includes a substrate; the epitaxial layer is arranged on the substrate, and the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked on the substrate; an exposed region for exposing the first semiconductor layer is formed on the epitaxial layer; a first transparent conductive layer laminated on the second semiconductor layer; a second transparent conductive layer laminated on the first transparent conductive layer; the first electrode is arranged on the first semiconductor layer in the exposed area and is electrically connected with the first semiconductor layer; the second electrode is arranged on the second transparent conductive layer and is electrically connected with the second semiconductor layer; wherein the light transmittance of the first transparent conductive layer is smaller than that of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is smaller than that of the second transparent conductive layer. By implementing the invention, the luminous efficiency of the light-emitting diode chip can be improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor optoelectronic devices, and in particular to a light emitting diode chip and a preparation method thereof. Background Art

[0002] Most of the existing light-emitting diodes are GaN-based epitaxial structures, that is, their P-type layer is a P-type GaN layer, and its work function is as high as 7.5eV, which is greater than the metal used to prepare the electrodes of light-emitting diodes. This results in a higher contact resistance between the P-type layer and the electrode, which increases the operating voltage. High voltage will lead to increased heat generation, reduced light efficiency, and reduced reliability. One of the commonly used methods is to form a transparent conductive film on the P-type layer to reduce the ohmic contact resistance, improve the lateral expansion capability of the current, and avoid current concentration. The commonly used transparent conductive layer is a tin-doped indium oxide layer (In2O3: Sn). When its doping concentration is high, the square resistance is low, which is conducive to optimizing the ohmic contact between the P-type layer and the metal electrode, but the transmittance will drop significantly, reducing the light efficiency. When its doping concentration is high, although the transmittance is high, the square resistance is large, resulting in a high operating voltage and poor reliability of the light-emitting diode. In addition, the voltage increase will also lead to a decrease in light efficiency. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a light emitting diode chip and a preparation method thereof, which can improve the light efficiency of the light emitting diode chip and reduce its operating voltage.

[0004] In order to solve the above technical problems, the present invention provides a light emitting diode chip, which includes:

[0005] substrate;

[0006] An epitaxial layer, which is disposed on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on the substrate; the epitaxial layer is formed with an exposed area exposing the first semiconductor layer;

[0007] A first transparent conductive layer stacked on the second semiconductor layer;

[0008] a second transparent conductive layer stacked on the first transparent conductive layer;

[0009] A first electrode is disposed on the first semiconductor layer in the exposed region and is electrically connected to the first semiconductor layer; and

[0010] a second electrode, which is disposed on the second transparent conductive layer and electrically connected to the second semiconductor layer;

[0011] The light transmittance of the first transparent conductive layer is smaller than the light transmittance of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is smaller than the sheet resistance of the second transparent conductive layer.

[0012] As an improvement of the above technical solution, the light transmittance of the first transparent conductive layer is 72% to 85%, and the light transmittance of the second transparent conductive layer is 92% to 98%;

[0013] The sheet resistance of the first transparent conductive layer is 4.6Ω / sq to 13.8Ω / sq, and the sheet resistance of the second transparent conductive layer is 18.6Ω / sq to 24.3Ω / sq;

[0014] The first transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or a FTO layer;

[0015] The second transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or a FTO layer.

[0016] As an improvement of the above technical solution, the first transparent conductive layer and the second transparent conductive layer are both ITO layers;

[0017] And the In content in the first transparent conductive layer is greater than or equal to the In content in the second transparent conductive layer.

[0018] As an improvement of the above technical solution, the first transparent conductive layer is an ITO layer, the In content of which is 8wt% to 15wt% and the thickness is

[0019] The second transparent conductive layer is an ITO layer, the In content of which is 2wt% to 5wt% and the thickness is

[0020]

[0021] As an improvement of the above technical solution, a plurality of through holes are arrayed on the first transparent conductive layer to separate the first transparent conductive layer into a plurality of conductive units distributed in an array; the second transparent conductive layer is at least partially in contact with the second semiconductor layer through the through holes;

[0022] The ratio of the cross-sectional area of ​​the first transparent conductive layer to the cross-sectional area of ​​the second transparent conductive layer is 5:100 to 30:100;

[0023] The cross section of the conductive unit is circular, rectangular or triangular, and its width is

[0024] As an improvement of the above technical solution, it also includes a first current blocking layer and a second current blocking layer, wherein the first current blocking layer is arranged between the first electrode and the first semiconductor layer and is covered by the first electrode;

[0025] The second current blocking layer is disposed between the first transparent conductive layer and the second semiconductor layer, and is disposed below the second electrode, and a projection of the second electrode on the surface where the second current blocking layer is located covers the second current blocking layer;

[0026] At least one conductive unit is disposed on the second current blocking layer.

[0027] As an improvement of the above technical solution, a plurality of through holes are arranged in an array on the first conductive layer to separate the first conductive layer into a plurality of conductive units distributed in an array;

[0028] The through hole is filled with a third transparent conductive layer, and the third transparent conductive layer is a periodic structure, and each period includes sequentially stacked Sc2O3 layers and Sc and Sn co-doped In2O3 layers.

[0029] As an improvement of the above technical solution, the thickness of the Sc2O3 layer is 1nm to 2nm;

[0030] The thickness of the Sc and Sn co-doped In2O3 layer is 10nm-15nm, the Sc doping concentration is 5%-10%, and the Sn doping concentration is 15%-20%.

[0031] Correspondingly, the present invention also discloses a method for preparing a light emitting diode chip, which is used to prepare the above-mentioned light emitting diode chip, and comprises:

[0032] forming an epitaxial layer on a substrate; the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on the substrate;

[0033] Etching the epitaxial layer to form an exposed area exposing the first semiconductor layer;

[0034] sequentially forming a first transparent conductive layer and a second transparent conductive layer on the second semiconductor layer;

[0035] forming a second electrode on the second transparent conductive layer, and forming a first electrode on the first semiconductor layer in the exposed area;

[0036] The light transmittance of the first transparent conductive layer is smaller than the light transmittance of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is smaller than the sheet resistance of the second transparent conductive layer.

[0037] As an improvement of the above technical solution, the step of sequentially forming the first transparent conductive layer and the second transparent conductive layer on the second semiconductor layer includes:

[0038] forming a plurality of conductive units on the second semiconductor layer to obtain a first transparent conductive layer; through holes are provided between the plurality of conductive units;

[0039] forming a third transparent conductive layer in the through hole;

[0040] forming a second transparent conductive layer on the first transparent conductive layer and the third transparent conductive layer;

[0041] Anneal in O2 atmosphere at 500℃~600℃ for 10min~20min.

[0042] The implementation of the present invention has the following beneficial effects:

[0043] See also Figure 1 In the light-emitting diode chip of one embodiment of the present invention, a first transparent conductive layer and a second transparent conductive layer are sequentially arranged on the second semiconductor layer, wherein the transmittance of the first transparent conductive layer is less than the transmittance of the second transparent conductive layer, and the square resistance of the first transparent conductive layer is less than the square resistance of the second transparent conductive layer. Based on the light-emitting diode chip of this embodiment, the first transparent conductive layer is in contact with the second semiconductor layer, and its square resistance is small and its lateral current expansion capability is strong, which can improve the current expansion capability and improve the ohmic contact between the electrode and the second semiconductor layer; and the second transparent conductive layer only needs to transfer the current to the second transparent conductive layer, so a material with large square resistance and large transmittance is used, which has little effect on the operating voltage and can improve the light extraction efficiency. Through the cooperation of the two, the luminous efficiency of the light-emitting diode chip can be improved and its operating voltage can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic structural diagram of a light emitting diode chip in one embodiment of the present invention;

[0045] Figure 2 is a schematic structural diagram of a light emitting diode chip in another embodiment of the present invention;

[0046] Figure 3 is a structural schematic diagram of a light emitting diode chip in another embodiment of the present invention;

[0047] Figure 4 Schematic diagram of the structure of the third transparent conductive layer in one embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. It is hereby stated that the directional terms such as up, down, left, right, front, back, inside, outside, etc. that appear or will appear in the text of the present invention are only based on the accompanying drawings of the present invention, and are not specific limitations of the present invention.

[0049] See also Figure 1 In one embodiment of the present invention, a light-emitting diode chip is provided, which includes a substrate 1, an epitaxial layer 2, a first transparent conductive layer 3, a second transparent conductive layer 4, a first electrode 5, and a second electrode 6. The epitaxial layer 2 is provided on the substrate 1, and includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate 1; an exposed area 24 exposing the first semiconductor layer 21 is also formed on the epitaxial layer 2; the first transparent conductive layer 3 is stacked on the second semiconductor layer 23; the second transparent conductive layer 4 is stacked on the first transparent conductive layer 3; the first electrode 5 is provided on the first semiconductor layer 21 in the exposed area 24, and is electrically connected to the first semiconductor layer 21; the second electrode 6 is provided on the second transparent conductive layer 4, and is electrically connected to the second semiconductor layer 23. The transmittance of the first transparent conductive layer 3 is less than the transmittance of the second transparent conductive layer 4, and the square resistance of the first transparent conductive layer 3 is less than the square resistance of the second transparent conductive layer 4. Based on the light-emitting diode chip of this embodiment, the first transparent conductive layer 3 is in contact with the second semiconductor layer 23, and its square resistance is small, and the current lateral expansion capability is strong, which can improve the current expansion capability and improve the ohmic contact between the electrode and the second semiconductor layer 23; and the second transparent conductive layer 4 only needs to transfer the current to the second transparent conductive layer 4, so a material with large square resistance and high light transmittance is used, which has little effect on the working voltage and can improve the light extraction efficiency. Through the cooperation of the two, the luminous efficiency of the light-emitting diode chip can be improved and its working voltage can be reduced.

[0050] Specifically, the substrate 1 may be a sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate or a zinc oxide substrate, but is not limited thereto, preferably a sapphire substrate, and more preferably a patterned sapphire substrate.

[0051] Specifically, different types of epitaxial layers 2 can be selected according to the different light-emitting wavelengths of the light-emitting LED chip. Specifically, the light-emitting diode chip of the present invention can be a red, green, yellow or purple LED chip. Based on the control of the light-emitting wavelength, different types of first semiconductor layers 21, active layers 22, and second semiconductor layers 23 can be selected. Exemplarily, in one embodiment of the present invention, when the light-emitting diode chip is a blue LED chip or a green LED chip, the first semiconductor layer 21 can be an N-type GaN layer, the active layer 22 can be an InGaN-GaN type multi-quantum well layer, and the second semiconductor layer 23 can be a P-type GaN layer. In another embodiment of the present invention, when the light-emitting diode chip is a purple LED chip, the first semiconductor layer 21 can be an N-type AlGaN layer, the active layer 22 can be an AlGaN-AlGaN type multi-quantum well layer, and the second semiconductor layer 23 can be a P-type AlGaN layer, but it is not limited thereto. Preferably, in this embodiment, the first semiconductor layer 21 is an N-type GaN layer, the active layer 22 is an InGaN-GaN type multi-quantum well layer, and the second semiconductor layer 23 may be a P-type GaN layer.

[0052] Specifically, the first transparent conductive layer 3 is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer, but is not limited thereto. Preferably, it is an ITO layer. The second transparent conductive layer 4 is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer. Preferably, it is an ITO layer. It should be noted that the materials of the first transparent conductive layer 3 and the second transparent conductive layer 4 can be the same or different. When the materials of the two are the same and both are ITO layers (i.e., Sn-doped In2O3 layers), the In content in the first transparent conductive layer 3 is greater than or equal to the In content in the second transparent conductive layer 4. By controlling the In content, the first transparent conductive layer 3 can have a lower square resistance and a lower transmittance, while the second transparent conductive layer 4 has a higher square resistance and a higher transmittance, thereby achieving the effect of reducing the operating voltage and improving the luminous efficiency at the same time. More specifically, the In content in the first transparent conductive layer 3 is 8wt% to 15wt%, and the In content in the second transparent conductive layer 4 is 2wt% to 5wt%.

[0053] Specifically, in one embodiment, the transmittance of the first transparent conductive layer 3 is 72% to 85%, and its square resistance is 4.6Ω / sq to 13.8Ω / sq. The transmittance of the first transparent conductive layer 3 is 92% to 98%, and its square resistance is 18.6Ω / sq to 24.3Ω / sq. Based on the control of the above transmittance and square resistance, the first transparent conductive layer 3 and the second transparent conductive layer 4 can be well matched, and the effect of reducing the operating voltage and improving the luminous efficiency can be achieved at the same time.

[0054] Specifically, in one embodiment, the thickness of the first transparent conductive layer 3 is The thickness of the second transparent conductive layer 4 is

[0055] Specifically, the first electrode 5 and the second electrode 6 are both metal single-layer or stacked-layer structures commonly seen in the art, for example, they may be made of one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag.

[0056] Preferably, see Figure 2 In one embodiment of the present invention, a plurality of through holes 31 are arrayed on the first conductive layer to separate the first transparent conductive layer 3 into a plurality of conductive units 32 distributed in an array; based on this implementation, while improving the uniformity of current distribution, the light extraction efficiency can also be improved, thereby further improving the luminous efficiency.

[0057] Specifically, in this embodiment, the ratio of the sum of the cross-sectional areas of the conductive units 32 (i.e., the cross-sectional area of ​​the first transparent conductive layer 3) to the cross-sectional area of ​​the second transparent conductive layer 4 is 5:100 to 30:100; if the area of ​​the first transparent conductive layer 3 is too small, it will affect the ohmic contact between the second electrode 6 and the second semiconductor layer 23.

[0058] Specifically, the cross-sectional shape of the conductive unit 32 may be circular, rectangular or triangular, but is not limited thereto. The width of the conductive unit 32 is Here, the width refers to the characteristic size of the conductive unit 32. For example, when the cross-section of the conductive unit 32 is circular, the width is its diameter; when the cross-section of the conductive unit 32 is rectangular, the width is its long side size; when the cross-section of the conductive unit 32 is triangular, the width is its longest side length.

[0059] Preferably, see Figure 2 In one embodiment, the light-emitting diode chip further includes a first current blocking layer 7 and a second current blocking layer 8. The first current blocking layer 7 is disposed between the first electrode 5 and the first semiconductor layer 21 and is covered by the first electrode 5. The second current blocking layer 8 is disposed between the first transparent conductive layer 3 and the second semiconductor layer 23 and is disposed below the second electrode 6. The projection of the second electrode 6 on the surface where the second current blocking layer 8 is located covers the second current blocking layer 8. At least one conductive unit 32 is disposed on the second current blocking layer 8. The first current blocking layer 7 and the second current blocking layer 8 can improve the uniformity of current distribution and improve the luminous efficiency.

[0060] Preferably, see Figure 3 and Figure 4In another embodiment of the present invention, the through hole 31 between the conductive units 32 is filled with a third transparent conductive layer 9, and the third transparent conductive layer 9 is a periodic structure, and each period includes a Sc2O3 layer 91 and a Sc, Sn co-doped In2O3 layer 92 stacked in sequence. Specifically, the third transparent conductive layer 9 can further improve the light transmittance, reduce the contact resistance between the electrode and the epitaxial layer 2, and reduce the operating voltage of the LED chip. Through the cooperation of the first transparent conductive layer 3, the second transparent conductive layer 4, and the third transparent conductive layer 9 of the structure, one can greatly improve the luminous efficiency and reduce the operating voltage; second, the current blocking layer in the traditional light-emitting diode chip can be eliminated, saving the process. Third, due to the difference in refractive index between the first transparent conductive layer 3 and the third transparent conductive layer 9, the light will change the exit angle when passing through the structure composed of the first transparent conductive layer 3 and the third transparent conductive layer 9, preventing the light from entering the etched side wall (i.e., the side wall of the exposed area 24), improving the light extraction efficiency, especially for Micro-LED, which can greatly improve the luminous efficiency.

[0061] Specifically, the number of periods of the third transparent conductive layer 9 is 3 to 20, the thickness of the Sc2O3 layer 91 is 1 nm to 2 nm, the thickness of the Sc and Sn co-doped In2O3 layer 92 is 10 nm to 15 nm, the Sc doping concentration is 5% to 10%, and the Sn doping concentration is 15% to 20%. The Sn doping concentration refers to the ratio of the number of Sc atoms to the total number of Sc, Sn, and In atoms.

[0062] It should be noted that the light emitting diode chip in the present invention may also include structures such as a passivation layer commonly used in the art, but is not limited thereto.

[0063] Correspondingly, the present invention also discloses a method for preparing a light emitting diode chip, which is used to prepare the above-mentioned light emitting diode chip, and comprises the following steps:

[0064] (1) forming an epitaxial layer 2 on a substrate 1;

[0065] Specifically, the epitaxial layer 2 may be formed on the substrate 1 by MOCVD, but is not limited thereto.

[0066] (2) etching the epitaxial layer 2 to form an exposed area 24 exposing the first semiconductor layer 21;

[0067] Specifically, an ICP or RIE etching device is used to etch the epitaxial layer 2 , and the first exposed area 24 is etched to the first semiconductor layer 21 .

[0068] (3) forming a first transparent conductive layer 3 and a second transparent conductive layer 4 in sequence on the second semiconductor layer 23;

[0069] Specifically, the first transparent conductive layer 3 , the second transparent conductive layer 4 and the third transparent conductive layer 9 may be formed by PVD, electron beam evaporation or other processes, but the present invention is not limited thereto.

[0070] Specifically, in one embodiment, in order to form the first transparent conductive layer 3 composed of a plurality of light-transmitting units, a method of first forming a whole layer and then etching can be adopted, or a method of first forming a specific photoresist pattern and then forming the light-transmitting units according to the pattern can be adopted. Accordingly, when forming the third transparent conductive layer 9, in order to ensure that it is accurately filled in the through hole 31, a process of first forming the whole layer and then etching, or forming the pattern by photolithography can also be adopted. But it is not limited thereto.

[0071] More specifically, in one embodiment, step (3) includes:

[0072] (3.1) forming a plurality of conductive units 32 on the second semiconductor layer 23 to obtain a first transparent conductive layer 3; through holes 31 are provided between the plurality of conductive units 32;

[0073] (3.2) forming a third transparent conductive layer 9 in the through hole 31;

[0074] (3.3) forming a second transparent conductive layer 4 on the first transparent conductive layer 3 and the third transparent conductive layer 9;

[0075] (3.4) Anneal in an O2 atmosphere at 500°C to 600°C for 10 min to 20 min.

[0076] Through annealing, the crystal quality of the first transparent conductive layer 3, the second transparent conductive layer 4, and the third transparent conductive layer 9 can be improved, the light transmittance can be improved, and then the luminous efficiency of the light emitting diode chip can be improved.

[0077] (4) forming a second electrode 6 on the second transparent conductive layer 4, and forming a first electrode 5 on the first semiconductor layer 21 in the exposed area 24;

[0078] Specifically, the first electrode 5 and the second electrode 6 may be formed by an evaporation process, and may be formed simultaneously or in steps, but is not limited thereto.

[0079] The present invention will be further described below with specific embodiments:

[0080] Example 1

[0081] This embodiment provides a light-emitting diode chip, which includes a sapphire substrate, an epitaxial layer (N-GaN layer, InGaN-GaN multi-quantum well layer and P-GaN layer) disposed on the sapphire substrate, and an exposed region of the N-GaN layer is formed by etching on the epitaxial layer. A first electrode is disposed on the N-GaN layer in the exposed region.

[0082] The first transparent conductive layer and the second transparent conductive layer are arranged on the P-GaN layer in sequence. The first transparent conductive layer is a whole layer structure, which is an ITO layer with an In content of 10wt% and a thickness of The second transparent conductive layer is a whole layer structure, which is an ITO layer, and its In content is 5wt% and its thickness is

[0083] A second electrode is also disposed on the second transparent conductive layer.

[0084] The method for preparing the light emitting diode chip in this embodiment is as follows:

[0085] (1) forming an epitaxial layer on a sapphire substrate;

[0086] (2) etching the epitaxial layer to form an exposed area exposing the first semiconductor layer;

[0087] (3) forming a first transparent conductive layer and a second transparent conductive layer in sequence on the second semiconductor layer; after the growth is completed, annealing is performed at 550° C. for 15 minutes.

[0088] (4) forming a second electrode on the second transparent conductive layer, and forming a first electrode on the first semiconductor layer in the exposed area.

[0089] Example 2

[0090] This embodiment provides a light emitting diode chip, which is different from the first embodiment in that:

[0091] The first transparent conductive layer includes a plurality of circular conductive units, the diameter of which is The array is distributed on the P-type GaN layer. Through holes are formed between the plurality of conductive units. The total cross-sectional area of ​​the conductive units is 45% of the cross-sectional area of ​​the second transparent conductive layer.

[0092] Accordingly, in the preparation method, a pattern is first formed by photoresist, then a first transparent conductive layer is deposited, and finally the photoresist is removed.

[0093] The rest are the same as in Example 1.

[0094] Example 3

[0095] This embodiment provides a light emitting diode chip, which is different from the embodiment 2 in that:

[0096] The third transparent conductive layer is filled in the through hole. The third transparent conductive layer is a periodic structure with 10 periods. Each period includes a Sc2O3 layer and a Sc, Sn co-doped In2O3 layer stacked in sequence. The thickness of the Sc2O3 layer is 1.5nm; the thickness of the Sc, Sn co-doped In2O3 layer is 13.5nm, and the Sc doping concentration is 7.5% and the Sn doping concentration is 17.6%.

[0097] Correspondingly, the preparation method also includes a step of preparing the third transparent conductive layer.

[0098] Comparative Example 1

[0099] This comparative example provides a light emitting diode chip, which is different from Example 1 in that:

[0100] Excluding the second transparent conductive layer, the first transparent conductive layer is an ITO layer, the In content of which is 8% and the thickness is

[0101] The rest are the same as in Example 1.

[0102] The light emitting diode chips obtained in Examples 1 to 3 and Comparative Example 1 were tested, and the specific results are shown in the following table:

[0103] Brightness(mW) Voltage (V) Example 1 115.4 3.096 Example 2 120.5 3.102 Example 3 132.5 2.814 Comparative Example 1 110.3 3.125

[0104] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A light emitting diode chip, characterized in that: include: substrate; An epitaxial layer, which is disposed on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on the substrate; The epitaxial layer is formed with an exposed area exposing the first semiconductor layer; A first transparent conductive layer stacked on the second semiconductor layer; a second transparent conductive layer stacked on the first transparent conductive layer; A first electrode, which is disposed on the first semiconductor layer in the exposed area and is electrically connected to the first semiconductor layer; and a second electrode, which is disposed on the second transparent conductive layer and electrically connected to the second semiconductor layer; The light transmittance of the first transparent conductive layer is smaller than the light transmittance of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is smaller than the sheet resistance of the second transparent conductive layer.

2. The light emitting diode chip according to claim 1, characterized in that: The light transmittance of the first transparent conductive layer is 72% to 85%, and the light transmittance of the second transparent conductive layer is 92% to 98%; The sheet resistance of the first transparent conductive layer is 4.6Ω / sq to 13.8Ω / sq, and the sheet resistance of the second transparent conductive layer is 18.6Ω / sq to 24.3Ω / sq; The first transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or a FTO layer; The second transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or a FTO layer.

3. The light emitting diode chip according to claim 1, characterized in that: The first transparent conductive layer and the second transparent conductive layer are both ITO layers; And the In content in the first transparent conductive layer is greater than or equal to the In content in the second transparent conductive layer.

4. The light emitting diode chip according to any one of claims 1 to 3, characterized in that: The first transparent conductive layer is an ITO layer, the In content of which is 8wt% to 15wt% and the thickness is The second transparent conductive layer is an ITO layer, the In content of which is 2wt% to 5wt% and the thickness is 5. The light emitting diode chip according to claim 1, characterized in that: A plurality of through holes are arranged in an array on the first transparent conductive layer to separate the first transparent conductive layer into a plurality of conductive units distributed in an array; The ratio of the cross-sectional area of ​​the first transparent conductive layer to the cross-sectional area of ​​the second transparent conductive layer is 5:100 to 30:100; The cross section of the conductive unit is circular, rectangular or triangular, and its width is 6. The light emitting diode chip according to claim 5, characterized in that: It also includes a first current blocking layer and a second current blocking layer, wherein the first current blocking layer is disposed between the first electrode and the first semiconductor layer and is covered by the first electrode; The second current blocking layer is disposed between the first transparent conductive layer and the second semiconductor layer, and is disposed below the second electrode, and a projection of the second electrode on the surface where the second current blocking layer is located covers the second current blocking layer; At least one conductive unit is disposed on the second current blocking layer.

7. The light emitting diode chip according to claim 1, characterized in that: The first conductive layer is provided with a plurality of through holes in an array so as to separate the first conductive layer into a plurality of conductive units distributed in an array; The through hole is filled with a third transparent conductive layer, and the third transparent conductive layer is a periodic structure, and each period includes sequentially stacked Sc2O3 layers and Sc and Sn co-doped In2O3 layers.

8. The light emitting diode chip according to claim 7, characterized in that: The thickness of the Sc2O3 layer is 1nm to 2nm; The thickness of the Sc and Sn co-doped In2O3 layer is 10nm-15nm, the Sc doping concentration is 5%-10%, and the Sn doping concentration is 15%-20%.

9. A method for preparing a light emitting diode chip, for preparing the light emitting diode chip according to any one of claims 1 to 8, characterized in that: include: forming an epitaxial layer on a substrate; the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on the substrate; Etching the epitaxial layer to form an exposed area exposing the first semiconductor layer; sequentially forming a first transparent conductive layer and a second transparent conductive layer on the second semiconductor layer; forming a second electrode on the second transparent conductive layer, and forming a first electrode on the first semiconductor layer in the exposed area; The light transmittance of the first transparent conductive layer is smaller than the light transmittance of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is smaller than the sheet resistance of the second transparent conductive layer.

10. The method for preparing a light emitting diode chip according to claim 9, characterized in that: The step of sequentially forming a first transparent conductive layer and a second transparent conductive layer on the second semiconductor layer comprises: forming a plurality of conductive units on the second semiconductor layer to obtain a first transparent conductive layer; through holes are provided between the plurality of conductive units; forming a third transparent conductive layer in the through hole; forming a second transparent conductive layer on the first transparent conductive layer and the third transparent conductive layer; Anneal in O2 atmosphere at 500℃~600℃ for 10min~20min.

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