I2C register mapping with virtual extensions

Abstract

A system (110) is presented that includes at least one integrated circuit interconnect node (I2C node) (112), at least one master controller (114), and at least one integrated circuit interconnect (I2C) (116). The I2C (116) is configured to transfer data between the I2C node (112) and the master controller (114). The I2C node (112) provides a register map (118). The main controller (114) is configured to read the register map (118) bytewise. The I2C node (112) is configured for incrementing the register address after each byte. The register map (118) includes a physical register map (120). The data of the physical register map (120) has a physical address in the memory of the I2C node (122). The I2C node (112) is configured to generate data that is larger in size than the physical register map (120). The register map (118) includes a virtual portion, where data of the virtual portion has an address in another memory location (124). The master controller (114) is configured to read the virtual portion by executing a transaction starting from a physical register map (118) and to increase the register address to a size beyond the physical register map.

Description

Technical Field

[0001] The present invention relates to a system comprising at least one inter-integrated circuit node (I2C node), a mobile device, a method for data transmission between at least one I2C node and at least one main controller, and several uses. Such methods and devices can generally be used for the purpose of research or monitoring, especially in the infrared (IR) spectral region, especially in the near infrared (NIR) spectral region, and for detecting heat, flames, fire or smoke. However, other types of applications are also possible. Background Art

[0002] An infrared spectrometer may be built into a mobile device, such as a smartphone. Such a spectrometer may typically include a plurality of IR sensors (also denoted as pixels), each having a filter for a different wavelength, so that each sensor can measure the intensity of light at a specific wavelength. The data thus acquired may need to be transmitted to the mobile device so that its processing unit, in particular its central processing unit (CPU), can further process the data. Data transmission in mobile devices often uses the so-called Inter-Integrated Circuit (I2C) protocol, which is designed for relatively simple components that transmit small amounts of data.

[0003] Cypress Semiconductor: "Master Slave 1.20", PSoC Creator Part Datasheet, 2015-12-20, page 1-36, XP093019583, gives a general description of I2C slave and master configuration.

[0004] Typically, an I2C node (such as a sensor module) can provide a standard 8-bit register map. For example, the data size generated by the I2C node may be larger than the register map, such as larger than 256 bytes, with size N>256. The master can read and write the register map byte by byte, and the node can automatically increment the address after each byte, so that a single transaction can include more than one byte.

[0005] For spectrometers, however, the data can quickly become very large. This is because different sensors (pixels) each provide a value. In addition, multiple measurements may be performed in order to improve the signal. Therefore, a fast readout of the generated data can be problematic and may need to be performed using complex techniques.

[0006] Problem to be solved

[0007] The problem addressed by the present invention is therefore to provide a system, a mobile device and a method for data transmission which at least substantially avoid the disadvantages of known methods and devices of this type. In particular, it is desirable to provide a method and a device which ensure a fast readout of data in a simple manner. Summary of the invention

[0008] The problem is solved by a system, a mobile device, a data transmission method having the features of the independent claims. Advantageous embodiments are listed in the dependent claims as well as in the entire description, which can be realized individually or in any arbitrary combination.

[0009] In a first aspect of the present invention, a system is disclosed, which includes at least one integrated circuit interconnect node (I2C node), at least one host controller and at least one integrated circuit interconnect (I2C). The I2C is configured to transfer data between the I2C node and the host controller. The I2C node provides a register map. The host controller is configured to read the register map byte by byte. The I2C node is configured to increment the register address after each byte. The register map includes a physical register map. The data of the physical register map has a physical address in a memory of the I2C node. The I2C node is configured to generate data of a size greater than the physical register map. The register map includes a virtual portion. The data of the virtual portion has an address in another memory location. The host controller is configured to read the virtual portion by executing a transaction starting from the physical register map. The transaction length of the transaction extends beyond the size of the physical register map. In particular, the transaction starts from a starting address and the transaction length is greater than the size of the physical register map.

[0010] As used herein, the term "system" is a broad term and will be given its ordinary and conventional meaning to those of ordinary skill in the art and is not limited to a special or custom meaning. The term specifically may refer to, but is not limited to, any set of interacting or interdependent components that form a whole. Specifically, these components may interact with each other to achieve at least one common function. At least two components may be processed independently, or may be coupled or connectable. The system includes at least one integrated circuit interconnect node (I2C node), at least one master controller, and at least one integrated circuit interconnect (I2C).

[0011] As used herein, the term "inter-integrated circuit" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a data bus configured to connect integrated circuits. For example, I2C may be designed as described in https: / / www.nxp.com / docs / en / user-guide / UM10204.pdf, www.ipd.kit.edu / ~buchmann / microcontroller / i2c.htm, or www.ti.com / lit / an / slva704 / slva704.pdf. I2C may be a synchronous, packet-switched, single-ended serial communication bus. Specifically, I2C is a hierarchical bus system with a so-called master-slave architecture, including at least one master controller and at least one I2C node.

[0012] The system may include one or more I2C nodes. As used herein, the term "I2C node" (also represented as a slave) is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to special or custom meanings. The term specifically may refer to, but is not limited to, any I2C device connected to an I2C bus. For example, an I2C node includes at least one sensor. The sensor may include at least one element selected from the group consisting of the following: at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor (intelligent sensor) with data buffering and automatic data accumulation functions. For example, an I2C node is a spectrometer. A spectrometer may include a plurality of pixels, each pixel having a filter of a different wavelength, so each pixel can measure the light intensity of a specific wavelength. The I2C node may further include at least one processor, such as at least one microprocessor, at least one microcontroller and / or at least one computer.

[0013] As used herein, the term "processor" is a broad term, and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, any logic circuit configured to perform the basic operations of a computer or system, and / or generally refers to a device configured to perform calculations or logical operations. In particular, a processor may be configured to process basic instructions that drive a computer or system. As an example, a processor may include at least one arithmetic logic unit (ALU), at least one floating point unit (FPU), such as a math coprocessor or a digital coprocessor, a plurality of registers, specifically configured to provide operands to the ALU and store operation results, and memories such as L1 and L2 cache memories. In particular, a processor may be a multi-core processor. In particular, a processor may be or may include a central processing unit (CPU). A processor may be or may include a microprocessor, so in particular, the elements of a processor may be contained in a single integrated circuit (IC) chip. The processor may further include one or more application specific integrated circuits (ASICs) and / or one or more field programmable gate arrays (FPGAs) and / or one or more tensor processing units (TPUs) and / or one or more chips, such as dedicated machine learning optimization chips, etc. The processor may be specifically configured, such as by software programming, to perform one or more evaluation operations.

[0014] The system may include one or more master controllers. As used herein, the term "master controller" (also referred to as master station) is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term specifically may refer to, but is not limited to, at least one processor, such as at least one microprocessor, at least one microcontroller and / or at least one computer designated as a system master station. The master controller may be configured to address one or more I2C nodes, but not vice versa.

[0015] I2C is configured to transfer data between an I2C node and a host controller. The transfer may include data exchange. The data may be transferred in a sequence of 8 bits. One data bit may be transferred during each clock cycle.

[0016] The I2C bus can be based on two wires, one of which is used to transmit a clock signal (serial clock line SCL) and the other is used to transmit data bits (serial data line SDA). The clock signal can be generated by a master controller. The master controller can be configured to initiate data transmission by sending a query to the I2C node. In order to start data transmission, the master controller can be configured to specify the address of the I2C node with which it wants to exchange data. Each I2C node may include an address hardwired into the chip of the I2C node, in particular a 4-bit address. In addition, the chip of each I2C node may include multiple address pins, which can be assigned arbitrary addresses. In order to address the corresponding I2C node, multiple bits, such as 7 bits, can be used and transmitted. At least one additional bit can be used to specify whether the master controller is to send data to the I2C node (i.e., write) or receive data from the I2C node (i.e., read). As described in www.ti.com / lit / an / slva704 / slva704.pdf, the process for the master controller to read data from the I2C node can be carried out as follows

[0017] - The master controller sends a START condition and addresses the I2C node, where a transition from high to low on the SDA line while SCL is high defines a START condition;

[0018] -The master controller sends a request to the I2C node to read the register;

[0019] -The master controller receives data from the I2C node;

[0020] - The master controller terminates the transfer through a STOP condition, where a low-to-high transition on the SDA line while SCL is high defines a STOP condition.

[0021] The I2C node may include one or more registers. As used herein, the term "register" is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a location in the memory of the I2C node that is configured to store information. The information may be configuration information and / or data obtained by at least one sensor of the I2C node. The information stored in the register may be a value, particularly one or more of a measured value, a measurement uncertainty, a calibration value, a (system) configuration value, a measurement parameter. Each register may have a unique address. Each register may include 8 bits. The master controller is configured to read (and optionally write) a register map byte by byte. The master controller may read and write a register map byte by byte. The I2C node is configured to increment the register address after each byte.

[0022] Typically, reading from a register can be performed as follows, such as described in www.ti.com / lit / an / slva704 / slva704.pdf. The master controller can be configured to indicate to the I2C node which register map it wishes to read from. The master controller can be configured to start the transfer by sending an address along with a bit indicating a write, followed by the register address it wishes to read from. After the I2C node acknowledges the register address, the master controller can again send a START condition, followed by the I2C node address, followed by a bit indicating a read. The I2C node can acknowledge the read request. The master controller can continue to issue clock pulses, but will release the SDA line so that the I2C node can transmit data. At the end of each byte of data, the master controller can send an ACK (acknowledgement) to the I2C node, letting the I2C node know that it is ready to receive more data. Once the master controller has received the expected number of bytes, it sends a NACK (negative acknowledgement), signaling the I2C node to stop communicating and release the bus. The master controller can then issue a STOP condition. The master controller can read and write the register map byte by byte. I2C nodes can be configured to automatically increment the address after each byte so that a single transaction can include more than one byte.

[0023] The I2C node provides a register map. As used herein, the term "register map" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, an ordered list of registers. The I2C node may include one or more registers. Each register may have a unique address. The register map may include a register map layout. The register map may include multiple columns and multiple rows. The register map may include an index N for each register. For example, the register map may include two columns, wherein the first column lists the index and the second column lists the register name. The register map may include a size. The size of the index N may be equal to the size of the register map.

[0024] The register map includes a physical register map. The data of the physical register map has a physical address in the memory of the I2C node. The I2C node is configured to generate data larger than the size of the physical register map. As used herein, the term "physical register map" is a broad term and will be given its ordinary and conventional meaning for ordinary technicians in the field and is not limited to special or custom meanings. The term may specifically refer to, but is not limited to, a part of the register map, which includes a register with a physical address in the memory of the I2C node. As used herein, the term "memory" is a broad term and will be given its ordinary and conventional meaning for ordinary technicians in the field and is not limited to special or custom meanings. The term may specifically refer to, but is not limited to, a device or system configured to store data. The memory of the I2C node may include a semiconductor memory. The memory of the I2C node may include a volatile memory and / or a non-volatile memory. For example, the memory of the I2C node may include one or more of RAMs, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). For example, the memory of the I2C node may include one or more of a flash memory, a ROM, a PROM, an EPROM, an EEPROM memory, and a ferroelectric random access memory (FRAM). The physical register map may include the size of the physical register map. The I2C node is configured to provide the physical register map as a standard 8-bit register map. The size of the physical register map may be N≤256. The I2C node may be configured to generate data of size N>256 bytes.

[0025] Typically, the size of the physical register map is 256 bytes, where the index N can be from 0 to 255. However, the size of the data generated by the I2C node may be larger than the physical register map (e.g., larger than 256 bytes) (size N>256). In this case, for example, the size of the register map can be increased. However, in some cases (e.g., the I2C node does not have enough RAM, or the size of the register address is fixed to 8 bits for software compatibility considerations), this may not be possible. Additionally or alternatively, the register map can be partitioned into smaller sizes and multiple transactions can be used to perform data transfers. For example, the data is partitioned into a smaller size that fits the register map, such as the size of a 128-byte value. The register map may include a special control register called "partition index" that controls which partition the host controller accesses. In order to read all the data, the host controller can first perform a write transaction to the partition index and then perform a read transaction, so that up to 254 bytes can be transferred. This pair of transactions must be performed multiple times until all the data is transferred. Therefore, if the data is partitioned and the partition index is used, multiple transactions must be performed. However, in the case of partitions, there will be a transfer gap between transactions. There will be a gap between transactions due to one or more of the following reasons: a) the bus may be in use by another sensor, b) natural processing delays, i.e., starting a new transaction requires several CPU cycles, c) the process requesting the next transfer is sleeping and waiting to be scheduled again (on systems with an operating system). The contribution of a) and b) depends mainly on the system load and processor performance. Depending on the number of bytes and the operating system, these gaps can become large (e.g., non-real-time operating systems such as Linux, Android, etc.).

[0026] Specifically, in order to be able to read out quickly even when the size of the data generated by the I2C node is larger than the physical register mapping, the present invention proposes a register mapping including a virtual part. The register mapping can be virtually extended. The data of the virtual part has an address in another memory location. As used herein, the term "virtual part" is a broad term and will be given its ordinary and conventional meaning for ordinary technicians in the field and is not limited to special or custom meanings. The term can specifically refer to but is not limited to another part of the register mapping, that is, in addition to the physical register mapping, it also includes a register with an address in another memory location. As used herein, the term "another memory location" is a broad term and will be given its ordinary and conventional meaning for ordinary technicians in the field and is not limited to special or custom meanings. The term can specifically refer to but is not limited to any memory location other than the memory including data related to the physical register mapping. The other memory location can be a physical storage location of the I2C node other than the memory, and / or the other memory location can be a memory location outside the I2C node. The other memory location can be a memory location where all data is available in a continuous form. Due to the continuous form, the I2C node can provide all data for reading in a single transaction.

[0027] The virtual portion cannot be addressed directly. The master controller is configured to read the virtual portion by executing a transaction starting from the physical register map. The transaction length of the transaction extends beyond the size of the physical register map. In particular, the transaction starts from the starting address and the transaction length is greater than the size of the physical register map. In order to read all the data generated by the I2C node, the master controller can start reading the first value (e.g., register address 0) and can continue reading after reading value 255 until all the data of the registers of the virtual portion are transferred (e.g., values ​​256 to N, where N>256). With this technique, all data is transferred in a single read transaction. Virtually extending the register map can provide the fastest solution for transferring all data.

[0028] As described above, the I2C node can be configured to automatically increment the address after each byte. When the address reaches the end of the physical register map, it cannot fetch data from the next consecutive physical address. The I2C node can be configured to provide the next data from the first register of the virtual portion. The I2C node can be configured to provide the next data by converting between an address in another memory location and a physical address in memory when the register address reaches the end of the physical register map.

[0029] For example, the I2C node can be configured to fill the physical register map with the value from the virtual part, and when the register address reaches the end of the physical register map, the physical address is reset back to zero. This process can be transparent to the master controller. The master controller can be configured to read as many values ​​and / or bytes as possible from the virtual part as needed and / or predefined (e.g., by a driver). Whenever the address in another memory location reaches a multiple of the size of the physical register map, the process occurs. The I2C node can be configured to update and / or refill the physical register map with the original value of page 0 after the transfer is completed.

[0030] The I2C node can be configured to operate with at least one special register. The I2C node can be configured to operate with multiple special registers. Only when the reading starts from a special register (or one of multiple special registers), the virtual extension of the physical register map is available. As used herein, the term "special register" is a broad term, and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to special or custom meanings. The term specifically refers to, but is not limited to, a register with a predefined and / or pre-assigned function in the physical register map. The special register can be any register or multiple registers in the physical register map. For example, the special register can be register 0 or the last register of the physical register map. For example, the special register can be placed after all register values ​​(if any) of the physical register map. If the main controller starts to read the special register, the I2C node can be configured to provide data stored in another memory location. This can also be transparent to the main controller. For example, once the main controller starts to read the special register, the I2C node can send data stored in different storage locations internally. If the read starts from a special register, the I2C node may fetch the data not from the physical register map but from a special memory location where all data is available in a contiguous form. The address in another memory location may be defined by another register, for example, by an offset to a special register location.

[0031] In another aspect, a mobile device is disclosed, comprising at least one system according to the present invention (e.g., according to any embodiment related to the system described above or in more detail below). For further details about the mobile device, reference may be made to the description of the system as described above and in more detail below. The mobile device is at least one element selected from the group consisting of: a notebook computer, a tablet computer, a mobile phone, a smart phone, a smart watch, and a wearable computer. The mobile device is configured to use at least one I2C protocol to perform data transmission within the mobile device.

[0032] In another aspect, a method for data transmission between at least one integrated circuit interconnect node (I2C node) and at least one host controller is disclosed. The method comprises using a system according to the present invention (e.g., according to any embodiment related to the system described above or in more detail below). The method comprises the following steps:

[0033] - Generate data larger than the physical register map and provide the register map using the I2C node;

[0034] - Read the register map byte by byte using this master controller and increment the register address after each byte using this I2C node,

[0035] - reading the virtual portion of the register map using the master controller by executing a transaction starting from the physical register map, wherein a transaction length of the transaction extends the register address beyond the size of the physical register map.

[0036] The method steps may be performed in the order indicated. However, it should be noted that a different order is also possible. The method may include additional method steps that are not listed. Further, one or more of the method steps may be performed once or repeatedly. Further, two or more of the method steps may be performed simultaneously or in a time-overlapping manner. The method may include repeating steps at predefined times or continuously.

[0037] The method may be computer-implemented. As used herein, the term "computer-implemented method" is a broad term and will be given its ordinary and conventional meaning for a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a method involving at least one computer and / or at least one computer network. The computer and / or computer network may include at least one processor that may be configured to perform at least one method step of the method according to the present invention. Specifically, each of these method steps is performed by a computer and / or a computer network. The method may be performed fully automatically, specifically without user interaction.

[0038] The method may include transmitting sensor data generated by an I2C node. The I2C node may include at least one sensor. The sensor may include at least one element selected from the group consisting of: at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor with data buffering and automatic data accumulation functions. For example, the I2C node is a spectrometer. The spectrometer may include a plurality of pixels, each pixel having a filter of a different wavelength, so that each pixel can measure the light intensity of a specific wavelength.

[0039] The I2C node can provide the next data when the register address reaches the end of the physical register map by converting between the address in another memory location and the physical address in memory.

[0040] When the register address reaches the end of the physical register map, the I2C node can fill the physical register map with the value of the virtual portion and reset the physical address back to zero. This process can be transparent to the host controller. The host controller can read as many values ​​and / or bytes from the virtual portion as needed and / or predefined (e.g., by a driver). This process occurs whenever the address in another memory location reaches a multiple of the size of the physical register map.

[0041] The I2C node can operate with at least one special register. If the host controller starts reading the special register, the I2C node can provide data stored in another memory location. This process can be transparent to the host controller.

[0042] This article further discloses and proposes a computer program, which includes computer executable instructions for executing the method according to the present invention in one or more embodiments contained in this article when the program is executed on a computer or a computer network. Specifically, the computer program can be stored on a computer readable data carrier and / or a computer readable storage medium.

[0043] As used herein, the terms "computer-readable data carrier" and "computer-readable storage medium" may specifically refer to a non-transitory data storage device, such as a hardware storage medium on which computer-executable instructions are stored. A computer-readable data carrier or storage medium may specifically be or may include a storage medium such as a random access memory (RAM) and / or a read-only memory (ROM).

[0044] Thus, in particular, one, more than one or even all of the method steps as indicated above may be performed by using a computer or a computer network, preferably by using a computer program.

[0045] This article further discloses and proposes a computer program product with program code means, so that when the program is executed on a computer or a computer network, the method according to the present invention in one or more embodiments contained in this article is performed. Specifically, the program code means can be stored on a computer-readable data carrier and / or a computer-readable storage medium.

[0046] This document further discloses and proposes a data carrier having a data structure stored thereon, which, after being loaded into a computer or a computer network (such as loaded into a working memory or a main memory of a computer or a computer network), can execute a method according to one or more embodiments disclosed herein.

[0047] This article further discloses and proposes a computer program product having program code means stored on a machine-readable carrier so that when the program is executed on a computer or computer network, a method according to one or more embodiments disclosed herein is performed. As used herein, a computer program product refers to a program that is a tradable product. The product can generally exist in any format, such as in paper format, or on a computer-readable data carrier and / or a computer-readable storage medium. Specifically, the computer program product can be distributed via a data network.

[0048] Finally, a modulated data signal containing instructions readable by a computer system or a computer network for executing a method according to one or more embodiments disclosed herein is disclosed and proposed herein.

[0049] With reference to the computer-implemented aspects of the present invention, one or more or even all of the method steps of the methods according to one or more of the embodiments disclosed herein may be performed using a computer or a computer network. Thus, typically, any of the method steps including the provision and / or manipulation of data may be performed using a computer or a computer network. Typically, these method steps may include any method steps, except for method steps that typically require manual work, such as providing samples and / or performing certain aspects of the actual measurement.

[0050] Specifically, this article further discloses:

[0051] - a computer or a computer network comprising at least one processor, wherein the processor is adapted to execute the method according to one of the embodiments described in this specification,

[0052] - a computer-loadable data structure, which is suitable for performing a method according to one of the embodiments described in this specification when the data structure is executed on a computer,

[0053] - a computer program, wherein the computer program is adapted to perform a method according to one of the embodiments described in this specification when the program is executed on a computer,

[0054] - a computer program comprising program means for executing a method according to one of the embodiments described in the present description when the computer program is executed on a computer or on a computer network,

[0055] - a computer program comprising the program means according to the preceding embodiment, wherein the program means is stored on a computer-readable storage medium,

[0056] - a storage medium, on which a data structure is stored, and wherein the data structure is suitable for executing a method according to one of the embodiments described in the present description after being loaded into a main storage device and / or a working storage device of a computer or a computer network, and

[0057] A computer program product having program code means, wherein the program code means can be stored or stored on a storage medium for performing a method according to one of the embodiments described in the present description when the program code means is executed on a computer or a computer network.

[0058] In another aspect of the present invention, there is disclosed the use of a system according to any of the embodiments of the system described above or below in further detail for a purpose of use selected from the group consisting of: infrared detection applications; thermal detection applications; thermometer applications; heat seeking applications; flame detection applications; fire detection applications; smoke detection applications; temperature sensing applications; spectroscopy applications; exhaust monitoring applications; combustion process monitoring applications; pollution monitoring applications; industrial process monitoring applications; chemical process monitoring applications; food processing process monitoring applications; water quality monitoring applications; air quality monitoring applications; quality control applications; temperature control applications; motion control applications; emission control applications; gas sensing applications; gas analysis applications; motion sensing applications; chemical sensing applications; mobile applications; medical applications; mobile spectroscopy applications; food analysis applications.

[0059] As used herein, the terms "having", "including" or "comprising" or any arbitrary grammatical variant thereof are used in a non-exclusive manner. Thus, these terms may refer to the absence of additional features in the entity described in this context in addition to the features introduced by these terms, or the presence of one or more additional features. As an example, the expressions "A has B", "A includes B" and "A contains B" may refer to the absence of other elements in A in addition to B (i.e., A consists only and solely of B), or the presence of one or more additional elements in entity A in addition to B (such as element C, elements C and D or even additional elements).

[0060] Further, it should be noted that the terms "at least one", "one or more", or similar expressions indicating that a feature or element may occur once or more than once are typically used only once when introducing the corresponding feature or element. In most cases, when referring to the corresponding feature or element, the expression "at least one" or "one or more" is not repeated, although the corresponding feature or element may occur once or more than once.

[0061] Further, as used herein, the terms "preferably", "more preferably", "particularly", "more particularly", "specifically", "more specifically" or similar terms are used in conjunction with optional features without limiting the possibilities of alternatives. Therefore, the features introduced by these terms are optional features and are not intended to limit the scope of the claims in any way. As the skilled person will recognize, the present invention can be implemented by using alternative features. Similarly, the features introduced by "in an embodiment of the present invention" or similar expressions are intended to be optional features, without any limitation on alternative embodiments of the present invention, without any limitation on the scope of the present invention, and without any limitation on the possibility of combining the features introduced in this manner with other optional or non-optional features of the present invention.

[0062] Summarizing and without excluding further possible embodiments, the following embodiments may be envisaged:

[0063] Embodiment 1. A system comprising at least one integrated circuit interconnect node (I2C node), at least one host controller and at least one integrated circuit interconnect (I2C), wherein the I2C is configured to transfer data between the I2C node and the host controller, wherein the I2C node provides a register map, wherein the host controller is configured to read the register map byte by byte, wherein the I2C node is configured to increment a register address after each byte, wherein the register map includes a physical register map, wherein data of the physical register map has a physical address in a memory of the I2C node, wherein the I2C node is configured to generate data having a size greater than the physical register map, wherein the register map includes a virtual portion, wherein data of the virtual portion has an address in another memory location, wherein the host controller is configured to read the virtual portion by executing a transaction starting from the physical register map and incrementing the register address to a size beyond the physical register map.

[0064] Embodiment 2. The system according to the preceding embodiment, wherein the I2C node is configured to provide next data by converting between the address in the other memory location and the physical address in the memory when the register address reaches the end of the physical register map.

[0065] Embodiment 3. A system according to any one of the preceding embodiments, wherein, when the register address reaches the end of the physical register map, the I2C node is configured to fill the physical register map with the value of the virtual portion and reset the physical address back to zero, wherein the process is transparent to the host controller.

[0066] Embodiment 4. The system according to the preceding embodiment, wherein the master controller is configured to read as many values ​​and / or bytes from the virtual part as needed and / or predefined.

[0067] Embodiment 5. A system according to any one of the two preceding embodiments, wherein the process occurs whenever the address in the other memory location reaches a multiple of the size of the physical register map.

[0068] Embodiment 6. A system according to any one of the preceding embodiments, wherein the I2C node is configured to operate with at least one special register, wherein if the host controller starts reading the special register, the I2C node is configured to provide data stored in the other memory location, wherein the process is transparent to the host controller.

[0069] Embodiment 7. The system according to the preceding embodiment, wherein the I2C node is configured to operate with a plurality of special registers.

[0070] Embodiment 8. A system according to any one of the two preceding embodiments, wherein the special register is one or more of register 0 and the last register of the physical register mapping.

[0071] Embodiment 9. The system of any one of the preceding embodiments, wherein the another memory location is a memory location where all data is available in a contiguous form.

[0072] Embodiment 10. A system according to any one of the preceding embodiments, wherein the I2C node is configured to provide a physical register map as a standard 8-bit register map, wherein the I2C node is configured to generate data of size N>256 bytes.

[0073] Embodiment 11. A system according to the previous embodiment, wherein the I2C node includes at least one sensor, wherein the sensor includes at least one element selected from the group consisting of: at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor with data buffering and automatic data accumulation functions.

[0074] Embodiment 12. The system according to the previous embodiment, wherein the I2C node is a spectrometer, wherein the spectrometer comprises a plurality of pixels, each pixel having a filter of a different wavelength, so that each pixel can measure the intensity of light of a specific wavelength.

[0075] Embodiment 13. A mobile device, comprising at least one system according to any one of the preceding embodiments, wherein the mobile device is at least one element selected from the group consisting of: a notebook computer, a tablet computer, a mobile phone, a smart phone, a smart watch, and a wearable computer, wherein the mobile device is configured to use at least one I2C protocol to perform data transmission within the mobile device.

[0076] Embodiment 14. A method for data transmission between at least one integrated circuit interconnect node (I2C node) and at least one host controller, wherein the method comprises using a system according to any of the above embodiments involving systems, wherein the method comprises the following steps:

[0077] - Generate data larger than the physical register map and provide the register map using the I2C node;

[0078] - Read the register map byte by byte using this master controller and increment the register address after each byte using this I2C node,

[0079] - Using the master controller to read the virtual portion of the register map by executing a transaction starting from the physical register map and increasing the register address beyond the size of the physical register map.

[0080] Embodiment 15. The method according to the previous embodiment, wherein the I2C node provides the next data by converting between the address in the other memory location and the physical address in the memory when the register address reaches the end of the physical register map.

[0081] Embodiment 16. A method according to any one of the aforementioned method-related embodiments, wherein, when the register address reaches the end of the physical register map, the I2C node uses the value of the virtual part to fill the physical register map and resets the physical address back to zero, wherein the process is transparent to the host controller.

[0082] Embodiment 17. A method according to the preceding embodiment, wherein the master controller reads as many values ​​and / or bytes from the virtual part as needed and / or predefined.

[0083] Embodiment 18. A method according to any one of the two preceding embodiments, wherein the process occurs whenever the address in the other memory location reaches a multiple of the size of the physical register map.

[0084] Embodiment 19. A method according to any one of the aforementioned method-related embodiments, wherein the I2C node operates with at least one special register, wherein if the host controller starts reading the special register, the I2C node provides the data stored in the other memory location, wherein the process is transparent to the host controller.

[0085] Embodiment 20. A method according to any one of the aforementioned embodiments involving methods, wherein the method includes transmitting sensor data generated by the I2C node, wherein the I2C node includes at least one sensor, wherein the sensor includes at least one element selected from the group consisting of: at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor with data buffering and automatic data accumulation functions.

[0086] Embodiment 21. The method according to the previous embodiment, wherein the I2C node is a spectrometer, wherein the spectrometer includes a plurality of pixels, each pixel having a filter of a different wavelength, so that each pixel can measure the intensity of light of a specific wavelength.

[0087] Embodiment 22. The method according to any one of the above method embodiments, wherein the method is computer-implemented.

[0088] Embodiment 23. A computer program, comprising instructions, which, when the system according to any one of the above embodiments involving systems executes the program, cause the system to execute the method according to any one of the above embodiments involving methods.

[0089] Embodiment 24. A computer-readable storage medium comprising instructions, which, when executed by a system according to any one of the preceding embodiments involving systems, causes the system to perform a method according to any one of the preceding embodiments involving methods.

[0090] Embodiment 25. A non-transitory computer-readable medium comprising instructions, which when executed by one or more processors cause the one or more processors to perform a method according to any one of the methods described in the preceding embodiments.

[0091] Embodiment 26. Use of the system according to any one of the aforementioned embodiments involving the system for a purpose of use selected from the group consisting of: infrared detection applications; thermal detection applications; thermometer applications; heat seeking applications; flame detection applications; fire detection applications; smoke detection applications; temperature sensing applications; spectroscopy applications; exhaust monitoring applications; combustion process monitoring applications; pollution monitoring applications; industrial process monitoring applications; chemical process monitoring applications; food processing process monitoring applications; water quality monitoring applications; air quality monitoring applications; quality control applications; temperature control applications; motion control applications; emission control applications; gas sensing applications; gas analysis applications; motion sensing applications; chemical sensing applications; mobile applications; medical applications; mobile spectroscopy applications; food analysis applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] Other optional features and embodiments are preferably disclosed in more detail in the subsequent description of the embodiments in conjunction with the dependent claims. Wherein, as the skilled person will recognize, the corresponding optional features can be implemented in an independent manner and in any arbitrary feasible combination. The scope of the present invention is not limited by the preferred embodiments. The embodiments are schematically depicted in the accompanying drawings. Wherein, the same reference numerals in these drawings represent the same or functionally equivalent elements.

[0093] In the attached picture:

[0094] Figure 1 An embodiment of a system according to the present invention is shown;

[0095] Figure 2A and Figure 2B Data readout is shown;

[0096] Figure 3 An embodiment of the method according to the present invention is shown; and

[0097] Figure 4 A further embodiment of the method according to the invention is shown. DETAILED DESCRIPTION

[0098] Figure 1An embodiment of a system 110 (e.g., a mobile device 111) according to the present invention is shown. The system 110 includes at least one integrated circuit interconnect node (I2C node) 112, at least one host controller 114, and at least one integrated circuit interconnect (I2C) 116. The I2C 116 is configured to transfer data between the I2C node 112 and the host controller 114. The I2C node 112 provides a register map 118. The host controller 114 is configured to read the register map 118 byte by byte. The I2C node 112 is configured to increment the register address after each byte. The register map 118 includes a physical register map 120. The data of the physical register map 120 has a physical address in a memory 122 of the I2C node 112. The I2C node 112 is configured to generate data of a size larger than the physical register map 120. The register map 118 includes a virtual portion. The data of the virtual portion has an address in another memory location 124. The host controller 114 is configured to read the virtual portion by executing a transaction starting from the physical register map 120. The transaction length of the transaction extends beyond the size of the physical register map. Specifically, the transaction starts from a start address and the transaction length is greater than the size of the physical register map.

[0099] The integrated circuit interconnect 116 may be a data bus configured to connect integrated circuits. For example, the I2C 116 may be designed as described in https: / / www.nxp.com / docs / en / user-guide / UM10204.pdf, www.ipd.kit.edu / ~buchmann / microcontroller / i2c.htm, or www.ti.com / lit / an / slva704 / slva704.pdf. The I2C 116 may be a synchronous, packet-switched, single-ended serial communication bus. Specifically, the I2C 116 is a hierarchical bus system having a so-called master-slave architecture, including a master controller 114 and an I2C node 112.

[0100] System 110 may include one or more I2C nodes 112. I2C node 112 may be any I2C device connected to I2C bus 116. For example, I2C node 112 includes at least one sensor. The sensor may include at least one element selected from the group consisting of: at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor with data buffering and automatic data accumulation function (smart sensor). For example, I2C node 112 is a spectrometer. The spectrometer may include a plurality of pixels, each pixel having a filter of a different wavelength, so each pixel can measure the light intensity of a specific wavelength. I2C node 112 may further include at least one processor, such as at least one microprocessor, at least one microcontroller and / or at least one computer.

[0101] The system may include one or more master controllers 114. The master controller 114 may be or may include at least one processor, such as at least one microprocessor, at least one microcontroller and / or at least one computer designated as a system master. The master controller 114 may be configured to address one or more I2C nodes 112, but not vice versa. The I2C 116 is configured to transmit data between the I2C nodes 112 and the master controller 114. The transmission may include data exchange. The data may be transmitted in a sequence of 8 bits. One data bit may be transmitted during each clock cycle.

[0102] The I2C bus 116 can be based on two lines, one of which is used to transmit a clock signal (serial clock line SCL) and the other is used to transmit data bits (serial data line SDA). The clock signal can be generated by the master controller 114. The master controller 114 can be configured to initiate data transmission by sending a query to the I2C node 112. In order to start data transmission, the master controller 114 can be configured to specify the address of the I2C node 112 that it wants to exchange data. Each I2C node 112 may include an address hardwired to the chip of the I2C node 112, in particular a 4-bit address. In addition, the chip of each I2C node 112 may include multiple address pins, which can be assigned any address. In order to address the corresponding I2C node 112, multiple bits, such as 7 bits, can be used and transmitted. At least one additional bit can be used to specify whether the master controller 114 is to send data to the I2C node 112 (i.e., write) or receive data from the I2C node 112 (i.e., read). As described in www.ti.com / lit / an / slva704 / slva704.pdf, the process of the master controller 114 reading data from the I2C node can be performed as follows

[0103] - the master controller 114 sends a START condition and addresses the I2C node 112, wherein a transition from high to low on the SDA line when SCL is high defines a START condition;

[0104] - The master controller 114 sends a register read request to the I2C node 112;

[0105] - The master controller 114 receives data from the I2C node 112;

[0106] - The master controller 114 terminates the transfer via a STOP condition, where a low-to-high transition on the SDA line while SCL is high defines a STOP condition.

[0107] The I2C node 112 may include one or more registers. The register may be a location in the memory 122, 124 of the I2C node 112 configured to store information. The information may be configuration information and / or data obtained by at least one sensor of the I2C node 112. The information stored in the register may be a value, in particular a measurement value, a measurement uncertainty, a calibration value, a (system) configuration value, a measurement parameter, one or more. Each register may have a unique address. Each register may include 8 bits. The main controller 114 is configured to read (and optionally write) a register map byte by byte. The main controller 114 may read and write a register map byte by byte. The I2C node 112 is configured to increment the register address after each byte.

[0108] Typically, reading from a register may be performed as follows, such as described in www.ti.com / lit / an / slva704 / slva704.pdf. The master controller 114 may be configured to indicate to the I2C node 112 which register map 118 it wishes to read from. The master controller 114 may be configured to begin a transfer by sending an address along with a bit indicating a write, and then sending the register address from which it wishes to read. After the I2C node 112 acknowledges the register address, the master controller 114 may again send a START condition, and then send the I2C node address along with a bit indicating a read. The I2C node 112 may acknowledge the read request. The master controller 114 may continue to issue clock pulses, but may release the SDA line so that the I2C node 112 may transmit data. At the end of each byte of data, the master controller 114 may send an ACK (acknowledgement) to the I2C node to let the I2C node 112 know that it is ready to receive more data. Once the master controller 114 receives the expected number of bytes, it sends a NACK (negative acknowledgement) to signal the I2C node 112 to stop communicating and release the bus. The master controller 114 may then issue a STOP condition. The master controller 114 may read and write the register map 118 byte by byte. The I2C node 112 may be configured to automatically increment the address after each byte so that a single transaction may include more than one byte.

[0109] As described above, the I2C node 112 provides a register map 118. The register map may be an ordered list of registers. The I2C node 112 may include one or more registers. Each register may have a unique address. The register map 118 may include a register map layout. The register map 118 may include multiple columns and multiple rows. The register map 118 may include an index N for each register. For example, Figure 1 As shown, the register map 118 may include two columns, wherein the first column lists the index and the second column lists the register name. The register map 118 may include a size. The size of the index N may be equal to the size of the register map 118.

[0110] The register map 118 includes a physical register map 120. The data of the physical register map 120 has a physical address in the memory 122 of the I2C node 112. The I2C node 112 is configured to generate data of a size larger than the physical register map 120. The physical register map 120 may be a portion of the register map 118 that includes registers having physical addresses in the memory 122 of the I2C node 112. The memory 122 may be or may include a device or system configured to store data. The memory 122 may include a semiconductor memory. The memory 122 of the I2C node 112 may include a volatile memory and / or a non-volatile memory. For example, the memory 122 of the I2C node 112 may include one or more of RAMs, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). For example, the memory 122 of the I2C node 112 may include one or more of a flash memory, a ROM, a PROM, an EPROM, an EEPROM memory, and a ferroelectric random access memory (FRAM). The physical register map 120 may include a size of the physical register map. The I2C node 112 is configured to provide the physical register map 120 as a standard 8-bit register map. The size of the physical register map may be N≤256. The I2C node 112 may be configured to generate data of size N>256 bytes.

[0111] Typically, the size of the physical register map 120 is 256 bytes, where the index N can range from 0 to 255. However, the size of the data generated by the I2C node 112 may be larger than the physical register map 120 (e.g., larger than 256 bytes) (size N>256). In this case, for example, the size of the register map can be increased. However, in some cases (e.g., the I2C node 112 does not have enough RAM, or the size of the register address is fixed to 8 bits for software compatibility considerations), this may not be possible. Additionally or alternatively, the register map 118 can be partitioned into smaller sizes and multiple transactions can be used to perform data transfers. The following table shows an example:

[0112]

[0113]

[0114] For example, the data is partitioned into a smaller size that fits into the register map 118, such as the size of a 128-byte value. The register map 118 may include a special control register called a "partition index" that controls which partition the host controller accesses. To read all the data, the host controller may first perform a write transaction to the partition index and then perform a read transaction, which may transfer up to 254 bytes. This pair of transactions must be performed multiple times until all the data is transferred. Therefore, if the data is partitioned and the partition index is used, multiple transactions must be performed. Figure 2A Such a data transfer is shown. However, in the case of partitions, there will be transfer gaps between transactions. There will be a gap between transactions due to one or more of the following reasons: a) the bus may be in use by another sensor, b) natural processing delays, i.e., starting a new transaction requires several CPU cycles, c) the process requesting the next transfer is dormant and waiting to be scheduled again (on a system with an operating system). The contribution of a) and b) depends mainly on the system load and processor performance. Depending on the number of bytes and the operating system, these gaps can become large (e.g., non-real-time operating systems such as Linux, Android, etc.).

[0115] Specifically, in order to enable fast reading even if the size of the data generated by the I2C node 112 is larger than the physical register map 120, the present invention proposes a register map 118 including a virtual part. The register map 118 can be virtually extended. The data of the virtual part has an address in another memory location 124. The virtual part can be another part of the register map 118, that is, in addition to the physical register map 120, it also includes a register with an address in another memory location 124. The other memory location 124 can be a physical storage location of the I2C node 112 that is different from the memory 122. The other memory location 124 can be a memory location where all data are available in a continuous form. Due to the continuous form, the I2C node 112 can provide all data for reading in a single transaction.

[0116] The following table shows an exemplary register map layout with virtual extension:

[0117]

[0118]

[0119] The virtual part cannot be addressed directly. The master controller 114 is configured to read the virtual part by executing a transaction starting from the physical register map 120. The transaction length of the transaction extends beyond the size of the physical register map. In order to read all the data generated by the I2C node 112, the master controller 114 can start reading the first value (e.g., register address 0), and can continue to read after reading the value 255 until all the data of the register of the virtual part is transmitted (e.g., value 256 to N, where N>256). With this technology, all data is transmitted in a single read transaction. Virtually extending the register map can provide the fastest solution for transmitting all data. Figure 2B Such a data transfer is shown.

[0120] As described above, the I2C node 112 can be configured to automatically increment the address after each byte. When the address reaches the end of the physical register map 120, it cannot fetch data from the next consecutive physical address. The I2C node 112 can be configured to provide the next data from the first register of the virtual portion. The I2C node 112 can be configured to provide the next data by converting between the address in another memory location 124 and the physical address 122 in the memory when the register address reaches the end of the physical register map 120.

[0121] For example, Figure 3As shown, the master controller can read 1 byte out of N bytes (reference numeral 126). If the end of the register map (reference numeral 128) is not reached at the end of the transfer (reference numeral 130), the I2C node 112 will update and / or refill the physical register map 120 with the original value of page 0 (reference numeral 132). If the end of the register map (reference numeral 128) is not reached and the transfer is not over (reference numeral 130), the master controller will continue to read 1 byte out of N bytes (reference numeral 126). However, if the end of the register map (reference numeral 128) is reached before the end of the transfer, the I2C node 112 can be configured to fill and / or update the physical register map 120 with a value from the virtual portion (reference numeral 134), and when the register address reaches the end of the physical register map 120 (reference numeral 128), the physical address is reset back to zero. This process can be transparent to the master controller 114. The master controller 114 may be configured to read as many values ​​and / or bytes from the virtual portion as needed and / or predefined (e.g., by a driver). This process occurs whenever the address in the other memory location 124 reaches a multiple of the size of the physical register map 120. The I2C node 112 may be configured to update and / or repopulate the physical register map 120 (reference numeral 132) with the original value of page 0 after the transfer is complete.

[0122] Figure 4Another embodiment is shown, in which the I2C node 112 can be configured to operate with at least one special register. The I2C node 112 can be configured to operate with multiple special registers. The virtual extension of the physical register map 120 is only available when the read starts from a special register (or one of multiple special registers). The special register can be a register with a predefined and / or pre-assigned function in the physical register map 120. The special register can be any register or multiple registers in the physical register map 120. The special register can be register 0. Other embodiments are also possible. For example, the special register can be placed after all register values ​​(if any) of the physical register map. If the main controller 114 starts to read the special register, the I2C node 112 can be configured to provide data stored in another memory location 124. This can also be transparent to the main controller 114. For example, once the main controller 114 starts to read the special register, the I2C node 112 can send data stored in different storage locations internally. If the read starts from a special register, the I2C node 112 may not obtain data from the physical register map 120, but from a special memory location where all data is available in a continuous form. The address in the other memory location 124 may be defined by another register, for example, by an offset to a special register location. Figure 4 As shown, in step 136, the master controller reads N bytes. If the special register (reference numeral 138) is not reached, the I2C node sends data from the physical register map (reference numeral 140). If the special register (reference numeral 138) is reached, the I2C node sends data from another memory location (reference numeral 142).

[0123] List of Reference Numerals

[0124] 110 System

[0125] 111 Mobile devices

[0126] 112 I2C nodes

[0127] 114 Main Controller

[0128] 116 I2C

[0129] 118 Register Map

[0130] 120 Physical Register Mapping

[0131] 122 Memory

[0132] 124 Another memory location

[0133] 126 The host controller reads 1 byte out of N bytes

[0134] 128 Register map ends

[0135] 130 Transmission completed

[0136] 132 Update and / or repopulate physical register map

[0137] 134 Fill and / or update the physical register map 120 with the value of the virtual part

[0138] 136 The host controller reads N bytes

[0139] 138 Special register reached?

[0140] 140 I2C node sends data from physical register map

[0141] 142 I2C node sends data from another memory location

Claims

1. A system (110) comprising at least one integrated circuit interconnect node (I2C node) (112), at least one host controller (114), and at least one integrated circuit interconnect (I2C) (116), wherein: The I2C (116) is configured to transfer data between the I2C node (112) and the host controller (114), wherein the I2C node (112) provides a register map (118), wherein the host controller (114) is configured to read the register map (118) byte by byte, wherein the I2C node (112) is configured to increment the register address after each byte, wherein the register map (118) includes a physical register map (120), wherein the data of the physical register map (120) has a physical address in the physical register map (120). A physical address in a memory of an I2C node (122), wherein the I2C node (112) is configured to generate data having a size greater than the physical register map (120), wherein the register map (118) includes a virtual portion, wherein data in the virtual portion has an address in another memory location (124), wherein the host controller (114) is configured to read the virtual portion by executing a transaction starting from the physical register map (118), wherein a transaction length of the transaction exceeds the size of the physical register map.

2. The system (110) according to the preceding claim, wherein: The I2C node (112) is configured to provide next data by converting between the address in the other memory location (124) and the physical address (122) in the memory when the register address reaches the end of the physical register map (120).

3. The system (110) according to any one of the preceding claims, wherein: When the register address reaches the end of the physical register map (120), the I2C node (112) is configured to fill the physical register map (120) with the value of the virtual portion and reset the physical address back to zero, wherein the process is transparent to the host controller (114).

4. The system (110) according to the preceding claim, wherein: The main controller (114) is configured to read as many values ​​and / or bytes from the virtual portion as required and / or predefined.

5. The system (110) according to any one of the two preceding claims, wherein: This process occurs whenever the address in the other memory location (124) reaches a multiple of the size of the physical register map (120).

6. The system (110) according to any one of the preceding claims, wherein: The I2C node (112) is configured to operate with at least one special register, wherein if the host controller (114) starts reading the special register, the I2C node (112) is configured to provide the data stored in the other memory location (124), wherein the process is transparent to the host controller (114).

7. The system (110) according to any one of the preceding claims, wherein: The other memory location (124) is a memory location where all data is available in a contiguous form.

8. System (110) according to the preceding claim, wherein The I2C node (112) includes at least one sensor, wherein the sensor includes at least one element selected from the group consisting of: at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor with data buffering and automatic data accumulation functions.

9. A mobile device (111) comprising at least one system (110) according to any one of the preceding claims, wherein: The mobile device (111) is at least one element selected from the group consisting of: a notebook computer, a tablet computer, a mobile phone, a smart phone, a smart watch and a wearable computer, wherein the mobile device (111) is configured to use at least one I2C protocol to perform data transmission within the mobile device (111).

10. A method for data transmission between at least one integrated circuit interconnect node (I2C node) (112) and at least one host controller (114), wherein: The method comprises using a system (110) according to any one of the preceding claims relating to a system, wherein the method comprises the following steps: - generating data having a size greater than the physical register map (120) and providing the register map (118) using the I2C node (112); - reading the register map (118) byte by byte using the host controller (114) and incrementing the register address after each byte using the I2C node (112), - using the master controller (114) to read a virtual portion of the register map (118) by executing a transaction starting from the physical register map (120), wherein a transaction length of the transaction exceeds the size of the physical register map.

11. A method according to any one of the preceding method claims, wherein: The method is computer implemented.

12. A computer program comprising instructions which, when executed by a system (110) according to any of the preceding system-related claims, cause the system (110) to perform a method according to any of the preceding method-related claims.

13. A computer-readable storage medium comprising instructions which, when executed by a system (110) according to any one of the preceding system-related claims, cause the system (110) to perform a method according to any one of the preceding method-related claims.

14. A non-transitory computer readable medium comprising instructions which, when executed by one or more processors, cause the one or more processors to perform a method according to any one of the preceding method-related claims.

15. Use of the system (110) according to any of the preceding claims relating to the system for a purpose of use selected from the group consisting of: infrared detection applications; thermal detection applications; thermometer applications; heat seeking applications; flame detection applications; fire detection applications; smoke detection applications; temperature sensing applications; spectroscopy applications; exhaust gas monitoring applications; combustion process monitoring applications; pollution monitoring applications; industrial process monitoring applications; chemical process monitoring applications; food processing process monitoring applications; water quality monitoring applications; air quality monitoring applications; quality control applications; temperature control applications; motion control applications; emission control applications; gas sensing applications; gas analysis applications; motion sensing applications; chemical sensing applications; mobile applications; medical applications; mobile spectroscopy applications; food analysis applications.

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