Flexible dual-arrangement memory system for improved performance

Abstract

Various embodiments include methods for implementing flexible arrangement in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which the first memory access command is implemented in a logical arrangement; generating, by the memory controller, a first signal configured to indicate to the logically arranged first memory device that the first memory access command is implemented via a first partial channel; transmitting the first signal from the memory controller to the first memory device; generating, by the memory controller, a second signal configured to indicate to a second memory device of the logic arrangement, different from the first memory device, that the first memory access command is implemented via a second partial channel; and transmitting the second signal from the memory controller to the second memory device.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 17 / 929,946, filed on September 6, 2022; the entire contents of which are incorporated herein by reference. Background Art

[0003] Next-generation low-power double data rate (LPDDR) memory (e.g., LPDDR6) may offer a balance of high performance, low power, competitive memory cost, various package types, and multi-source availability that is attractive to mobile and non-mobile applications. Summary of the invention

[0004] Various aspects may include apparatus and methods for implementing a flexible dual-arrangement memory system. Aspects may include: receiving a first memory access command at a memory controller and a first address at which the first memory access command is implemented in a logical arrangement; generating a first signal by the memory controller, the first signal being configured to indicate to a first memory device of the logical arrangement that the first memory access command is implemented via a first portion of channels; transmitting the first signal from the memory controller to the first memory device; generating a second signal by the memory controller, the second signal being configured to indicate to a second memory device of the logical arrangement that is different from the first memory device that the first memory access command is implemented via a second portion of channels; and transmitting the second signal from the memory controller to the second memory device.

[0005] Some aspects may also include: generating, by the memory controller, a third signal configured to indicate to the first memory device to activate a component of the first memory device associated with the first portion of the channel; transmitting the third signal from the memory controller to the first memory device; generating, by the memory controller, a fourth signal configured to indicate to the second memory device to activate a component of the first memory device associated with the second portion of the channel; and transmitting the fourth signal from the memory controller to the second memory device.

[0006] Some aspects may also include: determining whether the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement, wherein generating the first signal, transmitting the first signal, generating the second signal, and transmitting the second signal occur in response to determining that the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement.

[0007] Some aspects may also include: receiving a second memory access command at the memory controller and a second address at which the second memory access command is implemented in the arrangement; generating a third signal by the memory controller, the third signal being configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the first portion of channels; transmitting the third signal from the memory controller to the first memory device; generating a fourth signal by the memory controller, the fourth signal being configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the second portion of channels; and transmitting the fourth signal from the memory controller to the first memory device.

[0008] Some aspects may also include determining whether the second address at which the second memory access command is implemented in the arrangement is in a logical arrangement, wherein generating the third signal, transmitting the third signal, generating the fourth signal, and transmitting the fourth signal occur in response to determining that the second address at which the second memory access command is implemented in the arrangement is not in the logical arrangement.

[0009] Some aspects may also include: receiving the first signal at a first partial channel interface of the first memory device for the first partial channel; implementing the first memory access command at the first memory device via the first partial channel; receiving the second signal at a second partial channel interface of the second memory device for the second partial channel; and implementing the second memory access command at the second memory device via the second partial channel.

[0010] In some aspects, implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device may include implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device in parallel.

[0011] Additional aspects may include: receiving a first refresh signal at a first partial channel interface for a first partial channel of a first memory device; receiving a second refresh signal at a second partial channel interface for a second partial channel of a second memory device; implementing a refresh operation at the first memory device via the first partial channel in response to the first refresh signal; and implementing a refresh operation at the second memory device via the second partial channel in response to the second refresh signal.

[0012] In some aspects, the first memory device and the second memory device are logically arranged different memory devices, and implementing the refresh operation at the second memory device can include implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.

[0013] Some aspects may also include: receiving a first signal at the first partial channel interface, the first signal being configured to indicate to the first memory device of the logical arrangement to implement a first memory access command via the first partial channel; receiving a second signal at the second partial channel interface, the second signal being configured to indicate to the second memory device of the logical arrangement to implement a second memory access command via the second partial channel; implementing the first memory access command at the first memory device via the first partial channel after implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device; and implementing the second memory access command at the second memory device via the second partial channel after implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.

[0014] In some aspects, the second memory device is the first memory device.Some aspects may also include: waiting for a specified refresh cycle for the refresh operation at the first memory device, wherein implementing the refresh operation at the second memory device may include implementing the refresh operation at the second memory device after the specified refresh cycle.

[0015] Some aspects may also include: receiving a first signal at the first portion of the channel interface, the first signal being configured to indicate to the first memory device that a first memory access command is implemented via the first portion of the channel; receiving a second signal at the second portion of the channel interface, the second signal being configured to indicate to the second memory device that a second memory access command is implemented via the second portion of the channel; implementing the first memory access command at the first memory device via the first portion of the channel after implementing the refresh operation at the second memory device after the specified refresh cycle; and implementing the second memory access command at the second memory device via the second portion of the channel after implementing the refresh operation at the second memory device after the specified refresh cycle.

[0016] Various aspects include computing devices including a first memory device, a second memory device, and a memory controller communicatively connected to the first memory device and the second memory device and configured to perform the operations of any of the methods outlined above. Various aspects include computing devices having components for performing any of the functions of the methods outlined above. Various aspects include memory controllers configured to perform any of the methods outlined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate example embodiments in various embodiments and, together with the general description given above and the detailed description given below, serve to explain features of the claims.

[0018] Figure 1 is a component block diagram illustrating an example computing device suitable for implementing various embodiments.

[0019] Figure 2 is a component block diagram illustrating an example memory system with partial channels for implementing various embodiments.

[0020] Figure 3 is a component block diagram illustrating an example memory system having a partial channel based arrangement of memory devices for implementing various embodiments.

[0021] Figure 4 is a component block diagram illustrating an example memory system having a logical arrangement structure of partial channels based on multiple memory devices for implementing various embodiments.

[0022] Figure 5A and Figure 5B is a timing diagram illustrating an example of memory access commands of a memory system using an arrangement and a logical arrangement structure according to an embodiment.

[0023] Figure 6 is a block diagram illustrating an example memory space having a partitioned arrangement and a logical arrangement for implementing various embodiments.

[0024] Figure 7 is a process flow diagram illustrating a method for implementing flexible permutations in a memory system according to some embodiments.

[0025] Figure 8 is a process flow diagram illustrating a method for implementing flexible permutations in a memory system according to some embodiments.

[0026] Fig. 9 is a process flow diagram illustrating a method for activating a logical arrangement in a memory system according to some embodiments.

[0027] Fig.10 is a process flow diagram illustrating a method for implementing memory access using a logical arrangement in a memory system according to some embodiments.

[0028] Fig.11 is a process flow diagram illustrating a method for activating a permutation in a memory system according to some embodiments.

[0029] Fig.12is a process flow diagram illustrating a method for implementing memory access using permutations in a memory system according to some embodiments.

[0030] Fig.13 is a process flow diagram illustrating a method for implementing memory access using a logical arrangement in a memory system according to some embodiments.

[0031] Fig.14A and Fig. 14B is a process flow diagram illustrating a method for implementing memory access and refresh using an arrangement or logical arrangement in a memory system according to some embodiments.

[0032] Fig.15 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0033] Fig.16 is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0034] Fig.17 is a component block diagram illustrating an example server suitable for implementing various embodiments. DETAILED DESCRIPTION

[0035] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0036] Various embodiments include circuits, methods, and computing devices that implement such methods for implementing flexible permutations in a memory system. Some embodiments include implementing a logical permutation in a memory system for which the logical permutation can be implemented using partial channels of a memory device and different partial channels of different memory devices. Some embodiments include implementing a logical permutation in a memory system and implementing a permutation in a memory system for which the permutation can be implemented using multiple partial channels of a memory device.

[0037] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of the following: a cellular telephone, a smart phone, a personal or mobile multimedia player, a personal data assistant (PDA), a laptop computer, a tablet computer, a convertible laptop / tablet computer (2-in-1 computer), a smartbook, an ultrabook, a netbook, a palmtop computer, a wireless email receiver, an Internet-enabled multimedia cellular telephone, a mobile game console, a wireless game controller, and similar personal electronic devices that include a memory and a programmable processor. The term "computing device" may further refer to a stationary computing device, including a personal computer, a desktop computer, a stand-alone computer, a workstation, a supercomputer, a mainframe computer, an embedded computer, a server, a home theater computer, and a game console.

[0038] The partial channels implemented for the memory devices impose command timing constraints on accessing the memory devices via the partial channels, such as for the memory devices included in the arrangement of the memory system. Various embodiments solve and overcome the timing constraints on accessing the memory devices via the partial channels in the arrangement of the memory system by implementing a logical arrangement that enables parallel access to multiple memory devices via partial channels. Various embodiments can organize the memory system so that the logical arrangement can include different partial channels of different memory devices, thereby avoiding access conflicts to the same memory device via multiple partial channels of the arrangement. The logical arrangement can be enabled by using a chip select signal generated at a system on chip (SoC) and transmitted to multiple memory devices to enable the use of different partial channels of different memory devices in parallel. In some embodiments, the arrangement can also be implemented in a memory system in which the logical arrangement is implemented.

[0039] By providing a high-performance memory system, some embodiments may be particularly suitable for memory subsystems and memory devices of user devices, mobile computing, automotive, and artificial intelligence systems. Specifically, various embodiments may be implemented using the next generation LPDDR specification (LPDDR6) and associated double data rate memory (DDR) physical layer (PHY) chipsets used in mobile devices or non-mobile computing devices.

[0040] Various embodiments improve the operation of computing devices by improving the functionality of memory devices and memory subsystems by overcoming timing constraints on accessing memory devices via partial channels.

[0041] Figure 1A system including a computing device 10 suitable for use with various embodiments is illustrated. The computing device 10 may include a system on a chip (SoC) 12 having a processor 14, a memory 16, a memory interface 34, a communication interface 18, a storage memory interface 20, a clock controller 30, and an interconnect 32. The computing device 10 may also include a communication component 22 (such as a wired or wireless modem), a storage memory 24, an antenna 26 for establishing a wireless communication link, a power manager 28, and a memory 36. The processor 14 may include any of a variety of processing devices (e.g., multiple processor cores).

[0042] The term "system on chip" (SoC) is used herein to refer to a collection of interconnected electronic circuits, typically but not exclusively including a processing device, a memory, and a communication interface. The processing device may include a variety of different types of processors 14 and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), neural network processing units (NPUs), subsystem processors for specific components of the computing device (such as an image processor for a camera subsystem or a display processor for a display), auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. The processing device may further embody other hardware and hardware combinations, such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and time references. The integrated circuit may be configured so that the components of the integrated circuit reside on a single piece of semiconductor material (such as silicon).

[0043] SoC 12 may include one or more processors 14. Computing device 10 may include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. Computing device 10 may also include processors 14 that are not associated with SoC 12. Processors 14 may each be configured for a specific purpose that may be the same or different from other processors 14 of computing device 10. One or more of processors 14 and processor cores of the same or different configurations may be grouped together. A group of processors 14 or processor cores may be referred to as a multi-processor cluster.

[0044] The computing device 10 may include any number and combination of memories, such as a memory 16 integral to the SoC 12 and a memory 36 separate from the SoC 12. Any of the memories 16, 36 may be volatile or non-volatile memory configured to store data and processor executable code for access by the processor 14. The computing device 10 and / or the SoC 12 may include one or more memories 16, 36 configured for various purposes. The one or more memories 16, 36 may include volatile memory, such as random access memory (RAM) or main memory, including static RAM (SRAM) (such as memory 16), dynamic RAM (DRAM) (such as memory 36), or cache memory.

[0045] The memory 16, 36 may be configured to temporarily store a limited amount of data received from a data sensor or subsystem, data and / or processor executable code instructions requested from the non-volatile memory 16, 24, 36 that are loaded into the memory 16, 36 from the non-volatile memory 16, 24, 36 in anticipation of future access based on a variety of factors, and / or intermediate processing data and / or processor executable code instructions generated by the processor 14 and temporarily stored for future quick access without being stored in the non-volatile memory 16, 24, 36. The memory 16, 36 may be configured to store data and processor executable code in a portion of the memory 16, 36 that is configured to store data and processor executable code for secure computing operations (referred to herein as a secure portion). The memory 16, 36 may be configured to store data and processor executable code in a portion of the memory 16, 36 that is configured to store data and processor executable code for non-secure computing operations (referred to herein as a non-secure portion).

[0046] The memory interface 34 may work in concert with the memory 36 to enable the computing device 10 to store data and processor-executable code on and retrieve data and processor-executable code from the memory 36. The memory interface 34 may control access to the storage memory 36 and allow the processor 14 to read data from and write data to the memory 36.

[0047] The storage memory interface 20 and the storage memory 24 may work in concert to allow the computing device 10 to store data and processor executable code on a non-volatile storage medium. The storage memory 24 may be configured very similarly to the embodiment of the memory 16, where the storage memory 24 may store data or processor executable code for access by one or more of the processors 14. The non-volatile storage memory 24 may retain information after the computing device 10 has been powered off. When power is restored and the computing device 10 restarts, the information stored on the storage memory 24 may be available to the computing device 10. The storage memory interface 20 may control access to the storage memory 24 and allow the processor 14 to read data from and write data to the storage memory 24.

[0048] The power manager 28 may be configured to control the power states of the components of the SoC 12 and / or the power delivery to these components. In some embodiments, the power manager 28 may be configured to signal the power state to the components of the SoC 12 to prompt the components of the SoC 12 to transition to the signaled power state. In some embodiments, the power manager 28 may be configured to control the amount of power provided to the components of the SoC 12. For example, the power manager 28 may be configured to control the connection between the components of the SoC 12 and the power rail (not shown). As another example, the power manager 28 may be configured to control the amount of power on the power rail connected to the components of the SoC 12.

[0049] The clock controller 30 may be configured to control the clock signals sent to the components of the SoC 12. In some embodiments, the clock controller 30 may be configured to signal the clock state (such as gated or non-gated) to the components of the SoC 12 to prompt the components of the SoC 12 to transition to the clock state. For example, the components of the SoC 12 may transition to the gated clock state in response to receiving a gated clock state signal from the clock controller 30 by disconnecting from the clock signal, and may transition to the non-gated clock state in response to receiving a non-gated clock state signal from the clock controller 30 by connecting to the clock signal. In some embodiments, the clock controller 30 may be configured to control the clock signals to the components of the SoC 12. For example, the clock controller 30 may disconnect the components of the SoC 12 from the clock signal to transition the components of the SoC 12 to the gated clock state, and may connect the components of the SoC 12 to the clock signal to transition the components of the SoC 12 to the non-gated clock state.

[0050] Interconnect 32 may be a communication structure, such as a communication bus, configured to communicatively connect components of SoC 12. Interconnect 32 may transmit signals between components of SoC 12. In some embodiments, interconnect 32 may be configured to control signals between components of SoC 12 by controlling the timing and / or transmission paths of the signals.

[0051] Some or all of the components of computing device 10 and / or SoC 12 may be arranged and / or combined differently while still providing the functionality of the various embodiments. Computing device 10 may not be limited to one of each of the components, and multiple instances of each component may be included in various configurations of computing device 10.

[0052] Figure 2 An example memory system 200 with partial channels for implementing various embodiments is illustrated. Figure 1 and Figure 2 , the example memory system 200 may include a plurality of memory devices 212a, 212b (eg, Figure 1 36) of the SoC 202 (e.g., Figure 1 SoC 202 may include a memory controller 206 (eg, Figure 1 200 and the memory interface 34 in the memory physical layer 208 (e.g., Figure 1 Any number and combination of processors 204a, 204b, 204c (e.g., Figure 1 Each memory device 212a, 212b may include a plurality of partial channel interfaces 214a, 214b communicatively connected to at least one memory bank 216a, 216b.

[0053] The processors 204a-204c (e.g., CPU 204a, GPU 204b, NPU 204c) may be configured to execute program instructions (including reading and / or writing to the memory devices 212a, 212b). Memory access commands may be generated and transmitted by the processors 204a-204c to implement read and / or write instructions at the memory devices 212a, 212b.

[0054] The memory controller 206 may receive memory access commands from any number and combination of processors 204a-204c. The memory access command may include information for implementing read and / or write instructions at memory devices 212a, 212b. Such information may include virtual and / or physical addresses of memory devices 212a, 212b at which read and / or write instructions are implemented. The memory controller 206 may identify the addresses of the locations at the memory devices 212a, 212b corresponding to the addresses of the memory access commands and guide the memory access commands to these locations. In some embodiments, the addresses of the locations at the memory devices 212a, 212b may be identified by mapping or converting the addresses of the memory access commands to the addresses of these locations using algorithms and / or mapping tables (such as mapping tables stored at conversion lookaside buffers). The memory controller 206 may transmit memory access commands, addresses of locations at memory devices 212a, 212b, and / or signals for activating components of memory devices 212a, 212b for corresponding locations. In some embodiments, the memory controller 206 may be separate from the processors 204a-204c. In some embodiments, one or more memory controllers 206 may be integral to one or more of the processors 204a-204c.

[0055] The physical layer 208 may receive memory access commands, addresses of locations at the memory devices 212a, 212b, and / or signals for activating components of the memory devices 212a, 212b for the corresponding locations from the memory controller 206. The physical layer 208 may transmit the memory access commands, addresses of locations at the memory devices 212a, 212b, and / or signals for activating components of the memory devices 212a, 212b for the corresponding locations along with other signals via the communication bus. The communication bus may include various sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 228a, 228b, 230 to enable communication between the SoC 202 and the memory devices 212a, 212b. For example, the physical layer 208 can transmit signals for memory access commands, including: data signals via one or more data buses 218a, 218b; data clock signals via one or more data clock lines 220a, 220b; read enable clock signals via one or more read enable clock lines 222a, 222b; memory access command and location address signals via one or more command and address buses 224a, 224b; clock signals via one or more clock lines 226a, 226b; chip select signals via one or more chip select buses 228a, 228b; and / or a reset signal via a reset line 230.

[0056] Depending on the address of the location at the memory devices 212a, 212b, the physical layer 208 may transmit signals via a particular combination of sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 228a, 228b, 230. For example, for a memory access command directed to an address of a location associated with a partial channel 0 of one or more of the memory devices 212a, 212b, such as a location at the memory bank 216a, the physical layer 208 may transmit signals via the sub-buses and lines 218a, 220a, 222a, 224a, 226a, 228a. Similarly, for memory access commands directed to addresses associated with locations associated with a portion of channel 1 of one or more of the memory devices 212a, 212b, such as locations at memory bank 216b, the physical layer 208 may transmit signals via the sub-buses and lines 218b, 220b, 222b, 224b, 226b, 228b.

[0057] The memory devices 212a, 212b may receive signals transmitted by the physical layer 208 via the communication bus. These signals may be received at the partial channel interfaces 214a, 214b of the memory devices 212a, 212b. For example, for a memory access command directed to an address associated with a partial channel 0 of one or more of the memory devices 212a, 212b (such as a location at the memory bank 216a), these signals may be received at the partial channel 0 interface 214a of the memory devices 212a, 212b. Similarly, for a memory access command directed to an address associated with a partial channel 1 of one or more of the memory devices 212a, 212b (such as a location at the memory bank 216b), these signals may be received at the partial channel 1 interface 214b of the memory devices 212a, 212b.

[0058] The partial channel interfaces 214a, 214b may interpret signals and / or transmit signals to one or more memory banks 216a, 216b to which the partial channel interfaces 214a, 214b are communicatively connected. For example, a chip select signal may be interpreted by the partial channel interfaces 214a, 214b and indicate to these partial channel interfaces which of the memory devices 212a, 212b to activate the communicatively connected memory banks 216a, 216b and / or to implement a memory access command at the communicatively connected memory banks 216a, 216b. For example, for a chip select signal received via the chip select bus 228a, different values ​​may indicate to the partial channel 0 interface 214a to activate the memory bank 216a and / or to implement a memory access command at the memory bank 216a of one of the memory devices 212a, 212b. As another example, different values ​​for chip select signals received via chip select bus 228b may indicate to partial channel 1 interface 214b to activate memory bank 216b and / or implement a memory access command at memory bank 216b of one of memory devices 212a, 212b.

[0059] In some embodiments, the address of the location at the memory device 212a, 212b can be within the arrangement of one or more memory devices 212a, 212b. As mentioned herein, the arrangement can include a memory space of multiple memory banks 216a, 216b across a memory device 212a, 212b, wherein at least two memory banks 216a, 216b are associated with different partial channels. For example, for a DDR dual in-line memory module (DIMM), the memory devices 212a, 212b on the opposite sides of the DIMM can be part of different arrangements. In some embodiments, the address of the location at the memory device 212a, 212b can be within the logical arrangement of multiple memory devices 212a, 212b. As mentioned herein, the logical arrangement can include a memory space of multiple memory banks 216a, 216b across multiple memory devices 212a, 212b, wherein the memory banks 216a, 216b of two memory devices 212a, 212b are associated with different partial channels. For example, for a DDR DIMM, memory devices 212a, 212b located on opposite sides of the DIMM can be part of a logical arrangement. In some embodiments, two memory devices 212a, 212b of a logical arrangement can be communicatively connected to the same sub-bus and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 228a, 228b, 230.

[0060] Figure 3 illustrative embodiments of the present invention are provided with a memory-based device (e.g., Figure 1 Memory 36 in Figure 2 An example memory system 300 (eg, Figure 2 Memory system 200 in FIG. Figure 4 illustrative embodiments of the present invention are provided with a memory-based device (e.g., Figure 1 Memory 36 in Figure 2 An example memory system 400 (eg, a memory device 212a, 212b in FIG. 1 ) that includes a logical arrangement of a portion of channels of the memory device 212a, 212b in FIG. Figure 2 Memory system 200 in FIG. Figures 1 to 4 , the memory systems 300, 400 may include memory devices connected to the memory 306a, 306b, 308a, 308b, 310a, 310b, 312a, 312b via various buses and lines (e.g., Figure 2 20a, 20b, 204a, 204b, 204b, 204b, 204b, 204b, 204b, 204b, 204c, 204d ... Figure 2 SoC 202 (eg, Figure 1 SoC 12).

[0061] exist Figure 3 and Figure 4 In the example shown in FIG. 1 , part of the channel interface 302a ( Figure 3 and Figure 4 "Partial Channel Interface 0" in ), 302b( Figure 3 and Figure 4 The "partial channel interface 1" in the example can be the same memory device ( Figure 3 and Figure 4 Partial channel interface 304b ( Figure 3 and Figure 4 "Partial Channel Interface 0") in 304b( Figure 3 and Figure 4 The "partial channel interface 1" in the example may be the same memory device (different from the memory devices of the partial channel interfaces 302a and 302b) Figure 3 and Figure 4 A partial channel interface of "memory device 1" in FIG.

[0062] SoC 202 can communicate with the SoC 202 via data bus 306a (eg, Figure 2 data buses 218a, 218b), command and address buses 308a (e.g., Figure 2 command and address bus 224a, 224b) and one or more chip select lines 310a, 310b (e.g., Figure 2 228a, 228b in the chip select bus 228a, 228b) are communicatively connected to the partial channel interfaces 302a, 304a of different memory devices. Similarly, the SoC 202 can communicate via the data bus 306b (e.g., Figure 2 data buses 218a, 218b), command and address buses 308b (e.g., Figure 2 command and address bus 224a, 224b) and one or more chip select lines 312a, 312b (e.g., Figure 2 228a, 228b in the chip select bus 228a, 228b) are communicatively connected to the partial channel interfaces 302b, 304b of different memory devices. In some embodiments, the SoC 202 can be communicatively connected to each partial channel interface 302a, 302b, 304a, 304b via a separate chip select line 310a, 310b, 312a, 312b. The SoC 202 can be communicatively connected to the partial channel interfaces 302a, 302b, 304a, 304b via other buses and lines, as described in reference Figure 2 For clarity, the Figure 3 are omitted in the examples.

[0063] Using components of SoC 202 (not shown; for example, Figure 2 2, memory controller 206, memory physical layer 208) and / or various buses and lines 306a, 306b, 308a, 308b, 310a, 310b, 312a, 312b in the SoC 202, the SoC 202 can transmit signals for implementing memory access commands to the partial channel interfaces 302a, 302b, 304a, 304b. For example, the SoC 202 can transmit data signals via one or more data buses 306a, 306b and / or transmit memory access commands and address signals via one or more command and address buses 308a, 308b. The SoC 202 can transmit chip select signals via one or more chip select lines 310a, 310b, 312a, 312b to indicate to the partial channel interfaces 302a, 302b, 304a, 304b which memory device components (not shown; for example, Figure 2 The memory storage bodies 216a, 216b) in the memory access command are implemented.

[0064] exist Figure 3 In the example illustrated in , the memory device components controlled by the partial channel interfaces 302a, 302b, 304a, 304b can be organized in the arrangements 314a, 314b. For example, the arrangement 314a can include the memory device components of the memory device 0 controlled by the partial channel interface 0 302a and the partial channel interface 1 302b. The arrangement 314b can include the memory device components of the memory device 1 controlled by the partial channel interface 0 304a and the partial channel interface 1 304b. The SoC 202 can be configured to transmit chip select signals for the memory device components of the arrangements 314a, 314b for memory access commands that target addresses at locations at memory devices within the arrangements 314a, 314b. For example, for a memory access command targeting an address of a location within the arrangement 314a, the SoC 202 may transmit a chip select signal to the partial channel interface 0 302a of the memory device 0 via the chip select line 310a and transmit a chip select signal to the partial channel interface 1 302b of the memory device 0 via the chip select line 312a. For a memory access command targeting an address of a location within the arrangement 314b, the SoC 202 may transmit a chip select signal to the partial channel interface 0 304a of the memory device 1 via the chip select line 310b and transmit a chip select signal to the partial channel interface 1 304b of the memory device 1 via the chip select line 312b.

[0065] The partial channel interfaces 302a, 302b, 304a, 304b that control the memory device components of the arrangement 314a, 314b may receive chip select signals via chip select lines 310a, 310b, 312a, 312b. The chip select signals may be interpreted by the partial channel interfaces 302a, 302b, 304a, 304b to activate and / or implement memory access commands using the memory device components of the arrangement 314a, 314b corresponding to the chip select signals.

[0066] exist Figure 4 In the example illustrated in , the memory device components controlled by the partial channel interfaces 302a, 302b, 304a, 304b may be organized in logical arrangements 402a, 402b. For example, the logical arrangement 402a may include the memory device components of the memory device 0 controlled by the partial channel interface 0 302a and the memory device components of the memory device 1 controlled by the partial channel interface 1 304b. The logical arrangement 402b may include the memory device components of the memory device 1 controlled by the partial channel interface 0 304a and the memory device components of the memory device 0 controlled by the partial channel interface 1 302b.

[0067] SoC 202 may be configured to transmit chip select signals for memory device components of logical arrangements 402a, 402b for memory access commands that target addresses of locations at memory devices within logical arrangements 402a, 402b. For example, for memory access commands that target addresses of locations within logical arrangement 402a, SoC 202 may transmit chip select signals to partial channel interface 0 302a of memory device 0 via chip select line 310a and transmit chip select signals to partial channel interface 1 302b of memory device 1 via chip select line 312b. For memory access commands that target addresses of locations within logical arrangement 402b, SoC 202 may transmit chip select signals to partial channel interface 0 304a of memory device 1 via chip select line 310b and transmit chip select signals to partial channel interface 1 304b of memory device 0 via chip select line 312a.

[0068] The partial channel interfaces 302a, 302b, 304a, 304b that control the memory device components of the logic arrangement 402a, 402b may receive chip select signals via chip select lines 310a, 310b, 312a, 312b. The chip select signals may be interpreted by the partial channel interfaces 302a, 302b, 304a, 304b to activate and / or implement memory access commands using the memory device components of the logic arrangement 402a, 402b corresponding to the chip select signals.

[0069] In some embodiments, the arrangement 314a, 314b and the logic arrangement 402a, 402b can be implemented in the same memory system 300, 400. In some embodiments, transmitting the chip select signal can include asserting the signal via the chip select line 310a, 310b, 312a, 312b. In some embodiments, transmitting the chip select signal can include de-asserting the signal via the chip select line 310a, 310b, 312a, 312b.

[0070] Figure 5A and Figure 5B Illustrated using the arrangement structure and logical arrangement structure memory system (eg, Figures 2 to 4 Examples of memory access commands for memory systems 200, 300, 400 in FIG. Figures 1 to 5B , Figure 5A The example uses the same memory device (e.g., Figure 1 Memory 36 in Figure 2 An example of a memory system in which different portions of channels of the memory devices 212a, 212b in the memory device 212a, 212b are arranged over time to implement memory access commands. Figure 5BThe use of different memory devices (e.g. Figure 1 Memory 36 in Figure 2 An example of a memory system in which different portions of channels of the memory devices 212a, 212b in the memory device 212a, 212b are implemented over time to implement a logical arrangement of memory access commands.

[0071] exist Figure 5A In the example illustrated in , the memory device ( Figure 5A different parts of the channel ("Memory Device 0") in Figure 5A 0 and "Partial Channel 1" in the arrangement (e.g. Figure 3 314a, 314b) in the arrangement 314a, 314b) from a SoC (e.g., Figure 2 and Figure 3 SoC 202 in the memory access command ( Figure 5A Each partial channel may be implemented as a partial channel interface for the arranged partial channels (e.g., Figure 2 and Figure 3 214a, 214b, 302a, 302b, 304a, 304b) in the memory device. However, multiple partial channels of the same memory device have certain command timing constraints based on memory design and power distribution network limitations. For example, within the arrangement, the memory device components (e.g., Figure 2 The refresh operation ( Figure 5A The "ref" in the Figure 5A The refresh operation is performed for a memory device component of another partial channel of the same memory device, during which the memory device cannot perform another refresh operation for a memory device component of another partial channel of the same memory device. For example, when a refresh operation is performed for a memory device component of partial channel 0, a refresh operation cannot be performed for a memory device component of partial channel 1 until the period tRFC has elapsed. Multiple refresh operations for memory device components of different partial channels of the same memory device or within an arrangement are forced to be performed sequentially following the timing constraints.

[0072] exist Figure 5B In the example illustrated in , different memory devices ( Figure 5B different parts of the channels ("Memory Device 0" and "Memory Device 1") in Figure 5B 0 and 1) can be used in a logical arrangement (e.g. Figure 4 402a, 402b) in the logical arrangement 402a, 402b) from the SoC (e.g., Figure 2 and Figure 3SoC 202 in the memory access command ( Figure 5B Each partial channel may implement a partial channel interface such as a partial channel within a logical arrangement (e.g., Figure 2 and Figure 3 Memory access commands controlled by some channel interfaces 214a, 214b, 302a, 302b, 304a, 304b).

[0073] Use different parts of the channels of different memory devices. Use different parts of the channels of the same memory device to avoid Figure 5A The example memory design and power distribution network constraints illustrated in FIG. 4 are command timing constraints. For example, within a logical arrangement, a memory device component (e.g., Figure 2 The refresh operation ( Figure 5B ref in the figure), another refresh operation of the memory device components of another partial channel of another memory device can be implemented in parallel. For example, when the refresh operation is implemented for the memory device components of the partial channel 0 of the memory device 0, the refresh operation can be implemented for the memory device components of the partial channel 1 of the memory device 1.

[0074] Multiple refresh operations targeting different memory device components or within a logical arrangement in different partial channels can be performed without Figure 5A Thus, the logical arrangement (such as in Figure 5B In the example illustrated in ), can provide a performance improvement over implementing an arrangement, for example in terms of memory access speed.

[0075] Figure 6 Examples of methods for implementing various embodiments with targeted arrangements (e.g., Figure 3 314a, 314b) and logical arrangements (e.g., Figure 4 Example memory space 600 of a partition of a logical arrangement 402a, 402b in FIG. Figures 1 to 6 , the memory space 600 may include one or more memory devices (e.g., Figure 1 Memory 36 in Figure 2 212a, 212b) in the memory devices 212a, 212b, and includes memory space for one or more arrangements and / or logical arrangements. The allocation of storage space 600 for arrangements and logical arrangements can be in any proportion. The proportion can be based on the computing device (e.g., Figure 1The memory space 600 may be allocated to a logical arrangement greater than the allocation to an arrangement in view of the performance benefits of a logical arrangement over an arrangement.

[0076] In some embodiments, memory space 600 may be allocated only to logical permutations. The ability to use both permutations and logical permutations may achieve power efficiency benefits over using logical permutations alone because memory devices that are not part of the permutation that is the target of a memory access command may be placed in a low power state when permutations are used.

[0077] The allocation of memory space 600 for logical arrangements may be distributed across multiple memory devices. For example, the allocation of memory space 600 for logical arrangements may include Figure 6 The memory space of memory device 0 and memory device 1 in the example illustrated in FIG. The allocation of memory space 600 for the arrangement can be constrained to a single memory device. For example, in Figure 6 In the example illustrated in , an allocation of memory space 600 for an arrangement may include memory space of memory device 0 , and an allocation of memory space 600 for another arrangement may include memory space of memory device 1 .

[0078] Figure 7 Methods for implementing flexible permutations in a memory system according to some embodiments are illustrated. Figures 1 to 7 , method 700 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 2 The memory controller 206 and the memory physical layer 208 in the Figures 1 to 4 The method 700 may be implemented in a SoC 12, 202 in a processor (e.g., a processor that executes software and various memory / cache controllers within a flexible memory arrangement control system including other separate components). To encompass alternative configurations implemented in various embodiments, the hardware implementing the method 700 is referred to herein as a "flexible arrangement controller."

[0079] In block 702, the flexible permutation controller may receive a memory access command. The memory access command may originate from a processor (e.g., Figure 1 and Figure 214, 204a-204c) in the client software executed on the processor, which may need to access the memory (e.g., Figure 1 Memory 36 in Figure 2 The memory device 212a, 212b) in the memory access command is accessed to implement the instruction. The received memory access command may include an address at the memory for implementing the memory access command. Figure 8 Receiving a memory access command is further described in method 800. In some embodiments, the flexible permutation controller that receives the memory access command in block 702 may be a memory controller (e.g., Figure 2 206 in the memory controller) and / or the SoC (e.g., Figures 1 to 4 SoC 12, 202).

[0080] In optional decision block 704, the flexible arrangement controller may determine whether the address at which the memory access command is implemented is within the logical arrangement of the memory (eg, Figure 4 In some embodiments, the flexible arrangement controller may use at least a portion of the address to determine whether the address is within the logical arrangement based on a mapping of the portion of the logical address to the logical arrangement. For example, at least a portion of the address may be directly mapped to the logical arrangement. As another example, at least a portion of the address may be within the range of values ​​mapped to the logical arrangement. As another example, at least a portion of the address may be mapped to a portion of the channels of the memory and the portion of the channels may be mapped to the logical arrangement. In some examples, the flexible arrangement controller that determines in optional block 704 whether the address at which the memory access command is implemented is within the logical arrangement of the memory may be a memory controller and / or a SoC.

[0081] After receiving the memory access command in block 702, or in response to determining that the address at which the memory access command is implemented is within the logical arrangement of memories (i.e., optional block 704 = "Yes"), the flexible arrangement controller may activate components of different partial channels of different memories of the logical arrangement in block 706 (e.g., Figure 2 Memory banks 216a, 216b) in FIG. Fig. 9 Further described in method 900. In some embodiments, the flexible arrangement controller of the components that activate different partial channels of different logically arranged memories in block 706 can be a memory controller, a SoC, and / or a memory physical layer (e.g., Figure 2 Memory physical layer 208 in.

[0082] In block 708, the flexible arrangement controller may implement memory access via different partial channels of different memories arranged in a logical manner, as described with reference to FIG. Fig.10Further described in method 1000. In some embodiments, the flexible arrangement controller that implements memory access via different partial channels of different logically arranged memories in block 708 can be a memory controller, a SoC, and / or a memory physical layer (e.g., Figure 2 Memory physical layer 208 in.

[0083] In response to determining that the address at which the memory access command is implemented is not within the logical arrangement of the memory (ie, option block 704 = "No"), the flexible arrangement controller may activate the arrangement in option block 710 (eg, Figure 3 Components of different partial channels of the same memory (e.g., Figure 2 Memory banks 216a, 216b) in FIG. Fig.11 Further described in method 1100. In some embodiments, the flexible permutation controller that activates components of different partial channels of the same memory permutation in block 710 may be a memory controller, a SoC, and / or a memory physical layer.

[0084] In optional block 712, the flexible permutation controller may implement memory access via different partial channels of the same memory permutation, as described with reference to FIG. Fig.12 Further described in method 1200. In some embodiments, the flexible permutation controller that implements memory access via different partial channels of the same memory permutation in block 712 may be a memory controller, SoC, and / or memory physical layer (e.g., Figure 2 Memory physical layer 208 in.

[0085] Figure 8 Methods for implementing flexible permutations in a memory system according to some embodiments are illustrated. Figures 1 to 8 , the method 800 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 2 The memory controller 206 and the memory physical layer 208 in the Figures 1 to 4The method 800 may be implemented in a SoC 12, 202 in a processor configured in software and a combination of dedicated hardware (such as a processor executing software and various memory / cache controllers within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing the method 800 is referred to herein as a "flexible arrangement controller". The method 800 includes a plurality of processors configured in software and various memory / cache controllers that execute software within a flexible memory arrangement control system including other separate components. Figure 7 Operations performed as part of receiving a memory access command in block 702 of method 700 are described.

[0086] In block 802, a flexible permutation controller may receive a memory access command and a memory (eg, Figure 1 Memory 36 in Figure 2 The memory access command may originate from a processor (e.g., Figure 1 and Figure 2 The client software may be executed on a processor 14, 204a-204c in the processor, which may need to access the memory to implement the instruction. The client software may issue a memory access command for a virtual address of the virtual memory, which virtual address may be converted to a physical address of the memory by, for example, a virtual memory management unit implemented on the processor and provided to the flexible arrangement controller. The memory access command and the physical address may be accessed via a cache (e.g., Figure 1 In some embodiments, the flexible permutation controller that receives the memory access command and the physical address of the memory at which the memory access command is implemented in block 802 may be a memory controller (e.g., Figure 2 206 in the memory controller) and / or the SoC (e.g., Figures 1 to 4 SoC 12, 202).

[0087] In block 804, the flexible permutation controller may perform an error check on the physical address to determine whether the physical address is within the range of the memory. The flexible permutation controller may use a known error checking mechanism to determine whether the physical address is within the range of the memory. In some embodiments, the flexible permutation controller that performs an error check on the physical address to determine whether the physical address is within the range of the memory in block 804 may be a memory controller and / or a SoC.

[0088] In block 806, the flexible permutation controller may interpret the physical address of the location in the memory for implementing the memory access command. The flexible permutation controller may parse portions of the physical address to extract bits indicating a row, column, bank, partial channel, and / or permutation of the memory based on the bit positions of the physical address data (e.g., Figure 3 314a, 314b in the arrangement 314a, 314b). For example, one or more least significant bits of the physical address can indicate a column address. As another example, one or more most significant bits of the physical address can indicate an arrangement and / or logical arrangement of the memory. Similarly, another specified bit of the physical address can indicate a partial channel of the memory. Values ​​such as binary values ​​at any one or more specified bit positions can indicate various aspects of the row, column, memory bank, partial channel, and / or arrangement to the flexible arrangement controller. In some embodiments, the flexible arrangement controller that interprets the physical address of a location in the memory for implementing the memory access command in block 806 can be a memory controller and / or SoC.

[0089] In block 808, a flexible arrangement controller may decode the arrangement and partial channels of the physical address of the location in the memory for implementing the memory access command. The flexible arrangement controller may read the arrangement and partial channels from the physical address of the memory at which the memory access command is implemented. When the use of the logical arrangement is enabled, the flexible arrangement controller may map the arrangement and partial channels to the logical arrangement and partial channels at which the memory access command is implemented. For example, the bit value of the physical address indicates: the first arrangement and the first partial channel may be mapped to the first arrangement and the first partial channel; the second arrangement and the second partial channel may be mapped to the first arrangement and the second partial channel; the first arrangement and the second partial channel may be mapped to the second arrangement and the second partial channel; and the second arrangement and the first partial channel may be mapped to the second arrangement and the first partial channel. The flexible arrangement controller may map the arrangement and partial channels to the logical arrangement and partial channels at which the memory access command is implemented by manipulating the bit value of the physical address indicating the arrangement and partial channels. In some embodiments, the flexible arrangement controller that decodes the arrangement and partial channels of the physical address of the location in the memory for implementing the memory access command in block 808 may be a memory controller and / or a SoC.

[0090] Fig. 9 A method for activating a logical arrangement in a memory system according to some embodiments is illustrated. Figures 1 to 9 , method 900 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 2 The memory controller 206 and the memory physical layer 208 in the Figures 1 to 4The method 900 may be implemented in a SoC 12, 202 in a processor configured in software and a combination of dedicated hardware (such as a processor executing software and various memory / cache controllers within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing the method 900 is referred to herein as a "flexible arrangement controller". The method 900 includes a method that may be used as a reference herein. Figure 7 The method 700 described above activates the logical arrangement (e.g., Figure 4 logically arranged in 402a, 402b) of different memories (e.g., Figure 1 Memory 36 in, Figure 2 Components of different portions of a channel of a memory device 212a, 212b in FIG. Figure 2 Operations performed on portions of the memory storage bodies 216a, 216b).

[0091] In block 902, the flexible arrangement controller may generate signals for activating a first portion of channels of a first memory of a logical arrangement and a second portion of channels of a second memory of a logical arrangement. The flexible arrangement controller may generate signals, including chip select signals, configured to indicate to the first memory and the second memory to activate components associated with the first portion of channels and the second portion of channels. The first signal may be transmitted to the first portion of channels interface (e.g., Figure 2 and Figure 4 The second signal may be sent to a second partial channel interface (eg, Figure 2 and Figure 4 The flexible arrangement controller can be based on the reference Figure 8 In some embodiments, the flexible arrangement controller that generates the signal for activating the first portion of the channels of the first logically arranged memory and the second portion of the channels of the second logically arranged memory in block 902 may be a memory controller (e.g., Figure 2 206 in the memory controller), the memory physical layer (e.g., Figure 2 208) and / or SoC (e.g., Figures 1 to 4 SoC 12, 202).

[0092] In block 904, the flexible arrangement controller may transmit a signal for activating a first portion of channels of a first logically arranged memory and a second portion of channels of a second logically arranged memory. The flexible arrangement controller may transmit a signal for activating a first portion of channels of a first logically arranged memory and a second portion of channels of a second logically arranged memory via a chip select line (e.g., Figure 2 The chip select bus 228a, 228b in Figure 3 and Figure 4 The chip select lines 310a, 310b, 312a, 312b in block 904 transmit signals including chip select signals to the first memory and the second memory. The chip select lines may be communicatively connected to the first portion of the channel interface of the first memory and may carry the first signal. The chip select lines may be communicatively connected to the second portion of the channel interface of the second memory and may carry the second signal. In some embodiments, the flexible arrangement controller that transmits signals for activating the first portion of the channels of the logically arranged first memory and the second portion of the channels of the logically arranged second memory in block 904 may be a memory controller, a memory physical layer, and / or a SoC.

[0093] Fig.10 Methods for implementing memory access using a logical arrangement in a memory system according to some embodiments are illustrated. Figures 1 to 10 , method 1000 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 2 The memory controller 206 and the memory physical layer 208 in the Figures 1 to 4 The method 1000 may be implemented in a SoC 12, 202 in a processor configured in software and a combination of dedicated hardware (such as a processor executing software and various memory / cache controllers within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing the method 1000 is referred to herein as a "flexible arrangement controller". The method 1000 includes a plurality of processors configured in software and various memory / cache controllers that execute software within a flexible memory arrangement control system including other separate components. Figure 7 The method 700 described in block 708 is arranged by logic (e.g., Figure 4 logically arranged in 402a, 402b) of different memories (e.g., Figure 1 Memory 36 in Figure 2 Operations performed on portions of memory accesses implemented by different portions of channels of the memory devices 212a, 212b in the memory device 212a, 212b.

[0094] In block 1002, a flexible arrangement controller may generate signals for memory access at a first portion of channels of a first memory of a logical arrangement and at a second portion of channels of a second memory of a logical arrangement. The flexible arrangement controller may generate signals, including command and address signals, data signals, etc., configured to indicate to the first memory and the second memory that memory access is implemented at components associated with the first portion of channels and the second portion of channels. The first signal may be transmitted to the first portion of channels interface (e.g., Figure 2 and Figure 4 The partial channel interface 214a, 214b, 302a, 302b, 304a, 304b in the first partial channel indicates that the memory access is implemented at the component associated with the first partial channel. The second signal can be sent to the second partial channel interface of the second memory (for example, Figure 2 and Figure 4 The partial channel interface 214a, 214b, 302a, 302b, 304a, 304b in the embodiment indicates that the memory access is implemented at the component associated with the second partial channel. The flexible arrangement controller can be based on the reference Figure 8 In some embodiments, the flexible arrangement controller that generates the signals for memory access at a first portion of the channels of the first logically arranged memory and at a second portion of the channels of the second logically arranged memory in block 1002 may be a memory controller (e.g., Figure 2 206 in the memory controller), the memory physical layer (e.g., Figure 2 208) and / or SoC (e.g., Figures 1 to 4 SoC 12, 202).

[0095] In block 1004, the flexible permutation controller may transmit signals for memory access at a first portion of channels of a first logically permuted memory and at a second portion of channels of a second logically permuted memory. The flexible permutation controller may communicate via a communication bus (e.g., Figure 2 The sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 230 in Figure 3 and Figure 4The bus and lines 306a, 306b, 308a, 308b in block 1004 transmit signals including command and address signals, data signals, etc. to the first memory and the second memory. The bus can be communicatively connected to the first portion of the channel interface of the first memory and can carry the first signal. The bus can be communicatively connected to the second portion of the channel interface of the second memory and can carry the second signal. In some embodiments, the flexible arrangement controller that transmits signals for memory access at the first portion of the channels of the logically arranged first memory and at the second portion of the channels of the logically arranged second memory in block 1004 can be a memory controller, a memory physical layer, and / or a SoC.

[0096] Fig.11 A method for activating a permutation in a memory system according to some embodiments is illustrated. Figures 1 to 11 , the method 1100 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 2 The memory controller 206 and the memory physical layer 208 in the Figures 1 to 4 12, 202), or in a combination of a software-configured processor and dedicated hardware (such as a processor and various memory / cache controllers executing software within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing method 1100 is referred to herein as a "flexible arrangement controller." Method 1100 includes a method that can be used as a reference herein. Figure 7 The method 700 described above activates the arrangement (e.g., Figure 3 314a, 314b) of the same memory (e.g., Figure 1 Memory 36 in, Figure 2 Components of different portions of a channel of a memory device 212a, 212b in FIG. Figure 2 Operations performed on portions of the memory storage bodies 216a, 216b).

[0097] In block 1102, a flexible permutation controller may generate signals for activating a first portion of channels of a permuted memory and a second portion of channels of the same permuted memory. The flexible permutation controller may generate signals, including chip select signals, configured to indicate to the memory to activate components associated with the first portion of channels and the second portion of channels. The first signal may be transmitted to the first portion of channels interface (e.g., Figure 2 and Figure 3 The second signal may be sent to a second partial channel interface (e.g., Figure 2 and Figure 3 The flexible arrangement controller can be based on the reference Figure 8 In some embodiments, the flexible permutation controller that generates the signal for activating a first portion of channels of a permuted memory and a second portion of channels of the same permuted memory in block 1102 may be a memory controller (e.g., Figure 2 206 in the memory controller), the memory physical layer (e.g., Figure 2 208) and / or SoC (e.g., Figures 1 to 4 SoC 12, 202).

[0098] In block 1104, the flexible permutation controller may transmit a signal for activating a first portion of channels of a permuted memory and a second portion of channels of the same permuted memory. The flexible permutation controller may transmit a signal for activating a first portion of channels of a permuted memory and a second portion of channels of the same permuted memory via a chip select line (e.g., Figure 2 The chip select bus 228a, 228b in Figure 3 and Figure 4 The chip select lines 310a, 310b, 312a, 312b in block 1104 transmit signals including chip select signals to the memory. The chip select lines may be communicatively connected to a first portion of channel interfaces of the memory and may carry a first signal. The chip select lines may be communicatively connected to a second portion of channel interfaces of the same memory and may carry a second signal. In some embodiments, the flexible arrangement controller that transmits signals for activating a first portion of channels of the arranged memory and a second portion of channels of the same arranged memory in block 1104 may be a memory controller, a memory physical layer, and / or a SoC.

[0099] Fig.12Methods for implementing memory access using permutations in a memory system according to some embodiments are illustrated. Figures 1 to 12 , the method 1200 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 2 The memory controller 206 and the memory physical layer 208 in the Figures 1 to 4 12, 202), or in a combination of a software-configured processor and dedicated hardware (such as a processor and various memory / cache controllers executing software within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing method 1200 is referred to herein as a "flexible arrangement controller." Method 1200 includes a method that can be used as a reference herein. Figure 7 The method 700 described in block 712 is performed by arranging (e.g., Figure 3 314a, 314b) of the same memory (e.g., Figure 1 Memory 36 in Figure 2 Operations performed on portions of memory accesses implemented by different portions of channels of the memory devices 212a, 212b in the memory device 212a, 212b.

[0100] In block 1202, a flexible permutation controller may generate signals for memory access at a first portion of channels of a permuted memory and at a second portion of channels of the same permuted memory. The flexible permutation controller may generate signals, including command and address signals, data signals, etc., configured to indicate to the memory that memory access is implemented at components associated with the first portion of channels and the second portion of channels. The first signal may be provided to the first portion of channels interface (e.g., Figure 2 and Figure 3 The first signal may be sent to a second partial channel interface (e.g., Figure 2 and Figure 3 The partial channel interface 214a, 214b, 302a, 302b, 304a, 304b in the embodiment indicates that the memory access is implemented at the component associated with the second partial channel. The flexible arrangement controller can be based on the reference Figure 8The flexible permutation controller that generates the signals for memory access at a first portion of channels of a permuted memory and at a second portion of channels of the same permuted memory in block 1202 may be a memory controller (e.g., Figure 2 206 in the memory controller), the memory physical layer (e.g., Figure 2 208) and / or SoC (e.g., Figures 1 to 4 SoC 12, 202).

[0101] In block 1204, the flexible permutation controller may transmit signals for memory access at a first portion of channels of a permuted memory and at a second portion of channels of the same permuted memory. The flexible permutation controller may communicate via a communication bus (e.g., Figure 2 The sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 230 in Figure 3 and Figure 4 The bus and lines 306a, 306b, 308a, 308b in block 1204 transmit signals including command and address signals, data signals, etc. to the memory. The bus can be communicatively connected to a first portion of the channel interface of the memory and can carry the first signal. The bus can be communicatively connected to a second portion of the channel interface of the same memory and can carry the second signal. In some embodiments, the flexible permutation controller that transmits signals for memory access at a first portion of the channels of the permuted memory and at a second portion of the channels of the same permuted memory in block 1204 can be a memory controller, a memory physical layer, and / or a SoC.

[0102] Fig.13 Methods for implementing memory access using a logical arrangement in a memory system according to some embodiments are illustrated. Figures 1 to 13 , the method 1300 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 1 Memory 36 in Figure 2 The memory devices 212a, 212b, Figures 2 to 4The method 1300 may be implemented in a portion of the channel interfaces 214a, 214b, 302a, 302b, 304a, 304b in the embodiment of the present invention, or in a combination of a software configured processor and dedicated hardware (such as a processor and various memory / cache controllers executing software within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing the method 1300 is referred to herein as a "flexible arrangement memory device".

[0103] In some embodiments, blocks 1304, 1306, 1308, 1310 may be performed in a first memory device 1302a (e.g., Figure 2 212a, 212b), and blocks 1312, 1314, 1316, 1318 may be implemented at a second memory device 1302b (e.g., Figure 2 The blocks 1304, 1306, 1308, 1310 implemented at the first memory device 1302a may be implemented in parallel with the blocks 1312, 1314, 1316, 1318 implemented at the second memory device 1302b.

[0104] In block 1304, the flexible permutation memory device may receive a signal for activating a logical permutation (eg, Figure 4 The first memory (e.g., Figure 2 The flexible memory device may receive signals including chip select signals configured to indicate to the flexible memory device to activate components associated with the first portion of channels (e.g., Figure 2 The first signal may be transmitted to a first portion of a channel interface of a first memory (eg, Figure 2 and Figure 4 The flexible memory device can be connected via a chip select line (e.g., Figure 2 The chip select bus 228a, 228b in Figure 3 and Figure 4 The chip select lines 310a, 310b, 312a, 312b in the block 1304 receive signals. The chip select lines may be communicatively connected to the first portion of the channel interface of the first memory and may carry the first signal. In some embodiments, the flexible arrangement memory device that receives the signal for activating the first portion of the channels of the logically arranged first memory in block 1304 may be the first memory device 1302a and / or the first portion of the channel interface.

[0105] In block 1306, the flexible arrangement memory device may activate a first portion of channels of the first memory of the logical arrangement. Activating the first portion of channels may include transitioning a component associated with the first portion of channels from a low power state to an active state by a known method. In some embodiments, the flexible arrangement memory device that activates the first portion of channels of the first memory of the logical arrangement in block 1306 may be the first memory device 1302a and / or the first portion of channels interface.

[0106] In block 1308, the flexible permutation memory device may receive a signal for memory access at a first portion of channels of a first memory of a logical permutation. The flexible permutation memory device may receive a signal, including command and address signals, data signals, etc., configured to indicate to the first memory that memory access is to be implemented at a component associated with the first portion of channels. The first signal may indicate to the first portion of channels interface of the first memory that memory access is to be implemented at a component associated with the first portion of channels. The flexible permutation memory device may communicate to the first memory via a communication bus (e.g., Figure 2 The sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 230 in Figure 3 and Figure 4 The bus and lines 306a, 306b, 308a, 308b in block 1308 receive the signal. The bus can be communicatively connected to the first portion of the channel interface of the first memory and can carry the first signal. In some embodiments, the flexible arrangement memory device that receives the signal for memory access at the first portion of the channels of the logically arranged first memory in block 1308 can be the first memory device 1302a and / or the first portion of the channel interface.

[0107] In block 1310, the flexible permutation memory device may implement memory access at a first portion of channels of a first logically permuted memory. Implementing memory access at the first portion of channels may include known methods for reading from and / or writing to components associated with the first portion of channels. In some embodiments, the flexible permutation memory device implementing memory access at the first portion of channels of the first logically permuted memory in block 1310 may be the first memory device 1302a and / or the first portion of channels interface.

[0108] In block 1312, the flexible permutation memory device may receive a signal for activating a logical permutation (eg, Figure 4 The second memory (e.g., Figure 2The flexible memory device may receive signals, including chip select signals, configured to indicate to the flexible memory device to activate components associated with the second portion of the channels (e.g., Figure 2 The second signal may be transmitted to a second portion of a channel interface of a second memory (eg, Figure 2 and Figure 4 The flexible memory device can be connected via a chip select line (e.g., Figure 2 The chip select bus 228a, 228b in Figure 3 and Figure 4 The chip select lines 310a, 310b, 312a, 312b in block 1312 may receive a signal. The chip select lines may be communicatively connected to the second portion of the channel interface of the second memory and may carry the second signal. In some embodiments, the flexible arrangement memory device that receives the signal for activating the second portion of the channels of the logically arranged second memory in block 1312 may be the second memory device 1302b and / or the second portion of the channel interface.

[0109] In block 1314, the flexible arrangement memory device may activate the second portion of the channels of the second logically arranged memory. Activating the second portion of the channels may include transitioning a component associated with the second portion of the channels from a low power state to an active state by a known method. In some embodiments, the flexible arrangement memory device that activates the second portion of the channels of the second logically arranged memory in block 1314 may be the second memory device 1302b and / or the second portion of the channels interface.

[0110] In block 1316, the flexible memory device may receive a signal for memory access at a second portion of the channels of the second memory for logical arrangement. The flexible memory device may receive signals, including command and address signals, data signals, etc., which are configured to indicate to the second memory that memory access is implemented at a component associated with the second portion of the channels. The second signal may indicate to the second portion of the channel interface of the second memory that memory access is implemented at a component associated with the second portion of the channels. The flexible memory device may receive the signal via a communication bus. The bus may be communicatively connected to the second portion of the channel interface of the second memory and may carry the second signal. In some embodiments, the flexible memory device that receives the signal for memory access at the second portion of the channels of the second memory for logical arrangement in block 1316 may be the second memory device 1302b and / or the second portion of the channel interface.

[0111] In block 1318, the flexible memory device may implement memory access at the second portion of channels of the second logically arranged memory. Implementing memory access at the second portion of channels may include known methods for reading from and / or writing to components associated with the second portion of channels. In some embodiments, the flexible memory device that implements memory access at the second portion of channels of the second logically arranged memory in block 1318 may be the second memory device 1302b and / or the second portion of channels interface.

[0112] Fig.14A and Fig. 14B Methods for implementing memory access and refresh using an arrangement or logical arrangement in a memory system according to some embodiments are illustrated. Figures 1 to 14B , methods 1400a, 1400b may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and Figure 2 In software executed in processors 14, 204a-204c in the processors 14, 204a-204c), in general-purpose hardware, in dedicated hardware (e.g., Figures 2 to 4 The memory systems 200, 300, 400, Figure 1 Memory 36 in Figure 2 The memory devices 212a, 212b, Figures 2 to 4 The method 1400a, 1400b may be implemented in a portion of the channel interfaces 214a, 214b, 302a, 302b, 304a, 304b in the embodiment of the present invention, or in a combination of a software configured processor and dedicated hardware (such as a processor and various memory / cache controllers executing software within a flexible memory arrangement control system including other separate components). To cover alternative configurations implemented in various embodiments, the hardware implementing the method 1400a, 1400b is referred to herein as a "flexible arrangement memory device".

[0113] In some embodiments, blocks 1402, 1404, 1406, 1408, 1410, 1412 of method 1400a may be implemented in a single, identical memory device (e.g., Figure 2 212a, 212b), and blocks 1420, 1422, 1424, 1426 of method 1400b may be implemented at multiple different memory devices (e.g., Figure 2 The method is implemented at the memory devices 212a, 212b in the embodiment.

[0114] refer to Fig.14A In block 1402, a flexible permutation memory device may receive a memory device for permutation (eg, Figure 3314a, 314b) of the same memory (e.g., Figure 2 The flexible arrangement memory device can receive signals, including command and address signals, data signals, etc., which are configured to enable the same memory to implement memory access at components associated with different partial channels of the same memory. The first signal can be configured to enable a first partial channel interface (e.g., Figures 2 to 4 The partial channel interface 214a, 214b, 302a, 302b, 304a, 304b) in the same memory implements memory access at a component associated with a first partial channel of the same memory. The second signal can be configured to enable a second partial channel interface of the same memory (e.g., Figures 2 to 4 The memory access is implemented at a component associated with a second portion of the channels of the same memory by a portion of the channel interfaces 214a, 214b, 302a, 302b, 304a, 304b) in the same memory. The flexible arrangement memory device can be connected via a communication bus (e.g., Figure 2 The sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 230 in Figure 3 and Figure 4 The bus may be communicatively connected to a first partial channel interface of the same memory and may carry a first signal, and may be communicatively connected to a second partial channel interface of the same memory and may carry a second signal. In some embodiments, the flexible permutation memory device that receives the signal for memory access at different partial channels of the same memory in block 1402 may be the same memory device, the first partial channel interface, and / or the second partial channel interface.

[0115] In block 1404, the flexible permutation memory device may implement memory access at different partial channels of the same memory of the permutation. Implementing memory access at the first partial channel and the second partial channel may include known mechanisms for reading from and / or writing to components associated with the first partial channel and the second partial channel. In some embodiments, the flexible permutation memory device implementing memory access at different partial channels of the same memory of the permutation in block 1404 may be the same memory device, the first partial channel interface, and / or the second partial channel interface.

[0116] In block 1406, the flexibly arranged memory device may receive signals for refresh execution at different partial channels of the same memory of the arrangement. The flexibly arranged memory device may receive signals, including refresh signals, configured to cause the same memory to implement refresh operations at components associated with different partial channels of the same memory. The first refresh signal may be configured to cause a first partial channel interface of the same memory to implement refresh operations at components associated with the first partial channel of the same memory. The second refresh signal may be configured to cause a second partial channel interface of the same memory to implement memory access at components associated with the second partial channel of the same memory. The flexibly arranged memory device may receive signals via a communication bus. The bus may be communicatively connected to the first partial channel interface of the same memory and may carry the first refresh signal, and may be communicatively connected to the second partial channel interface of the same memory and may carry the second refresh signal. The signals may be transmitted by a memory control device (e.g., a memory control device) communicatively connected to the bus. Figure 2 In some embodiments, the flexible arrangement memory device receiving the refresh execution signal at different partial channels of the same memory arrangement in block 1406 can be the same memory device, the first partial channel interface and / or the second partial channel interface.

[0117] In box 1408, the flexible arrangement memory device can implement a refresh operation at the first partial channel of the same memory of the arrangement. The resources of the flexible arrangement memory device for implementing the refresh operation can be used at a limited number of partial channels (such as as few as a single partial channel) of the same memory at one time. The flexible arrangement memory device can be preconfigured with a mechanism for implementing the refresh operation in the order of the partial channels, which can be static or dynamic based on one or more factors. For example, the flexible arrangement memory device can implement a refresh operation at the first partial channel before the second partial channel of the same memory of the arrangement. In some embodiments, the flexible arrangement memory device that implements the refresh operation at the first partial channel of the same memory of the arrangement in box 1408 can be the same memory device and / or the first partial channel interface.

[0118] In block 1410, the flexible memory device may wait for a specified refresh cycle (eg, Figure 5AtRFC in ). Multiple partial channels of the same memory may have certain command timing constraints based on memory design and power distribution network limitations. For example, within an arrangement, executing a refresh operation of a memory component of a first partial channel of the same memory may impose a timing constraint during which the same memory may not implement another refresh operation of a memory component of another partial channel of the same memory (such as a second partial channel). The specified period may be a period expressed in terms of any of a variety of events, such as time, execution of an operation, receipt of a signal, etc. In some embodiments, the flexible arrangement memory device waiting for a specified refresh period for a refresh implementation in block 1410 may be the same memory device and / or the second partial channel interface.

[0119] In box 1412, the flexible arrangement memory device can implement a refresh operation at the second portion of the channels of the same memory of the arrangement. Implementing the refresh operation at the second portion of the channels of the same memory of the arrangement can occur after waiting for the specified refresh cycle for the specific implementation of the refresh in box 1410. Therefore, implementing the refresh operation at the first portion of the channels of the same memory of the arrangement in box 1408 can be completed during the specified refresh cycle, thereby releasing the resources of the flexible arrangement memory device for implementing the refresh operation. The flexible arrangement memory device can implement the refresh operation at the second portion of the channels of the same memory of the arrangement sequentially with implementing the refresh operation at the first portion of the channels of the same memory of the arrangement in box 1408. In some embodiments, the flexible arrangement memory device that implements the refresh operation at the second portion of the channels of the same memory of the arrangement in box 1412 can be the same memory device and / or the first portion of the channel interface.

[0120] After implementing the refresh operation at the second portion of channels of the same memory in the arrangement in block 1412 , the flexible arrangement memory device may again receive signals for memory access at different portion of channels of the same memory in the arrangement in block 1402 .

[0121] refer to Fig. 14B In block 1420, the flexible arrangement memory device may receive a logical arrangement (eg, Figure 4 logically arranged in 402a, 402b) of different memories (e.g., Figure 2 The flexible memory device may receive signals including command and address signals, data signals, etc., which are configured to indicate to different memories that memory access is implemented at components associated with different partial channels of different memories. A first signal may be sent to a first memory (e.g., Figure 2A first portion of a channel interface (eg, Figures 2 to 4 The first memory is a memory access memory. The second signal may be sent to a second memory (e.g., Figure 2 A second portion of a channel interface (eg, Figures 2 to 4 The partial channel interface 214a, 214b, 302a, 302b, 304a, 304b in the second memory indicates that the memory access is implemented at the component associated with the second partial channel of the second memory. The flexible arrangement memory device can be connected via a communication bus (e.g., Figure 2 The sub-buses and lines 218a, 218b, 220a, 220b, 222a, 222b, 224a, 224b, 226a, 226b, 230 in Figure 3 and Figure 4 The bus and lines 306a, 306b, 308a, 308b in block 1420 receive signals. The bus can be communicatively connected to a first partial channel interface of a different memory and can carry a first signal, and can be communicatively connected to a second partial channel interface of a different memory and can carry a second signal. In some embodiments, the flexible arrangement memory device that receives signals for memory access at different partial channels of different memories in the logical arrangement in block 1420 can be different memory devices, the first partial channel interface, and / or the second partial channel interface.

[0122] In block 1422, the flexible arrangement memory device may implement memory access at different partial channels of different memories of the logical arrangement. Implementing memory access at the first partial channel and the second partial channel may include known mechanisms for reading from and / or writing to components associated with the first partial channel and the second partial channel. In some embodiments, the flexible arrangement memory device that implements memory access at different partial channels of different memories of the logical arrangement in block 1422 may be a different memory device, a first partial channel interface, and / or a second partial channel interface.

[0123] In box 1424, the flexible arrangement memory device can receive signals for refresh execution at different partial channels of different logically arranged memories. The flexible arrangement memory device can receive signals, including refresh signals, which are configured to indicate to different memories that refresh operations are implemented at components associated with different partial channels of different memories. The first refresh signal can indicate to a first partial channel interface of a first memory that a refresh operation is implemented at a component associated with a first partial channel of the first memory. The second refresh signal can indicate to a second partial channel interface of a second memory that a memory access is implemented at a component associated with a second partial channel of the second memory. The flexible arrangement memory device can receive the signal via a communication bus. The bus can be communicatively connected to the first partial channel interface of the first memory and can carry the first refresh signal, and can be communicatively connected to the second partial channel interface of the second memory and can carry the second refresh signal. The signal can be transmitted by a memory control device (e.g., a memory control device) that is communicatively connected to the bus. Figure 2 In some embodiments, the flexible arrangement memory device receiving the refresh execution signal at different partial channels of different logically arranged memories in block 1424 can be different memory devices, a first partial channel interface, and / or a second partial channel interface.

[0124] In box 1426, the flexible arrangement memory device can implement refresh operations in parallel at different partial channels of different logically arranged memories. The resources of the flexible arrangement memory device for implementing the refresh operation can be used at a limited number of partial channels (such as as few as a single partial channel) of the memory at one time. Such resources can be separated for each memory, and the flexible arrangement memory device can implement refresh operations in parallel at different memories. In some embodiments, the flexible arrangement memory device that implements the refresh operation in parallel at different partial channels of different logically arranged memories in box 1426 can be a different memory device, a first partial channel interface, and / or a second partial channel interface.

[0125] After implementing the refresh operation at different partial channels of different memories of the logical arrangement in parallel in block 1426 , the flexible arrangement memory device may again receive signals for memory access at different partial channels of different memories of the logical arrangement in block 1420 .

[0126] Various embodiments (including but not limited to the above reference Figures 1 to 14B The embodiments described herein may be implemented in a wide variety of computing systems including mobile computing devices, examples of which are suitable for use with the various embodiments are described in Fig.151500. The mobile computing device 1500 may include a processor 1502 coupled to a touch screen controller 1504 and an internal memory 1506. The processor 1502 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 1506 may be a volatile or non-volatile memory, and may also be a secure and / or encrypted memory, or an unsecure and / or unencrypted memory, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touch screen controller 1504 and the processor 1502 may also be coupled to a touch screen panel 1512, such as a resistive sensing touch screen, a capacitive sensing touch screen, an infrared sensing touch screen, and the like. In addition, the display of the mobile computing device 1500 does not need to have touch screen capabilities.

[0127] The mobile computing device 1500 may have one or more radio signal transceivers 1508 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radios) coupled to each other and / or to the processor 1502 and an antenna 1510 for transmitting and receiving communications. The transceiver 1508 and antenna 1510 may be used with the circuits mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1500 may include a cellular network wireless modem chip 1516 that enables communication via a cellular network and is coupled to the processor.

[0128] The mobile computing device 1500 may include a peripheral device connection interface 1518 coupled to the processor 1502. The peripheral device connection interface 1518 may be configured solely to accept one type of connection, or may be configured to accept various types of physical and communication connections that are shared or proprietary, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1518 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0129] The mobile computing device 1500 may also include a speaker 1514 for providing audio output. The mobile computing device 1500 may also include a housing 1520 for housing all or some of the components described herein, the housing being constructed of plastic, metal, or a combination of materials. The mobile computing device 1500 may include a power source 1522 coupled to the processor 1502, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to a peripheral device connection port to receive a charging current from a source external to the mobile computing device 1500. The mobile computing device 1500 may also include a physical button 1524 for receiving user input. The mobile computing device 1500 may also include a power button 1526 for turning the mobile computing device 1500 on and off.

[0130] Various embodiments (including but not limited to the above reference Figures 1 to 14B The described embodiments) can be implemented in a wide variety of computing systems including a laptop computer 1600, an example of which is shown in FIG. Fig.16 16. Many laptop computers include a touchpad touch surface 1617 that serves as a pointing device for the computer and can therefore receive drag, scroll, and tap gestures similar to those implemented on computing devices equipped with a touch screen display and as described above. Laptop computer 1600 will typically include a processor 1602 coupled to volatile memory 1612 and a disk drive 1613 of a large capacity non-volatile memory such as flash memory. In addition, computer 1600 may have one or more antennas 1608 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link, and / or a cellular telephone transceiver 1616 coupled to processor 1602. Computer 1600 may also include a floppy disk drive 1614 and a compact disk (CD) drive 1615 coupled to processor 1602. In a notebook configuration, the computer housing includes a touchpad 1617, a keyboard 1618, and a display 1619, all coupled to processor 1602. Other configurations of computing devices may include a computer mouse or trackball coupled to a processor (eg, via USB input) as is well known, which may also be used in conjunction with various embodiments.

[0131] Various embodiments (including but not limited to the above reference Figures 1 to 14B The described embodiments may also be implemented in a fixed computing system, such as any of a variety of commercially available servers. Fig.17 An example server 1700 is illustrated in FIG. Such a server 1700 typically includes one or more multi-core processor components 1701 coupled to a volatile memory 1702 and a large capacity non-volatile memory (such as a disk drive 1704). Fig.17As shown, a multi-core processor assembly 1701 can be added to a server 1700 by inserting it into a chassis of the assembly. The server 1700 may also include a floppy disk drive, a compact disk (CD), or a digital versatile disk (DVD) disk drive 1706 coupled to the processor 1701. The server 1700 may also include a network access port 1703 coupled to the multi-core processor assembly 1701 for establishing a network interface connection with a network 1705, such as a local area network coupled to other broadcast system computers and servers, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, 5G, LTE, or any other type of cellular data network).

[0132] Computer program code or "program code" for execution on a programmable processor to perform the operations of the various embodiments may be written in a high-level programming language (such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic), a structured query language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or program stored on a computer-readable storage medium as used in this application may refer to machine language code (such as object code) in a format that can be understood by a processor.

[0133] Specific implementation examples are described in the following paragraphs. Although some of the following specific implementation examples are described in terms of an example computing device memory system, other example implementations may include: the example functions of the computing device memory system discussed in the following paragraphs implemented as methods of the following specific implementation examples; and the example computing device memory system discussed in the following paragraphs implemented by a computing device memory system including components for performing the functions of the computing device memory system of the following specific implementation examples.

[0134] Embodiment 1. A method implemented in a memory system, comprising: receiving a first memory access command and a first address at which the first memory access command is implemented in a logical arrangement at a memory controller; generating a first signal by the memory controller, the first signal being configured to indicate to a first memory device of the logical arrangement that the first memory access command is implemented via a first portion of channels; transmitting the first signal from the memory controller to the first memory device; generating a second signal by the memory controller, the second signal being configured to indicate to a second memory device of the logical arrangement that is different from the first memory device that the first memory access command is implemented via a second portion of channels; and transmitting the second signal from the memory controller to the second memory device.

[0135] Embodiment 2. The method according to embodiment 1 may further include: generating a third signal by the memory controller, the third signal being configured to indicate to the first memory device to activate a component of the first memory device associated with the first portion of the channel; transmitting the third signal from the memory controller to the first memory device; generating a fourth signal by the memory controller, the fourth signal being configured to indicate to the second memory device to activate a component of the first memory device associated with the second portion of the channel; and transmitting the fourth signal from the memory controller to the second memory device.

[0136] Embodiment 3. The method according to any one of Embodiments 1 and 2 may also include: determining whether the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement, wherein generating the first signal, transmitting the first signal, generating the second signal, and transmitting the second signal occur in response to determining that the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement.

[0137] Embodiment 4. The method according to any one of embodiments 1-3 may also include: receiving a second memory access command and a second address at which the second memory access command is implemented in the arrangement at the memory controller; generating a third signal by the memory controller, the third signal being configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the first portion of channels; transmitting the third signal from the memory controller to the first memory device; generating a fourth signal by the memory controller, the fourth signal being configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the second portion of channels; and transmitting the fourth signal from the memory controller to the first memory device.

[0138] Embodiment 5. The method according to embodiment 4 may also include: determining whether the second address at which the second memory access command is implemented in the arrangement is in a logical arrangement, wherein the third signal is generated, the third signal is transmitted, the fourth signal is generated; and transmitting the fourth signal occurs in response to determining that the second address at which the second memory access command is implemented in the arrangement is not in the logical arrangement.

[0139] Embodiment 6. The method according to any one of Embodiments 4 or 5 may also include: receiving the first signal at a first partial channel interface of the first memory device for the first partial channel; implementing the first memory access command at the first memory device via the first partial channel; receiving the second signal at a second partial channel interface of the second memory device for the second partial channel; and implementing the second memory access command at the second memory device via the second partial channel.

[0140] Embodiment 7. A method according to embodiment 6, wherein implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device comprises: implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device in parallel.

[0141] Embodiment 8. A method implemented in a memory system, comprising: receiving a first refresh signal at a first partial channel interface for a first partial channel of a first memory device; receiving a second refresh signal at a second partial channel interface for a second partial channel of a second memory device; implementing a refresh operation at the first memory device via the first partial channel in response to the first refresh signal; and implementing a refresh operation at the second memory device via the second partial channel in response to the second refresh signal.

[0142] Embodiment 9. A method according to embodiment 8, wherein the first memory device and the second memory device are logically arranged different memory devices, and implementing the refresh operation at the second memory device includes implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.

[0143] Embodiment 10. The method according to embodiment 9 further includes: receiving a first signal at the first partial channel interface, the first signal being configured to enable the first memory device of the logical arrangement to implement a first memory access command via the first partial channel; receiving a second signal at the second partial channel interface, the second signal being configured to enable the second memory device of the logical arrangement to implement a second memory access command via the second partial channel; implementing the first memory access command at the first memory device via the first partial channel after implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device; and implementing the second memory access command at the second memory device via the second partial channel after implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.

[0144] Embodiment 11. A method according to any one of embodiments 8-10, wherein the second memory device is the first memory device, and the method further comprises: waiting for a specified refresh cycle for the refresh operation at the first memory device, wherein implementing the refresh operation at the second memory device comprises implementing the refresh operation at the second memory device after the specified refresh cycle.

[0145] Embodiment 12. The method according to embodiment 11 further includes: receiving a first signal at the first partial channel interface, the first signal being configured to enable the first memory device to implement a first memory access command via the first partial channel; receiving a second signal at the second partial channel interface, the second signal being configured to enable the second memory device to implement a second memory access command via the second partial channel; implementing the first memory access command at the first memory device via the first partial channel after implementing the refresh operation at the second memory device after the specified refresh cycle; and implementing the second memory access command at the second memory device via the second partial channel after implementing the refresh operation at the second memory device after the specified refresh cycle.

[0146] The foregoing method descriptions and process flow charts are provided only as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of operations in the foregoing embodiments may be performed in any order. Words such as "thereafter", "then", "next", etc. are not intended to limit the order of operations; these words are only used to guide the reader to read the description of the method. In addition, any reference to a claim element in the singular form (e.g., a reference using the article "one", "an", or "said") should not be interpreted as limiting the element to the singular.

[0147] The various exemplary logic blocks, modules, circuits, and algorithmic operations described in conjunction with the various embodiments may be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Although the technician may implement the described functionality in different ways for each specific application, such specific implementation decisions should not be interpreted as departing from the scope of the claims.

[0148] The hardware for implementing the various exemplary logics, logic blocks, modules and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination thereof designed to perform the functions described herein. Although a general-purpose processor can be a microprocessor, in an alternative, the processor can be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods can be performed by circuits specific to a given function.

[0149] In one or more embodiments, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, each function can be stored as one or more instructions or codes on a non-transient computer-readable medium or a non-transient processor-readable medium. The operation of the method or algorithm disclosed herein can be implemented in a processor executable software module, which can reside on a non-transient computer-readable or processor-readable storage medium. A non-transient computer-readable or processor-readable storage medium can be any storage medium that can be accessed by a computer or a processor. By way of example and not limitation, such non-transient computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of an instruction or data structure and can be accessed by a computer. Disks and optical disks as used herein include compact discs (CDs), laser discs, optical disks, digital versatile discs (DVDs), floppy disks, and blue discs, wherein disks generally reproduce data magnetically, and optical disks reproduce data optically with lasers. The above combination is also included in the scope of non-transient computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and / or instructions on a non-transitory processor-readable medium and / or computer-readable medium, which may be incorporated into a computer program product.

[0150] The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the universal principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but should be granted the broadest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method implemented in a memory system, comprising: receiving, at a memory controller, a first memory access command and a first address in a logical arrangement at which the first memory access command is implemented; generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical arrangement that the first memory access command is implemented via a first portion of channels; transmitting the first signal from the memory controller to the first memory device; generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical arrangement different from the first memory device that the first memory access command is implemented via a second portion of channels; as well as The second signal is transmitted from the memory controller to the second memory device.

2. The method according to claim 1, further comprising: generating, by the memory controller, a third signal configured to indicate to the first memory device to activate a component of the first memory device associated with the first portion of channels; transmitting the third signal from the memory controller to the first memory device; generating, by the memory controller, a fourth signal configured to indicate to the second memory device to activate a component of the first memory device associated with the second portion of channels; as well as The fourth signal is transmitted from the memory controller to the second memory device.

3. The method according to claim 1, further comprising: determining whether the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement, Wherein generating the first signal, transmitting the first signal, generating the second signal, and transmitting the second signal occur in response to determining that the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement.

4. The method according to claim 1, further comprising: receiving, at the memory controller, a second memory access command and a second address in an arrangement at which the second memory access command is implemented; generating, by the memory controller, a third signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the first portion of channels; transmitting the third signal from the memory controller to the first memory device; generating, by the memory controller, a fourth signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the second portion of channels; as well as The fourth signal is transmitted from the memory controller to the first memory device.

5. The method according to claim 4, further comprising: determining whether the second address at which the second memory access command is implemented is in a logical arrangement in the arrangement, Wherein generating the third signal, transmitting the third signal, generating the fourth signal, and transmitting the fourth signal occur in response to determining that the second address at which the second memory access command is implemented in the arrangement is not in the logical arrangement.

6. The method according to claim 4, further comprising: receiving the first signal at a first partial channel interface for the first partial channel of the first memory device; implementing the first memory access command at the first memory device via the first portion of channels; receiving the second signal at a second partial channel interface for the second partial channel of the second memory device; as well as The second memory access command is implemented at the second memory device via the second partial channel.

7. The method of claim 6, wherein implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device comprises: The first memory access command is implemented at the first memory device and the second memory access command is implemented at the second memory device in parallel.

8. A computing device comprising: a first memory device; a second memory device; and a memory controller communicatively connected to the first memory device and the second memory device and configured to: receiving a first memory access command and a first address at which the first memory access command is implemented in a logical arrangement; generating a first signal configured to indicate to the first memory device of the logical arrangement that the first memory access command is implemented via a first portion of channels; transmitting the first signal to the first memory device; generating a second signal configured to indicate to the second memory device of the logical arrangement different from the first memory device that the first memory access command is implemented via a second portion of channels; as well as The second signal is transmitted to the second memory device.

9. The computing device of claim 8, wherein the memory controller is further configured to: generating a third signal configured to indicate to the first memory device to activate a component of the first memory device associated with the first portion of channels; transmitting the third signal to the first memory device; generating a fourth signal configured to indicate to the second memory device to activate a component of the first memory device associated with the second portion of channels; as well as The fourth signal is transmitted to the second memory device.

10. The computing device of claim 8, wherein the memory controller is further configured to: determining whether the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement; and Generating the first signal, transmitting the first signal, generating the second signal, and transmitting the second signal occur in response to determining that the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement.

11. The computing device of claim 8, wherein the memory controller is further configured to: receiving a second memory access command and a second address in an arrangement at which to implement the second memory access command; generating a third signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the first portion of channels; transmitting the third signal to the first memory device; generating a fourth signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the second portion of channels; as well as The fourth signal is transmitted to the first memory device.

12. The computing device of claim 11, wherein the memory controller is further configured to: determining whether the second address at which the second memory access command is implemented is in a logical arrangement in the arrangement; and The third signal is generated, the third signal is transmitted, the fourth signal is generated, and the fourth signal is transmitted in response to determining that the second address at which the second memory access command is implemented in the arrangement is not in the logical arrangement.

13. The computing device of claim 11, wherein: The first memory device is configured as: receiving the first signal at a first partial channel interface for the first partial channel of the first memory device; as well as implementing the first memory access command at the first memory device through the first portion of channels; and The second memory device is configured as: receiving the second signal at a second partial channel interface for the second partial channel of the second memory device; as well as The second memory access command is implemented at the second memory device through the second partial channel.

14. The computing device of claim 13, wherein the first memory device is configured to implement the first memory access command at the first memory device in parallel with implementing the second memory access command at the second memory device.

15. A computing device comprising: means for receiving a first memory access command and a first address in a logical arrangement at which said first memory access command is implemented; means for generating a first signal configured to indicate to a first memory device of the logical arrangement that the first memory access command is implemented via a first portion of channels; means for transmitting said first signal to said first memory device; means for generating a second signal configured to indicate to a second memory device of the logical arrangement different from the first memory device that the first memory access command is implemented via a second portion of channels; and Means for transmitting the second signal to the second memory device.

16. The computing device of claim 15, further comprising: means for generating a third signal configured to indicate to the first memory device to activate a component of the first memory device associated with the first portion of channels; means for transmitting said third signal to said first memory device; means for generating a fourth signal configured to indicate to the second memory device to activate a component of the first memory device associated with the second portion of channels; and Means for transmitting the fourth signal to the second memory device.

17. The computing device of claim 15, further comprising: means for determining whether the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement, Wherein the means for generating the first signal, the means for transmitting the first signal, the means for generating the second signal, and the means for transmitting the second signal are implemented in response to determining that the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement.

18. The computing device of claim 15, further comprising: means for receiving a second memory access command and a second address in an arrangement at which to implement said second memory access command; means for generating a third signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the first portion of channels; means for transmitting said third signal to said first memory device; means for generating a fourth signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the second portion of channels; and Means for transmitting the fourth signal to the first memory device.

19. The computing device of claim 18, further comprising: means for determining whether said second address at which said second memory access command is implemented is in a logical arrangement in said arrangement, wherein the means for generating the third signal, the means for transmitting the third signal, the means for generating the fourth signal, and the means for transmitting the fourth signal are implemented in response to determining that the second address at which the second memory access command is implemented in the arrangement is not in the logical arrangement.

20. The computing device of claim 18, further comprising: means for receiving said first signal; means for implementing the first memory access command at the first memory device via the first portion of channels; means for receiving said second signal; and Means for implementing the second memory access command at the second memory device via the second portion of the channel.

21. The computing device of claim 20, further comprising: Means for implementing the first memory access command at the first memory device and the second memory access command at the second memory device in parallel.

22. A memory controller, the memory controller being configured to: receiving a first memory access command and a first address at which the first memory access command is implemented in a logical arrangement; generating a first signal configured to indicate to a first memory device of the logical arrangement that the first memory access command is implemented via a first portion of channels; transmitting the first signal to the first memory device; generating a second signal configured to indicate to a second memory device of the logical arrangement different from the first memory device that the first memory access command is implemented via a second portion of channels; as well as The second signal is transmitted to the second memory device.

23. The memory controller of claim 22, wherein the memory controller is further configured to: generating a third signal configured to indicate to the first memory device to activate a component of the first memory device associated with the first portion of channels; transmitting the third signal to the first memory device; generating a fourth signal configured to indicate to the second memory device to activate a component of the first memory device associated with the second portion of channels; as well as The fourth signal is transmitted to the second memory device.

24. The memory controller of claim 22, wherein the memory controller is further configured to: determining whether the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement; and Generating the first signal, transmitting the first signal, generating the second signal, and transmitting the second signal occur in response to determining that the first address at which the first memory access command is implemented in the logical arrangement is in the logical arrangement.

25. The memory controller of claim 22, wherein the memory controller is further configured to: receiving a second memory access command and a second address in an arrangement at which to implement the second memory access command; generating a third signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the first portion of channels; transmitting the third signal to the first memory device; generating a fourth signal configured to indicate to the first memory device of the arrangement that the second memory access command is implemented via the second portion of channels; as well as The fourth signal is transmitted to the first memory device.

26. The memory controller of claim 25, wherein the memory controller is further configured to: determining whether the second address at which the second memory access command is implemented is in a logical arrangement in the arrangement; and The third signal is generated, the third signal is transmitted, the fourth signal is generated, and the fourth signal is transmitted in response to determining that the second address at which the second memory access command is implemented in the arrangement is not in the logical arrangement.

27. A method implemented in a memory system, comprising: receiving a first refresh signal at a first partial channel interface for a first partial channel of a first memory device; receiving a second refresh signal at a second partial channel interface for a second partial channel of a second memory device; implementing a refresh operation at the first memory device via the first portion of channels in response to the first refresh signal; as well as A refresh operation is implemented at the second memory device via the second portion of channels in response to the second refresh signal.

28. The method of claim 27, wherein the first memory device and the second memory device are logically arranged different memory devices, and implementing the refresh operation at the second memory device comprises implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.

29. The method according to claim 28, further comprising: receiving a first signal at the first portion of the channel interface, the first signal being configured to cause the first memory device of the logical arrangement to implement a first memory access command via the first portion of the channels; receiving a second signal at the second portion of the channel interface, the second signal being configured to cause the second memory device of the logical arrangement to implement a second memory access command via the second portion of the channels; implementing the first memory access command at the first memory device via the first portion of channels after implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device; as well as The second memory access command is implemented at the second memory device via the second partial channel after implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.

30. The method of claim 27, wherein the second memory device is the first memory device, the method further comprising: A specified refresh cycle is waited for the refresh operation at the first memory device, wherein implementing the refresh operation at the second memory device includes implementing the refresh operation at the second memory device after the specified refresh cycle.

31. The method of claim 29, further comprising: receiving a first signal at the first portion of the channel interface, the first signal being configured to cause the first memory device to implement a first memory access command via the first portion of the channel; receiving a second signal at the second portion of the channel interface, the second signal being configured to cause the second memory device to implement a second memory access command via the second portion of the channel; implementing the first memory access command at the first memory device via the first portion of channels after implementing the refresh operation at the second memory device after the specified refresh cycle; as well as The second memory access command is implemented at the second memory device via the second portion of channels after the refresh operation is implemented at the second memory device after the designated refresh cycle.

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