Adaptive integrated programmable data processing unit

Abstract

An integrated circuit device is disclosed that includes a plurality of heterogeneous functional circuit blocks and an interface circuit that allows the heterogeneous functional circuit blocks to exchange data with each other using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed function circuitry, user configurable circuitry (e.g., programmable logic), and / or an embedded processor / core. The functional circuit block may be configured in a fixed functional circuit or in a user configurable circuit (i.e., as a plug-in). The interface circuit includes a network-on-chip (NoC), an adapter configured in the user-configurable circuit, and / or a memory. The functional circuit blocks may access the memory through an adapter configured by the user configurable circuit and / or through the NoC. The IC device may be configured as a SmartNIC, a DPU, or other type of system on chip (SoC).

Description

Technical Field

[0001] Examples of the present disclosure generally relate to the integration of heterogeneous circuit blocks on an integrated circuit device serving a Smart Network Interface Controller (SmartNIC) or Data Processing Unit (DPU) function. Background Art

[0002] In a system on a chip (SoC) serving SmartNIC or DPU functionality, multiple circuit blocks may be combined with little or no apparent attempt to consolidate and / or eliminate redundant and / or unnecessary features (e.g., memory, input / output buffer circuits), optimize communications between circuit blocks, address security / privacy of data transmission between circuit blocks, or accommodate updates or changes to circuit blocks. Such an SoC may utilize more area than necessary, consume more power than necessary, suffer unnecessary performance loss and / or latency, compromise the security of user / tenant data, and / or become obsolete prematurely. Summary of the invention

[0003] Techniques for the flexible integration of heterogeneous functional circuit blocks are described.

[0004] One example is an integrated circuit (IC) device that includes a plurality of heterogeneous functional circuit blocks and an interface circuit that allows the heterogeneous functional circuit blocks to exchange data with each other using a communication protocol of the corresponding heterogeneous functional circuit blocks.

[0005] Another example described herein is a system on chip (SoC) comprising a host subsystem interfacing with a local device, a network subsystem interfacing with an external packet switching network, an accelerator block comprising a plurality of heterogeneous functional circuit blocks, and an interface circuit, wherein each of the heterogeneous functional circuit blocks performs a corresponding one of a plurality of tasks on data from the host subsystem and / or the network subsystem, and the interface circuit allows the heterogeneous functional circuit blocks to exchange data with each other using communication protocols of the corresponding heterogeneous functional circuit blocks.

[0006] Another example described herein is a method that includes interfacing with an external packet switching network through a network subsystem of a system on chip (SoC), interfacing with a local device through a host interface subsystem of the SoC, processing data from the network subsystem and / or the host interface subsystem using heterogeneous functional circuit blocks of the SoC, and exchanging data between these functional circuit blocks using communication protocols of these corresponding functional circuit blocks, wherein these heterogeneous functional circuit blocks are implemented in fixed-function circuits, configurable circuits, embedded processor circuits, and / or combinations thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to be able to understand in detail the manner in which the above features are described, a more specific description briefly summarized above may be obtained by reference to example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical example implementations and therefore should not be considered to limit the scope thereof.

[0008] Figure 1 is a block diagram of an integrated circuit (IC) device that includes multiple heterogeneous functional circuit blocks and flexible or configurable interface circuits that allow the functional circuit blocks to communicate with each other (e.g., share / exchange data) using the native communication protocols of the corresponding functional circuit blocks.

[0009] Figure 2 is a block diagram of an IC device according to one embodiment, wherein the interface circuitry includes a network-on-chip (NoC) circuit that allows functional circuit blocks to communicate with each other over an on-chip packet-switched network.

[0010] Figure 3 is a block diagram of a NoC circuit including circuitry that interfaces with one of the functional circuit blocks, according to one embodiment.

[0011] Figure 4 is a block diagram of an IC device according to one embodiment, wherein the interface circuit includes one or more adapters that convert communications between functional circuit blocks based on communication protocols of the corresponding functional circuit blocks.

[0012] Figure 5 is a block diagram of an IC device according to one embodiment, wherein the interface circuit includes a combination of a NoC circuit and an adapter.

[0013] Figure 6 is a block diagram of an IC device according to one embodiment in which interface circuits allow functional circuit blocks to communicate with each other through memory.

[0014] Figure 7 is a conceptual illustration of an IC device configured as a network interface device according to one embodiment.

[0015] Figure 8 is a block diagram of an IC device configured as a network interface device according to one embodiment.

[0016] Fig. 9 is another block diagram of an IC device configured as a network interface device according to one embodiment.

[0017] Fig.10 is a block diagram of an IC device including a data transfer element (DTE) and a data exchange element (DEE) according to one embodiment.

[0018] Fig.11 is a flow chart of a method for processing data using heterogeneous functional circuit blocks according to one embodiment.

[0019] Fig.12 is a flow chart of a method for processing data in a network application using heterogeneous functional circuit blocks according to one embodiment.

[0020] Fig.13 is a flow chart of another method of processing data using heterogeneous functional circuit blocks according to one embodiment.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0022] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by similar reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to be an exhaustive description of the features nor to limit the scope of the claims. In addition, the illustrated examples do not necessarily have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular example are not necessarily limited to that example, and may be practiced in any other example even if not so illustrated or so explicitly described.

[0023] Embodiments herein describe methods and systems for flexibly integrating functionally heterogeneous circuit blocks within an integrated circuit (IC) device to allow the functionally heterogeneous circuit blocks to communicate with each other (eg, share / exchange data) using communication protocols of the respective functional circuit blocks.

[0024] Embodiments herein include multiple techniques for communicating or sharing data between functional circuit blocks using the communication protocols of the corresponding functional circuit blocks. Various combinations of these techniques can be used to provide a flexible / configurable communication structure. The communication techniques include adapters that are configured in programmable logic to allow direct communication between functional circuit blocks, on-chip packet switching networks (i.e., on-chip networks or NoCs), and shared memories.

[0025] Embodiments herein may be used to merge heterogeneous or disparate functional circuit blocks into a system on a chip (SoC), such as a smart network interface controller (SmartNIC) or a data processing unit (DPU).

[0026] The embodiments herein may be used to provide an adaptive computing acceleration platform, such as for use in SmartNIC or DPU domains.

[0027] Embodiments herein may be used to offload tasks from local devices (e.g., host computer systems / servers and / or storage devices and / or network devices). This may allow local devices to focus on tasks that can be charged to users / customers / tenants (i.e., maximizing revenue without sacrificing tenant security).

[0028] Embodiments herein include flexible combinations of fixed logic or fixed function circuits (e.g., application specific integrated circuits (ASICs)), embedded processors / cores, configurable circuits (e.g., programmable logic of field programmable gate arrays (FPGAs)), and combinations thereof.

[0029] Tasks may be assigned to one type of circuit, or may be divided between a combination of types based on the characteristics of the task and the characteristics of the circuit type. For example, fixed-function circuits may be used for tasks or subtasks that are expected to be widely used, used in a variety of applications / situations, and / or expected not to change in the foreseeable future. Examples include, but are not limited to, standards-based interfaces (e.g., Ethernet and / or Peripheral Component Interconnect Express (PCIe) interface standards) and encryption tasks. Fixed-function circuits may be useful for power consumption considerations.

[0030] Embedded processors / cores may be used for high software flexibility tasks (e.g., open source software stacks) or relatively low functionality tasks (e.g., non-floating point operations or tasks where speed or high throughput is not critical).

[0031] Configurable circuits (e.g., programmable logic / field programmable gate arrays (FPGAs)) may be useful where flexibility is important (e.g., to accommodate user-specific or infrequently used tasks), such as providing unique plug-ins as adapters that convert between communication protocols of heterogeneous functional circuit blocks, and / or to accommodate rapidly evolving and / or new acceleration or offload functionality.

[0032] Embodiments herein may be useful for presenting a unified software view of heterogeneous elements of a SoC.

[0033] Figure 1 1 is a block diagram of an integrated circuit (IC) device 100 that includes a plurality of heterogeneous functional circuit blocks 102 and a flexible or configurable interface circuit 110 that allows the functional circuit blocks 102 to communicate with each other (e.g., share / exchange data) using the native communication protocols of the respective functional circuit blocks. The functional circuit blocks 102 are heterogeneous because the communication protocols of the functional circuit blocks 102 are different from each other. The IC device 100 may also include homogeneous circuit blocks.

[0034] One or more of functional circuit blocks 102, or portions thereof, may include fixed function circuits (eg, application specific integrated circuits (ASICs)), processor circuits, and / or configurable circuits (eg, programmable logic).

[0035] IC device 100 may be configurable in a number of aspects, including configuring features of functional circuit blocks, dynamically adding functional circuit blocks (i.e., plug-ins) in the configurable circuit, and configuring interface circuit 110 in the configurable circuit (e.g., configuring / adding adapters, configuring access to memory 604, and configuring access to NoC circuit 202).

[0036] For the purpose of illustration, the IC device 100 is described in one or more examples herein as a network interface device that interfaces between a packet switching network and a local device, such as a host system (e.g., a server, a server cluster, and / or a data center) and / or a storage system. The IC device 100 may represent, for example, an intelligent network interface controller (SmartNIC) or a data processing unit (DPU) that performs tasks other than conventional NIC tasks. The IC device 100 may, for example, offload tasks of a host computer system or a storage system or a network system. Such tasks may be referred to as accelerated tasks herein. The IC device 100 may perform accelerated tasks in a pipeline and / or parallel manner. However, the IC device 100 is not limited to any of the foregoing examples.

[0037] Reference below Figures 2 to 6 An exemplary implementation of the interface circuit 110 is provided.

[0038] Figure 2 is a block diagram of an IC device 100 according to one embodiment, wherein the interface circuit 110 includes a network-on-chip (NoC) circuit 202 that allows the functional circuit blocks 102 to communicate with each other via an on-chip packet switching network. The NoC circuit 202 may include NoC interface circuits that interface with the functional circuit blocks 102. Figure 3 Provide an example.

[0039] Figure 32 is a block diagram of a NoC circuit 202 according to one embodiment, including a NoC interface circuit 300 that interfaces with a circuit block 102A. The NoC interface circuit 300 includes a NoC master unit (NMU) 304 that handles communications (e.g., memory access requests) initiated by the functional circuit block 102A. The NoC interface circuit 300 also includes a NoC slave unit (NMU) 306 that handles communications initiated by other circuits and directed to the functional circuit block 102A. The NoC interface circuit 300 also includes a NoC packet switch (NPS) 308 that interfaces between the interconnect 302 and each of the NMU 304 and the NSU 306. The interconnect 302 can couple the NPS 308 to other NPs of the NoC.

[0040] NMU 304 includes packing circuitry 310 for packing data transmitted over NoC interconnect 302 and unpacking circuitry 312 for unpacking transmissions received over NoC interconnect 302. NMU 304 also includes configurable interface circuitry 314 for converting between the communication protocol of functional circuit block 102A and the protocol of NMU 304.

[0041] NSU 306 includes packing circuitry 316 for packing data for transmission over NoC interconnect 302 and unpacking circuitry 318 for unpacking transmissions received over NoC interconnect 302. NSU 306 also includes configurable interface circuitry 320 for converting between the communication protocol of functional circuit block 102A and the protocol of NMU 304.

[0042] Figure 4 1 is a block diagram of an IC device 100 according to one embodiment, wherein the interface circuit 110 includes one or more adapters 402 that convert communications between functional circuit blocks 102 based on the communication protocols of the corresponding functional circuit blocks 102. Figure 4 In the embodiment, the adapters 402A, 402B and 402C switch between the corresponding pairs of functional circuit blocks 102A, 102B and 102C. The adapter 402 may be implemented using an ASIC, a configurable circuit, an embedded processor circuit and / or a combination thereof.

[0043] Figure 5 is a block diagram of an IC device 100 according to one embodiment, wherein the interface circuit 110 includes a combination of the NoC circuit 202 and the adapter 402. In this example, the functional circuit blocks 102 may communicate with each other via the adapter 402 and / or the NoC circuit 202.

[0044] In one embodiment, the interface circuit 110 allows the functional circuit blocks 102 to share or exchange data through a shared memory. Figure 6 Provide examples.

[0045] Figure 6 604 is a block diagram of an IC device 100 according to one embodiment, wherein the interface circuit 110 allows the functional circuit blocks 102 to communicate with each other (eg, share or exchange data) through the memory 604. Figure 6 As shown, the memory 604 may be disposed on the chip or off the chip.

[0046] exist Figure 6 In the example of FIG. 1 , the interface circuit 110 includes one or more adapters 602 that allow one or more functional circuit blocks 102 to access a common area of ​​a memory 604. The adapter 602 can be configured as a direct memory access (DMA) controller. The adapter 602 can be implemented using fixed function circuits, configurable circuits, embedded processors, and / or a combination thereof.

[0047] Interface circuit 110 also includes NoC circuit 202. In this example, one or more of functional circuit blocks 102 may access adapter 602 through the packet switching network of NoC circuit 202 and / or directly via adapter 602 (ie, without passing through the packet switching network of NoC circuit 202).

[0048] Functional circuit blocks 102 may communicate with each other through the common area of ​​memory 604. For example, functional circuit block 102A may process data and store the processed data in the common area of ​​memory 604. Thereafter, functional circuit block 102B may retrieve the data from the common area of ​​memory 604 and further process the data. Functional circuit block 102B may return the further processed data to the common area of ​​memory 604 and / or may send the further processed data to another functional circuit block in functional circuit block 102 and / or an off-chip device.

[0049] Exemplary applications or use cases of IC device 100 are provided below.

[0050] Figure 7 is a conceptual illustration of an IC device 100 configured as a network interface device according to one embodiment. Figure 7 , IC device 100 includes ASIC logic 702, embedded processing circuitry 704, and programmable logic (PL) 706 (ie, configurable circuitry).

[0051] ASIC logic 702, embedded processing circuitry 704, PL 706, and / or a combination thereof perform functions or tasks 710. Figure 7In the example of FIG. 1 , task 710 includes network control plane task 710A, telemetry task 710B, DMA offload task 710C, encryption offload task 710D, network data plane offload task 710E, client header extension 710F, hot add / remove new function 710G, custom data plane offload task 710H, and custom coherent accelerator 710I. IC device 100 may be dynamically configurable to add and / or remove functions, shown here as hot add / remove new function 710G. However, task 710 is not limited to the foregoing example. Task 710 may represent a corresponding functional circuit block.

[0052] exist Figure 7 , network control plane tasks 710A are shown as being physically proximate to embedded processing circuitry 704 to convey that network control plane tasks 710A may be executed entirely or substantially entirely within embedded processing circuitry 704 .

[0053] Similarly, ASIC logic 702 is shown physically proximate to cryptographic offload task 710D to convey that cryptographic offload task 710D may be executed entirely or substantially entirely within ASIC logic 702 .

[0054] exist Figure 7 , IC device 100 further includes adapter 708, including adapter 708A that interfaces between ASIC logic 702 and embedded processing circuit 704, adapter 708B that interfaces between ASIC logic 702 and PL 706, and adapter 708C that interfaces between embedded processing circuit 704 and PL 706. Adapter 708 may be implemented in ASIC logic 702, embedded processing circuit 704, PL 706, and / or a combination thereof.

[0055] Tasks 710 or a subset thereof may communicate with each other through adapter 708. Alternatively or additionally, tasks 710 or a subset thereof may communicate directly with each other. Figure 7 In the example, the customized data plane offload task 710H is directly connected to the telemetry task 710B via the link 712A, connected to the network data plane offload task 710E via the link 712B, and connected to the customized coherent accelerator 710I via the link 712C.

[0056] exist Figure 7 704, the connections between ASIC logic 702, embedded processing circuitry 704, PL 706, and tasks 710 in the course of completing a particular task are conceptually illustrated with lines, such as line 712. For example, telemetry task 710B, while primarily performed by embedded processing circuitry 704, may have logical and / or physical connections to ASIC logic 702 and PL 706.

[0057] Figure 8is a block diagram of an IC device 100 configured as a network interface device according to one embodiment. Figure 8 8, functional circuit block 102B includes a network subsystem 802 that interfaces with a packet-switched network via a switch 804. Functional circuit block 102A includes a host subsystem 806 that interfaces with a host 808 and / or a storage system 810. Functional circuit block 102C includes a processor subsystem 812. One or more of functional circuit blocks 102A, 102B, and 102C may perform tasks in addition to conventional NIC tasks, such as described in one or more examples herein. Network subsystem 802, host subsystem 806, processor subsystem 812, interface circuit 110, or portions thereof may utilize PL logic 706. In alternative embodiments, PL logic may be omitted from IC device 100.

[0058] Fig. 9 is another block diagram of an IC device 100 configured as a network interface device according to one embodiment.

[0059] exist Fig. 9 , IC device 100 includes memory 604 within memory subsystem 902. IC device 100 also includes programmable logic region 904, which may include configurable hardware. Programmable logic region 904 may be programmable or configurable by, for example, a manufacturer, a distributor, and / or an end user (e.g., a cloud owner / operator or user / tenant).

[0060] IC device 100 also includes Figure 8 The network subsystem 802, the host subsystem 806, and the processor subsystem 812 of the programmable logic region 904 can perform DAP acceleration tasks and / or domain-specific acceleration tasks.

[0061] Fig.10 is a block diagram of an IC device 100 including a data transfer element (DTE) and a data exchange element (DEE) according to one embodiment.

[0062] exist Fig.10 In the embodiment, DTE includes host-side DTE 1002, network-side DTE 1004, encryption DTE 1008A and decryption DTE 1008B. Host-side DTE 1002 performs host-related tasks (eg, offloaded / accelerated host tasks). Network-side DTE 1004 performs network-related tasks.

[0063] DEEs 1006A to 1006F represent data switching (e.g., to / from memory and / or between DTEs). DEEs 1006A to 1006F may represent data switching through NoC circuits and / or through configurable adapters. Element 1006 may be used to exchange data between host-side DTEs 1002, between network-side DTEs 1004, and / or between host-side DTEs 1002 and network-side DTEs 1004.

[0064] Such as Fig.10 The DTE and DEE shown may include fixed function circuitry, configurable circuitry, embedded processing circuitry, and / or combinations thereof.

[0065] A DTE or DEE implemented in configurable circuitry may be referred to as a card.

[0066] Fig.11 is a flow chart of a method 1100 of processing data with heterogeneous functional circuit blocks according to one embodiment. The method 1100 is described below with reference to the IC device 100. However, the method 1100 is not limited to the example of the IC device 100.

[0067] At 1102 , IC device 100 processes data using heterogeneous functional circuit blocks 102 implemented in fixed function circuits, configurable circuits, embedded processing circuits, and / or combinations thereof, such as described in one or more examples herein.

[0068] At 1104 , the functional circuit blocks 102 share or exchange data between each other through the configurable interface circuit 110 using a communication protocol of the respective functional circuit blocks, such as described in one or more examples herein.

[0069] The method 1100 may be performed in a network application, such as the following reference Fig.12 as described.

[0070] Fig.12 is a flow chart of a method 1200 of processing data in a network interface application using heterogeneous functional circuit blocks according to one embodiment. The method 1200 is described below with reference to the IC device 100. However, the method 1100 is not limited to the example of the IC device 100.

[0071] At 1202, IC device 100 receives data from network subsystem 802 ( Figure 8 , Fig. 9 and Fig.10 ) to interface with an external packet-switched network, such as described in one or more examples herein.

[0072] At 1204, IC device 100 receives the data from host subsystem 806 ( Figure 8 , Fig. 9and Fig.10 ) and local devices (for example, Figure 8 808 and / or storage system 810) handover, such as described in one or more examples herein.

[0073] At 1206, IC device 100 processes data using heterogeneous functional circuit blocks 102, such as described with respect to one or more examples herein. IC device 100 may, for example, process data from a local device and / or from an external packet-switched network, such as described above with respect to Figure 8 , Fig. 9 and / or Fig.10 as described.

[0074] At 1208 , the functional circuit blocks 102 share data between each other through the configurable interface circuit 110 using a communication protocol of the respective functional circuit blocks, such as described with respect to one or more examples herein.

[0075] Fig.13 is a flow chart of a method 1300 of processing data with heterogeneous functional circuit blocks according to one embodiment. The method 1300 is described below with reference to the IC device 100. However, the method 1300 is not limited to the example of the IC device 100.

[0076] At 1302 , the IC device 100 processes data using heterogeneous functional circuit blocks 102 implemented in fixed function circuits, configurable circuits, embedded processing circuits, and / or combinations thereof, such as described in one or more examples herein.

[0077] At 1304 , two or more heterogeneous functional circuit blocks 102 share or exchange data through the NoC circuit 202 , such as described in one or more examples herein.

[0078] At 1306 , two or more heterogeneous functional circuit blocks 102 share or exchange data through an adapter 402 , such as described in one or more examples herein.

[0079] At 1308 , two or more heterogeneous functional circuit blocks 102 share or exchange data through memory 604 , such as described in one or more examples herein.

[0080] In the foregoing, reference is made to the embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the described features and elements (whether or not involving different embodiments) is contemplated as implementing and practicing the contemplated embodiments. In addition, although the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the scope of the present disclosure. Therefore, the foregoing aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless expressly stated in the claims.

[0081] As will be appreciated by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Thus, various aspects may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." Additionally, various aspects may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0082] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or apparatus, or any suitable combination of the foregoing. More specific examples (not a complete list) of computer-readable storage media would include the following: an electrical connector having one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device or apparatus.

[0083] A computer readable signal medium may include a propagated data signal having computer readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such a propagated signal may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0084] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0085] The computer program code for performing operations for various aspects of the present disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming language or similar programming languages). The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0086] Aspects of the present disclosure are described below with reference to flowchart illustrations and / or block diagrams of the methods, devices (systems) and computer program products of the embodiments presented in the present disclosure. It should be understood that each frame of the flowchart illustration and / or block diagram and the combination of frames in the flowchart illustration and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that instructions executed by a processor of a computer or other programmable data processing device create components for implementing the functions / actions specified in one or more frames of a flowchart and / or block diagram.

[0087] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus, or other device to function in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0088] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operating steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer-implemented method, so that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0089] The flow chart and block diagram in the figure illustrate the possible concrete implementation architecture, functionality and operation of the system, method and computer program product according to various examples of the present invention.In this regard, each frame in the flow chart or block diagram may represent the module, segment or part of one or more executable instructions for realizing the specified logical function of the instruction.In some alternative implementations, the function pointed out in the frame may not occur in the order pointed out in the figure.For example, depending on the functionality involved, the two frames shown in succession can actually be performed substantially at the same time, or these frames can sometimes be performed in reverse order.It will also be noted that each frame in the block diagram and / or flow chart illustration and the combination of the frames in the block diagram and / or flow chart illustration can be realized by a system based on special hardware that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0090] The above disclosure may be illustrated in one or more of the following non-limiting examples.

[0091] Embodiment 1: An integrated circuit (IC) device, comprising: a plurality of heterogeneous functional circuit blocks; and an interface circuit, wherein the interface circuit is configured to allow the heterogeneous functional circuit blocks to exchange data with each other using a communication protocol of the corresponding heterogeneous functional circuit blocks.

[0092] Embodiment 2: An IC device according to embodiment 1, wherein the interface circuit comprises: a network on chip (NoC) circuit, wherein the NoC circuit allows the heterogeneous functional circuit blocks to communicate with each other through a packet switching network using the communication protocol of the corresponding heterogeneous functional circuit blocks.

[0093] Embodiment 3: An IC device according to Embodiment 1, wherein the interface circuit comprises: a user-configurable circuit, wherein the user-configurable circuit is configured as an adapter to convert between the communication protocol of the first heterogeneous functional circuit block of the heterogeneous functional circuit blocks and the communication protocol of the second heterogeneous functional circuit block of the heterogeneous functional circuit blocks.

[0094] Embodiment 4: The IC device according to embodiment 1 further comprises: a memory, wherein the interface circuit is configured to allow the heterogeneous functional circuit blocks to exchange data with each other through the memory.

[0095] Embodiment 5: The IC device according to embodiment 4, wherein the interface circuit includes: a user configurable circuit, the user configurable circuit is configured as a direct memory access (DMA) controller to allow the heterogeneous functional circuit blocks to access the memory.

[0096] Embodiment 6: The IC device according to embodiment 5, wherein the interface circuit further comprises: a network on chip (NoC) circuit, wherein the NoC circuit is configured to allow the heterogeneous functional circuit blocks to access the DMA controller through an on-chip packet switching network.

[0097] Embodiment 7: The IC device of Embodiment 1 further comprising a combination of fixed function circuitry and user configurable circuitry.

[0098] Embodiment 8: An IC device according to Embodiment 7, wherein: a first heterogeneous functional circuit block among the heterogeneous functional circuit blocks is configured in the fixed functional circuit; and a second heterogeneous functional circuit block among the heterogeneous functional circuit blocks is configured in the user configurable circuit as a plug-in module.

[0099] Embodiment 9: An IC device according to Embodiment 7, wherein: a portion of the user-configurable circuit is configured as an adapter to convert between the communication protocol of the first heterogeneous functional circuit block of the heterogeneous functional circuit blocks and the communication protocol of the second heterogeneous functional circuit block of the heterogeneous functional circuit blocks.

[0100] Embodiment 10: The IC device of Embodiment 7 further comprising a processor circuit.

[0101] Embodiment 11: An IC device according to embodiment 1, wherein the heterogeneous functional circuit block includes: a network subsystem, which is configured to interface with an external packet switching network; a host subsystem, which is configured to interface with a host device; and an accelerator circuit block, which is configured to process data received from the network interface subsystem and / or the host subsystem.

[0102] Embodiment 12: The IC device of embodiment 11, wherein the accelerator circuit block is further configured to perform tasks selected from the group consisting of: direct memory access tasks; encryption tasks; network data plane tasks; and network control plane tasks.

[0103] Embodiment 13: The IC device of Embodiment 12, wherein at least a portion of the accelerator circuit block is configured as a plug-in module in a user-configurable circuit of the IC device.

[0104] Embodiment 14: The IC device according to embodiment 1, wherein the communication protocols of the heterogeneous functional circuit blocks are different from each other.

[0105] Embodiment 15: A system on chip (SoC), the SoC comprising: a host subsystem, the host subsystem being configured to interface with a local device; a network subsystem, the network subsystem being configured to interface with an external packet switching network; an accelerator block, the accelerator block comprising a plurality of heterogeneous functional circuit blocks, each of the heterogeneous functional circuit blocks being configured to perform a corresponding one of a plurality of tasks on data from the host subsystem and / or the network subsystem; and an interface circuit, the interface circuit being configured to allow the heterogeneous functional circuit blocks to exchange data with each other using communication protocols of the corresponding heterogeneous functional circuit blocks.

[0106] Embodiment 16: A SoC according to embodiment 15, wherein the interface circuit comprises: a network on chip (NoC) circuit, the NoC circuit allowing the heterogeneous functional circuit blocks to communicate with each other through a packet switching network using the communication protocol of the corresponding functional circuit blocks; and / or a user-configurable circuit, the user-configurable circuit being configured as an adapter to convert between the communication protocol of a first functional circuit block among the functional circuit blocks and the communication protocol of a second functional circuit block among the functional circuit blocks.

[0107] Embodiment 17: According to the SoC of Embodiment 15, the SoC further comprises: a memory, wherein the interface circuit is configured to allow the functional circuit blocks to exchange data with each other through the memory.

[0108] Embodiment 18: The SoC according to embodiment 16, wherein: a first heterogeneous functional circuit block among the heterogeneous functional circuit blocks is configured in a fixed functional circuit; and

[0109] A second one of the heterogeneous functional circuit blocks is configured as a plug-in module in the user-configurable circuit.

[0110] Embodiment 19: A method, comprising: interfacing with an external packet switching network through a network subsystem of a system on chip (SoC); interfacing with a local device through a host interface subsystem of the SoC; using heterogeneous functional circuit blocks of the SoC to process data from the network subsystem and / or the host interface subsystem, wherein the heterogeneous functional circuit blocks are implemented in fixed-function circuits, configurable circuits, embedded processor circuits, and / or a combination thereof; and exchanging data between the heterogeneous functional circuit blocks using communication protocols of the corresponding heterogeneous functional circuit blocks.

[0111] Embodiment 20: A method according to embodiment 19, wherein the exchanging data comprises: exchanging the data through an on-chip packet switching network of the SoC; exchanging the data through an adapter configured in a user-configurable circuit of the SoC; and / or exchanging the data through a memory of the SoC.

[0112] While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope of the invention, and the scope of the invention is determined by the following claims.

Claims

1. An integrated circuit (IC) device, the IC device comprising: Multiple heterogeneous functional circuit blocks; and An interface circuit is configured to allow the heterogeneous functional circuit blocks to exchange data with each other using a communication protocol of the corresponding heterogeneous functional circuit blocks.

2. The IC device of claim 1 , wherein the interface circuit comprises: A network-on-chip (NoC) circuit allows the heterogeneous functional circuit blocks to communicate with each other over a packet switching network using the communication protocol of the corresponding heterogeneous functional circuit blocks.

3. The IC device of claim 1 , wherein the interface circuit comprises: A user configurable circuit is configured as an adapter to convert between the communication protocol of a first one of the heterogeneous functional circuit blocks and the communication protocol of a second one of the heterogeneous functional circuit blocks.

4. The IC device according to claim 1, further comprising: a memory, wherein the interface circuit is configured to allow the heterogeneous functional circuit blocks to exchange data with each other through the memory; And wherein the interface circuit comprises: A user configurable circuit is configured as a direct memory access (DMA) controller to allow the heterogeneous functional circuit blocks to access the memory.

5. The IC device of claim 4, wherein the interface circuit further comprises: A network-on-chip (NoC) circuit is configured to allow the heterogeneous functional circuit blocks to access the DMA controller through an on-chip packet switching network.

6. The IC device of claim 1, further comprising a combination of fixed function circuitry and user configurable circuitry.

7. The IC device of claim 6, wherein: A first heterogeneous functional circuit block among the heterogeneous functional circuit blocks is configured in the fixed functional circuit; and A second one of the heterogeneous functional circuit blocks is configured in the user-configurable circuit as a plug-in module.

8. The IC device of claim 6, wherein: A portion of the user configurable circuit is configured as an adapter to convert between the communication protocol of a first one of the heterogeneous functional circuit blocks and a communication protocol of a second one of the heterogeneous functional circuit blocks.

9. The IC device of claim 1 , wherein the heterogeneous functional circuit blocks include: a network subsystem configured to interface with an external packet-switched network; a host subsystem configured to interface with a host device; and An accelerator circuit block is configured to process data received from the network interface subsystem and / or the host subsystem.

10. The IC device of claim 9, wherein the accelerator circuit block is further configured to perform a task selected from the group consisting of: Direct memory access tasks; Encryption tasks; Network data plane tasks; and Network control plane tasks.

11. The IC device of claim 10, wherein at least a portion of the accelerator circuit block is configured as a plug-in module in a user-configurable circuit of the IC device. 12 . The IC device according to claim 1 , wherein the communication protocols of the heterogeneous functional circuit blocks are different from each other.

13. A system on chip (SoC), the SoC comprising: a host subsystem configured to interface with a local device; a network subsystem configured to interface with an external packet-switched network; an accelerator block, the accelerator block comprising a plurality of heterogeneous functional circuit blocks, each of the heterogeneous functional circuit blocks being configured to perform a corresponding one of a plurality of tasks on data from the host subsystem and / or the network subsystem; and An interface circuit is configured to allow the heterogeneous functional circuit blocks to exchange data with each other using a communication protocol of the corresponding heterogeneous functional circuit blocks.

14. The SoC according to claim 13, wherein the interface circuit comprises: a network-on-chip (NoC) circuit that allows the heterogeneous functional circuit blocks to communicate with each other over a packet-switched network using the communication protocol of the corresponding functional circuit blocks; and / or A user configurable circuit is configured as an adapter to convert between the communication protocol of a first one of the functional circuit blocks and the communication protocol of a second one of the functional circuit blocks.

15. The SoC according to claim 14, wherein: A first heterogeneous functional circuit block among the heterogeneous functional circuit blocks is configured in a fixed functional circuit; and A second one of the heterogeneous functional circuit blocks is configured as a plug-in module in the user-configurable circuit.

16. A method comprising: Interfacing with external packet-switched networks through the network subsystem of the system-on-chip (SoC); Interfacing with a local device via a host interface subsystem of the SoC; Processing data from the network subsystem and / or the host interface subsystem using heterogeneous functional circuit blocks of the SoC, wherein the heterogeneous functional circuit blocks are implemented in fixed function circuits, configurable circuits, embedded processor circuits, and / or combinations thereof; as well as Data is exchanged between the heterogeneous functional circuit blocks using the communication protocols of the corresponding heterogeneous functional circuit blocks.

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