Storage device

Abstract

The invention provides a storage device. The first string has one end connected to the first wiring and the other end connected to the second wiring, and includes a first memory cell transistor. The second string has one end connected to the first wiring and the other end connected to the second wiring, and includes a second memory cell transistor. The first power supply line is connected to the gate of the first memory cell transistor via the first transistor, and is connected to the gate of the second memory cell transistor via the second transistor. The third string has one end connected to the first wiring and the other end connected to the second wiring, and includes a third memory cell transistor. The second power supply line is connected to the gate of the third memory cell transistor, and a voltage different from that of the first power supply line is applied during the data erase period.

Description

Technical Field

[0001] Embodiments generally relate to storage devices. Background Art

[0002] A memory device in which memory cells are arranged three-dimensionally is known. Memory devices are required to have a smaller area.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent No. 11011237 Summary of the invention

[0006] Problems to be solved by the invention

[0007] A storage device having a smaller area is provided.

[0008] Technical solutions to solve problems

[0009] A storage device according to one embodiment includes a first wiring, a second wiring, a first string, a second string, a first power line, a third string, and a second power line.

[0010] One end of the first string is connected to the first wiring, and the other end is connected to the second wiring, and the first string includes a first memory cell transistor. One end of the second string is connected to the first wiring, and the other end is connected to the second wiring, and the second string includes a second memory cell transistor. The first power line is connected to the gate of the first memory cell transistor via the first transistor, and is connected to the gate of the second memory cell transistor via the second transistor. One end of the third string is connected to the first wiring, and the other end is connected to the second wiring, and the third string includes a third memory cell transistor. The second power line is connected to the gate of the third memory cell transistor, and a voltage different from that of the first power line is applied during data erasure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram showing components of the storage device according to the first embodiment and an example of connection between the components.

[0012] Figure 2 This is a diagram showing the types of blocks in the first embodiment.

[0013] Figure 3 This is a diagram showing components of one block of the storage device according to the first embodiment and connections between the components.

[0014] Figure 4 It is a diagram showing voltages output from the voltage generating circuit according to the first embodiment.

[0015] Figure 5 It is a diagram showing components of the driver according to the first embodiment and connections between the components.

[0016] Figure 6 This is a diagram showing components of the row decoder according to the first embodiment and connections between the components.

[0017] Figure 7 The diagram shows a cross-sectional structure of a part of the memory cell array of the memory device according to the first embodiment, and is a diagram showing the structure along the yz plane.

[0018] Figure 8 This is a diagram showing the concentration distribution of impurities in a part of the storage device according to the first embodiment.

[0019] Fig. 9 This is a diagram showing the concentration distribution of impurities in a part of the storage device according to the first embodiment.

[0020] Fig.10 This is a diagram showing voltages applied to several wirings during a data erasing period in the memory device according to the first embodiment.

[0021] Fig.11 This is a diagram showing voltages applied to several wirings over time during a data erasing period in the memory device according to the first embodiment.

[0022] Fig.12 This is a diagram showing voltages applied to several wirings during a data writing period in the memory device according to the first embodiment.

[0023] Fig.13 This is a diagram showing voltages applied to several wirings during a data read period in the memory device according to the first embodiment.

[0024] Fig.14 This is a diagram showing voltages applied to several wirings during a data erasing period in a memory device according to a modification of the first embodiment.

[0025] Fig.15 This is a diagram showing voltages applied to several wirings during a data writing period in a memory device according to a modification of the first embodiment.

[0026] Fig.16 The following diagram shows voltages applied to several wirings during a data read period in a memory device according to a modification of the first embodiment.

[0027] Description of Reference Numerals

[0028] BLKO…Usually block

[0029] BLKB…Bias Block

[0030] SGDdr...Driver Circuit

[0031] SGSdr...Driver Circuit

[0032] CGdr...Driver Circuit

[0033] BLKBdr…Driver Circuit

[0034] SGD…wiring

[0035] CG…Wiring

[0036] SGS…Wiring

[0037] BLKBI…wiring

[0038] 111…Block Decoder

[0039] 112…Transmission switch group

[0040] XS…Transfer Switch DETAILED DESCRIPTION

[0041] The following describes the embodiments with reference to the accompanying drawings. For a plurality of components having substantially the same function and configuration in a certain embodiment or different embodiments, numbers or characters are sometimes further added to the end of the reference numerals in order to distinguish them from each other. In the subsequent embodiments of a certain embodiment that has been described, the main points that are different from the described embodiment are described. All descriptions of a certain embodiment are also applicable to the descriptions of other embodiments unless explicitly or obviously excluded.

[0042] The drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. may be different from the actual. Therefore, the specific thickness and size should be judged by referring to the following description. In addition, the drawings may also contain parts with different relationship and ratio of size.

[0043] In the present specification and claims, a first element being “connected to a second element” includes the first element being connected to the second element directly or always or selectively via an element that is conductive.

[0044] The following describes the implementation using an xyz orthogonal coordinate system. In the following description, the term "lower" and its derivatives and related terms refer to a smaller coordinate position on the z-axis, and the term "upper" and its derivatives and related terms refer to a larger coordinate position on the z-axis.

[0045] 1. First Implementation Method

[0046] 1.1. Composition (structure)

[0047] 1.1.1. Storage Device

[0048] Figure 1 An example of components of a storage device 1 according to a first embodiment and connections of the components is shown. The storage device 1 is a device that uses a storage unit to store data. The storage device 1 is controlled by an external memory controller. The storage device 1 operates based on, for example, a command CMD and address information ADD received from the memory controller. The storage device 1 receives data DAT to be written and outputs the data stored in the storage device 1.

[0049] like Figure 1 As shown, the storage device 1 includes components such as a plurality of planes PLN, for example, four planes PLN_0, PLN_1, PLN_2 and PLN_3, a register 12, a sequencer 13, a voltage generating circuit 14 and a driver 15.

[0050] Each plane PLN is a collection of multiple components. The plane PLN is a unit (storage area) to which data is written and read. Planes PLN_0 to PLN_3 can operate independently of each other. Each plane PLN includes a group of the same components, including a memory cell array 10, a row decoder 11, and a sense amplifier 17.

[0051] The register 12 is a circuit for holding the command CMD and address information ADD received from the memory device 1. The command CMD instructs the sequencer 13 to perform various operations including data reading, data writing, and data erasing. The address information ADD specifies the access target in the memory cell array 10.

[0052] The sequencer 13 is a circuit that controls the overall operation of the memory device 1. Based on the command CMD received from the register 12, the sequencer 13 controls the row decoder 11, the driver 15, and the sense amplifier 17 to perform various operations including data reading, data writing, and data erasing.

[0053] The voltage generating circuit 14 is a circuit that generates a plurality of voltages of different magnitudes. The voltage generating circuit 14 receives a power supply voltage from outside the memory device 1 and generates a plurality of voltages from the power supply voltage. The generated voltages are supplied to components such as the memory cell array 10 and the driver 15.

[0054] The driver 15 is a circuit that applies various voltages required for the operation of the memory device 1 to several components. The driver 15 receives a plurality of voltages from the voltage generating circuit 14 and supplies a selected voltage from the plurality of voltages to one or more row decoders 11 .

[0055] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT (not shown). Wiring such as word lines WL (not shown) and bit lines BL (not shown) are also located in the memory cell array 10.

[0056] The row decoder 11 is a circuit for selecting a block BLK and transmits a voltage supplied from the driver 15 to one block BLK selected based on a block address received from the register 12 .

[0057] The sense amplifier 17 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT, generates read data based on the sensed state, or transmits write data to the memory cell transistor MT. The sense amplifier 17 also applies a voltage of a magnitude based on the operation to the bit line BL during data reading and data writing.

[0058] 1.1.2. Types of blocks

[0059] Figure 2 The types of blocks in the first embodiment are shown. Figure 2 The memory cell array 10 of one plane PLN is shown. The following description is applicable to the memory cell array 10 of each plane PLN.

[0060] like Figure 2 As shown, the blocks BLK in the memory cell array 10 in one plane PLN include a normal type block BLK and at least one bias block BLKB. The normal block BLK is used for storing data and is sometimes referred to as a normal block BLKO hereinafter.

[0061] As described later, the bias block BLKB has the same configuration as the normal block BLK, that is, components and connections of the components. On the other hand, the bias block BLKB is not used for storing data but for applying and (or) transferring a voltage to a certain component.

[0062] 1.1.3. Circuit structure of memory cell array

[0063] Figure 3 FIG. 1 shows components of one block BLK of the storage device according to the first embodiment and connections between the components. A plurality of blocks BLK, for example, all blocks BLK include Figure 3 The components and connections shown in the figure. The normal block BLK and the offset block BLKB both include Figure 3 The components and connections shown.

[0064] The block BLK includes a plurality of string units SU. Figure 3An example of five string units SU_0 to SU_4 is shown.

[0065] like Figure 3 As shown, each of the m bit lines BL_0 to BL_m-1 is connected to one NAND string NS of each string unit SU_0 to SU_4 from each block BLK. m is a positive integer. Each bit line BL is shared by all blocks BLK in each plane PLN, that is, it is common to all blocks BLK in each plane PLN.

[0066] Each NAND string NS includes a selection gate transistor ST, n-1 memory cell transistors MT, and a selection gate transistor DT (DT0, DT1, DT2, DT3 or DT4). n is a positive integer. The memory cell transistor MT is an element that includes a control gate electrode and a charge storage film insulated from the surroundings and stores data in a non-volatile manner based on the amount of charge in the charge storage film. The selection gate transistor ST, the memory cell transistor MT, and the selection gate transistor DT are connected in series between a source line SL and a bit line BL in this order. The source line SL is shared by all blocks BLK in each plane PLN, that is, it is common to all blocks BLK in each plane PLN.

[0067] A plurality of NAND strings NS connected to different bit lines BL constitute a string unit SU. In each string unit SU, the control gate electrodes of the memory cell transistors MT_0 to MT_n-1 are connected to the word lines WL_0 to WL_n-1, respectively. A group of memory cell transistors MT sharing a word line WL in a string unit SU is called a cell unit CU.

[0068] The selection gate transistors DT0 to DT4 belong to the string units SU_0 to SU_4 respectively. Figure 3 The select gate transistors DT2, DT3 and DT4 are not shown in the figure. The gate of the select gate transistor DT0 of each of the multiple NAND strings NS of the string unit SU_0 is connected to the select gate line SGDL_0. Similarly, the gates of the select gate transistors DT1, DT2, DT3 and DT4 of each of the multiple NAND strings NS of the string units SU_1, SU_2, SU_3 and SU_4 are connected to the select gate lines SGDL_1, SGDL_2, SGDL_3 and SGDL_4.

[0069] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0070] 1.1.4. Voltage generation circuit

[0071] Figure 4 2 shows the voltage output from the voltage generating circuit of the first embodiment. Figure 4As shown, the voltage generating circuit 14 generates and outputs a ground voltage VSS, a power supply voltage VDDSA, a programming selection voltage VSGD, a programming selection voltage VSGS, a programming voltage VPGM, a programming pass voltage VPASS, a read selection voltage VSG, a read voltage VCG, a read pass voltage VREAD, a read bias voltage VCELSRC, a read bias voltage VBL, an erase voltage VERA, an erase voltage transfer voltage VERAH, an erase selection voltage VSGE, and an erase bias voltage VWLE from the voltage supplied to the storage device 1.

[0072] The ground voltage VSS is, for example, 0 V. The power supply voltage VDDSA is higher than 0V.

[0073] The program selection voltage VSGD is higher than 0 V. When the program selection voltage VSGD is applied to the gate of the selection gate transistor DT connected to the bit line BL receiving a low voltage and a high voltage used for data writing, the selection gate transistor DT is maintained OFF and ON, respectively.

[0074] The program selection voltage VSGS is higher than 0 V. When the program selection voltage VSGS is applied to the gate of the selection gate transistor ST, the selection gate transistor ST is maintained off even if a voltage exceeding 0 V used in data writing is applied to the source line SL.

[0075] The program voltage VPGM is higher than 0 V and has a variable magnitude. When the program voltage VPGM is applied to the gate electrode of the memory cell transistor MT, it has a magnitude that causes electrons to enter the charge storage film of the memory cell transistor MT.

[0076] The program pass voltage VPASS is lower than the program voltage VPGM. The program pass voltage VPASS has a magnitude that turns on the memory cell transistor MT to which no data is written and suppresses electrons from entering the charge storage film of the memory cell transistor MT to which no data is written.

[0077] The read selection voltage VSG is higher than 0 V. The read selection voltage VSG has a magnitude that enables a current used for data reading to flow through the select gate transistors DT and ST when applied to the gates of the select gate transistors DT and ST.

[0078] The read voltage VCG is higher than 0 V, and has a variable magnitude determined based on the type of data read.

[0079] The read pass voltage VREAD has a magnitude that, when applied to the gate of the memory cell transistor MT, keeps the memory cell transistor MT turned on regardless of the state of the memory cell transistor MT, and is higher than the read voltage VCG.

[0080] The read bias voltage VCELSRC is higher than 0 V. The read bias voltage VBL is higher than the read bias voltage VCELSRC.

[0081] The erase voltage VERA is higher than 0 V and higher than the program voltage VPGM and the read pass voltage VREAD. The erase voltage VERA has a magnitude capable of supplying holes to the semiconductor in the NAND string NS when applied to the source line SL and / or the bit line BL.

[0082] The erase voltage transfer voltage VERAH is higher than the erase voltage VERA. The erase voltage transfer voltage VERAH has a magnitude that enables the memory cell transistor MT and the selection gate transistors DT and ST that receive the erase voltage transfer voltage VERAH at their gates to transfer the erase voltage VERA.

[0083] The erase selection voltage VSGE is higher than 0 V. The erase selection voltage VSGE has a magnitude capable of generating GIDL (Gate Induced Drain Leakage) in the select gate transistors ST and (or) DT when being applied to the source line SL and (or) the bit line BL, respectively.

[0084] The erase bias voltage VWLE has a magnitude that enables holes to enter the charge storage film of the memory cell transistor MT when applied to the gate of the memory cell transistor MT. The erase bias voltage VWLE has, for example, the same magnitude as the ground voltage VSS, for example, 0 V. The erase bias voltage VWLE may also be less than 0V.

[0085] 1.1.5. Driver

[0086] Figure 5 The components of the driver according to the first embodiment and the connection between the components are shown.

[0087] like Figure 5 As shown, the driver 15 includes the same number of driver circuits SGDdr (SGDdr_0~SGDdr_4) as the number of string units SU included in a block BLK, driver circuits SGSdr, the same number of driver circuits CGdr (CGdr_0~CGdr_n-1) as the number of word lines WL included in a NAND string NS, and driver circuits BLKBdr.

[0088] The driver circuits SGDdr_0 to SGDdr_4 receive the ground voltage VSS, the program selection voltage VSGD, the read selection voltage VSG, and the erase selection voltage VSGE from the voltage generation circuit 14. The driver circuits SGDdr_0 to SGDdr_4 supply one of the received voltages instructed by the sequencer 13 to the wirings SGD_0 to SGD_4, respectively.

[0089] Driver circuits CGdr_0 to CGdr_n-1 receive program voltage VPGM, program pass voltage VPASS, read voltage VCG, read pass voltage VREAD, and erase bias voltage VWLE from voltage generation circuit 14. Driver circuits CGdr_0 to CGdr_n-1 supply one of the received voltages instructed by sequencer 13 to wirings CG_0 to CG_n-1, respectively.

[0090] The driver circuit SGSdr receives the program selection voltage VSGS, the read selection voltage VSG, and the erase selection voltage VSGE from the voltage generation circuit 14. The driver circuit SGSdr supplies one of the received voltages instructed by the sequencer 13 to the wiring SGS.

[0091] The driver circuit BLKBdr receives the erase voltage transfer voltage VERAH from the voltage generation circuit 14. Based on the instruction of the sequencer 13, the driver circuit BLKBdr supplies the erase voltage transfer voltage VERAH to the wiring BLKBI.

[0092] 1.1.6. Block Decoder

[0093] Figure 6 The components of the row decoder according to the first embodiment and the connections between the components are shown. Figure 6 Block BLK is also shown.

[0094] The row decoder 11 includes the same number of block decoders 111 as the number of normal blocks BLKO and the same number of transfer switch groups 112 as the number of normal blocks BLKO.

[0095] The block decoder 111 is a circuit that decodes the address information ADD and outputs a block selection signal BSS on the wiring BSSL based on the result of the decoding, and outputs a signal ￣BSS on the wiring ￣BSSL. The signal ￣BSS has an inverted logic of the logic of the block selection signal BSS.

[0096] Each block decoder 111 is associated with a normal block BLKO. Each block decoder 111 performs control for setting the associated normal block BLKO to a selected state. When the address information ADD specifies the normal block BLKO associated with itself, the block decoder 111 outputs an asserted block selection signal BSS.

[0097] Each transfer switch group 112 is a group of multiple transfer switches XS and multiple transfer switches XSB. Each transfer switch group 112 is associated with a normal block BLKO. Each transfer switch group 112 sets the normal block BLKO associated with itself to a selected state based on the block selection signal BSS. Each transfer switch XS is, for example, an n-type MOSFET. The four transfer switches XS are respectively connected between the wiring SGD_0 to SGD_4 and the selection gate lines SGDL_0 to SGDL_4. The n transfer switches XS are respectively connected between the wiring CG_0 to CG_n-1 and the word lines WL_0 to WL_n-1. One transfer switch XS is connected between the wiring SGS and the selection gate line SGSL. Each transfer switch XS receives the block selection signal BSS at its own gate.

[0098] Each transfer switch XSB is, for example, an n-type MOSFET. The four transfer switches XSB are connected between wirings SGDU_0 to SGDU_4 and selection gate lines SGDL_0 to SGDL_4, respectively. Wirings SGDU_0 to SGDU_4 receive ground voltage Vss from voltage generation circuit 14 or from voltage generation circuit 14 via driver 15. Each transfer switch XSB receives signal ￣BSS at its gate.

[0099] When a block selection signal BSS is asserted, the transfer switch XS receiving the block selection signal BSS is turned on. As a result, the voltages of the wirings SGD, CG, and SGS are respectively transmitted to the selection gate line SGDL, the word line WL, and the selection gate line SGSL of the selected block BLK. On the other hand, during the period when the block BLK is not selected, the signal ￣BSS for the block BLK is asserted. As a result, in the unselected block BLK, the transfer switch XSB is turned on. Therefore, the selection gate lines SGDL_0 to SGDL_4 receive the ground voltage VSS via the wirings SGDU_0 to SGDU_4, respectively.

[0100] Thus, the normal block BLKO is connected to the driver 15 via the row decoder 11. On the other hand, the bias block BLKB is connected to the driver 15 without passing through the row decoder 11. That is, the selection gate line SGDL, word line WL, and selection gate line SGSL of the bias block BLKB are connected to the wiring BLKBI connected to the driver 15.

[0101] 1.1.5. Storage Cell Array

[0102] Figure 7 The cross-sectional structure of a part of the memory cell array of the memory device according to the first embodiment is shown, and the structure along the yz plane is shown.

[0103] like Figure 7 As shown, the memory cell array 10 includes conductors 21 and 22, n conductors 23, conductors 24 and 27, and insulators 33 to 36. The insulators 33 to 36 contain silicon oxide or are formed of silicon oxide, for example.

[0104] The conductor 21 extends along the xy plane and has a plate-like shape. The conductor 21 functions as at least a part of the source line SL. The conductor 21 contains, or is formed of, silicon doped with phosphorus, for example, and has an n-type conductivity.

[0105] The insulator 33 is located on the upper surface of the conductor 21 .

[0106] The conductor 22 is located on the upper surface of the insulator 33. The conductor 22 extends along the xy plane and has a plate-like shape. The conductor 22 functions as at least a part of the selection gate line SGSL. The conductor 22 contains tungsten or is formed of tungsten, for example.

[0107] The plurality of insulators 34 and the plurality of conductors 23 are arranged one by one on the upper surface of the conductor 22 in an alternating manner along the z-axis. Thus, the conductors 23 are arranged along the z-axis with intervals between them. The insulators 34 and the conductors 23 extend along the xy plane and have a plate-like shape. The plurality of conductors 23 function as at least a part of the word lines WL_0 to WL_n-1 in order from the conductor 21 side. The conductors 23 contain tungsten, for example, or are formed of tungsten.

[0108] The insulator 35 is located on the upper surface of the uppermost conductor 23 .

[0109] The conductor 24 is located on the upper surface of the insulator 35. The conductor 24 functions as at least a part of one of the selection gate lines SGDL_0 to SGDL_4. The conductor 24 contains tungsten or is formed of tungsten.

[0110] The insulator 36 is located on the upper surface of the conductor 24 .

[0111] The conductor 26 is located on the upper surface of the insulator 36. The conductor 26 has a linear shape and extends along the y-axis. The conductor 26 functions as at least a portion of a bit line BL. Figure 7The conductors 26 are also provided in a yz plane different from the yz plane shown, so that the conductors 26 are arranged at intervals along the x-axis. The conductors 26 contain copper or are formed of copper, for example.

[0112] The storage column MP extends along the z-axis and has a column shape. The storage column MP is located in a stacked structure formed by insulators 33 to 36 and conductors 22 to 24, and penetrates or passes through the insulators 33 to 36 and the conductors 22 to 24. The upper surface of the storage column MP is located above the uppermost conductor 24. The lower surface of the storage column MP is in contact with the conductor 21. The portion of the storage column MP in contact with the conductor 22 functions as a selection gate transistor ST. The portion of the storage column MP in contact with a conductor 23 functions as a storage cell transistor MT. The portion of the storage column MP in contact with the conductor 24 functions as a selection gate transistor DT.

[0113] The memory pillar MP includes, for example, a core 50, a semiconductor 51, a tunnel insulator 53, a charge storage film 54, a block insulator 55, and a conductor 27. The core 50 extends along the z-axis and has a pillar shape. The core 50 is formed of an insulator, for example, containing silicon oxide, or is formed of silicon oxide.

[0114] The semiconductor 51 covers the surface of the core 50. The semiconductor 51 is in contact with the conductor 21 at the lower surface. The semiconductor 51 functions as a channel (current path) of the memory cell transistor MT and the selection gate transistors DT and ST. The semiconductor 51 contains silicon or is formed of silicon, for example.

[0115] The tunnel insulator 53 surrounds the side surfaces of the semiconductor 51. The tunnel insulator 53 contains silicon oxide or is formed of silicon oxide, for example.

[0116] The charge storage film 54 surrounds the side surfaces of the tunnel insulator 53. The charge storage film 54 contains, for example, silicon nitride or is formed of silicon nitride.

[0117] The blocking insulator 55 surrounds the side surface of the charge storage film 54. The side surface of the blocking insulator 55 is surrounded by the conductor 23. The blocking insulator 55 contains silicon oxide, or is formed of silicon oxide, for example.

[0118] The structure of the storage column MP is not limited to Figure 7 For example, the region including the bottom surface of the memory column MP may also be located in the conductor 21. In this case, the tunnel insulator 53, the charge storage film 54, and the group of the charge storage film 54 are partially opened in the conductor 21. The conductor 21 is in contact with the semiconductor 51 by the material of the conductor 21 being located in the opening.

[0119] The conductor 25 is located on the upper surface of the core 50 and the semiconductor 51. The conductor 25 contains silicon doped with phosphorus, or is formed of silicon doped with phosphorus, for example.

[0120] One memory column MP is connected to one conductor 25 via a conductor 27 .

[0121] Figure 7 The structure around the structure shown may be any structure. For example, the conductor 21 is located above the substrate, and the circuits such as the row decoder 11, the driver 15, and (or) the sense amplifier 17 are formed in the area including the upper surface of the substrate. The circuit may be provided below the storage column MP described later in the upper surface of the substrate, or may be provided in an area different from below the area where the storage column MP is provided in the upper surface of the substrate.

[0122] Alternatively, the storage device 1 may also include a Figure 7 The structure shown is an upper structure inverted along the xy plane. That is, the storage device 1 includes a substrate and a lower structure including a circuit formed in a region including the upper surface of the substrate. Figure 7 In the structure shown, the structure formed by inverting the structure with respect to the xy plane is joined to the lower structure as the upper structure. Then, the substrate used to form the upper structure is removed.

[0123] Figure 8 The impurity concentration distribution of a part of the storage device according to the first embodiment is shown. Figure 8 In part (a), the enlarged view shows Figure 7 The area RA is shown. Figure 8 Part (b) shows the concentration distribution of impurities contained in the portion shown in part (a) of the semiconductor 51 .

[0124] As shown in part (b), the region of the semiconductor 51 including the end portion on the conductor 21 side is doped with phosphorus as an impurity, for example. Since phosphorus is contained, the region of the semiconductor 51 including the end portion on the conductor 21 side has an n-type conductivity. The doped impurity is not limited to phosphorus. For example, arsenic may also be doped.

[0125] Phosphorus is distributed as follows. That is, the portion of the semiconductor 51 that is within the range of a distance D from the interface with the conductor 21 toward the conductor 22 contains, for example, 1×10 19 atoms / cm 3 The portion of the semiconductor 51 extending from the interface with the conductor 21 toward the conductor 22 beyond the distance D contains, for example, less than 1×10 19 atoms / cm 3The distance D is larger than the distance from the interface between the semiconductor 51 and the conductor 21 to the lower surface of the conductor 22 and smaller than the distance from the interface between the semiconductor 51 and the conductor 21 to the upper surface of the conductor 22.

[0126] With such an impurity concentration distribution, the channel of the select gate transistor ST includes phosphorus at a concentration of 1×10 19 atoms / cm 3 The above part. Thus, the selection gate transistor ST can generate a GIDL current in the semiconductor 51. The GIDL current generates electron-hole pairs. The holes of the generated electron-hole pairs are injected into the charge storage film 54 and can recombine with the electrons entering the charge storage film 54. Through the recombination, the negative charge disappears from the charge storage film 54. Due to the disappearance of the negative charge, the threshold voltage of the memory cell transistor MT is reduced. That is, the data stored in the memory cell transistor MT is erased. Hereinafter, the GIDL current flowing from the source line SL to the selection gate transistor DT is sometimes referred to as the SL-side GIDL current.

[0127] In addition, the channel of the select gate transistor ST includes phosphorus at a concentration lower than 1×10 19 atoms / cm 3 Thus, the selection gate transistor ST also functions as a switch that controls the connection and disconnection between the source line SL (conductor 21) and the memory cell transistor MT_0 during data writing and data reading.

[0128] The semiconductor 51 also contains impurities such as phosphorus in the portion of the selection gate transistor DT, similarly to the portion of the selection gate transistor ST. Fig. 9 The impurity concentration distribution of a part of the storage device according to the first embodiment is shown. Fig. 9 In part (a), the enlarged view shows Figure 7 The area RB is shown. Fig. 9 Part (b) shows the concentration distribution of impurities contained in the portion shown in part (a) of the semiconductor 51 and the conductor 25 .

[0129] As shown in part (b), the region of the end portion of the group of semiconductor 51 and conductor 25 including the conductor 27 (not shown) side (upper side) is doped with, for example, phosphorus as an impurity. Due to the inclusion of phosphorus, the region of the end portion of the group of semiconductor 51 and conductor 25 including the conductor 27 side has an n-type conductivity. The doped impurity is not limited to phosphorus. For example, arsenic may also be doped.

[0130] Phosphorus is distributed as follows. That is, the portion of the semiconductor 51 and the conductor 25 group that is within the range of the distance D from the upper surface of the conductor 25 toward the conductor 24 contains, for example, 1×10 19atoms / cm 3 The portion of the semiconductor 51 and the conductor 25 extending from the upper surface of the conductor 25 toward the conductor 24 beyond the distance D contains, for example, less than 1×10 19 atoms / cm 3 The distance D is larger than the distance from the upper surface of the conductor 25 to the upper surface of the conductor 24 , and smaller than the distance from the upper surface of the conductor 25 to the lower surface of the conductor 24 .

[0131] With such an impurity concentration distribution, the channel of the select gate transistor DT includes phosphorus at a concentration of 1×10 19 atoms / cm 3 As a result, the select gate transistor DT can generate a GIDL current in the semiconductor 51 and the conductor 25. Holes can be generated by the GIDL current. Hereinafter, the GIDL current flowing from the bit line BL to the select gate transistor DT may be referred to as a BL-side GIDL current.

[0132] In addition, the channel of the select gate transistor DT includes phosphorus at a concentration lower than 1×10 19 atoms / cm 3 Therefore, the selection gate transistor DT also functions as a switch that controls the connection and disconnection between the bit line BL (conductor 26) and the memory cell transistor MT_n-1 during data writing and data reading.

[0133] 1.2. Action

[0134] 1.2.1. Data erasure

[0135] Fig.10 The following shows voltages applied to several wirings during data erasure (data erasing operation) in the storage device according to the first embodiment. Fig.10 The offset block BLKB, the non-selection block BLKns, and the selection block BLKs are shown. The selection block BLKs is a data erasure target block BLK in the normal block BLKO. The non-selection block BLKns is a block BLK other than the selection block BLKs in the normal block BLKO.

[0136] The block decoder 111 connected to the selected block BLKs is activated, that is, all the transfer switches XS in the activated block decoder 111 are turned on. On the other hand, the block decoder 111 connected to the non-selected block BLKns is not activated, that is, all the transfer switches XS in the non-activated block decoder 111 are turned off.

[0137] The source line SL receives the erase voltage VERA through the voltage generating circuit 14 and the driver 15. Figure 3As described above, the source line SL is connected to each block BLK, that is, the bias block BLKB, the non-selection block BLKns, and the selection block BLKs. Therefore, in any of the bias block BLKB, the non-selection block BLKns, and the selection block BLKs, the source line SL has the potential VERA.

[0138] All the selection gate lines SGDL (SGDL_0 to SGDL_4), all the word lines WL (WL_0 to WL_n-1) and the selection gate line SGSL of the bias block BLKB receive the erase voltage transfer voltage VERAH from the driver 15. Therefore, all the selection gate transistors DT, all the memory cell transistors MT and the selection gate transistor ST of the bias block BLKB are in a state of being turned on and capable of transmitting the erase voltage VERA.

[0139] All the selection gate transistors DT, all the memory cell transistors MT, and all the selection gate transistors ST of the bias block BLKB are in a state of being turned on and capable of transmitting the erase voltage VERA. Thus, any bit line BL is electrically connected to the source line SL via the NAND string NS connected to the bit line BL and including the selection gate transistors DT and ST in a state capable of transmitting the erase voltage VERA and the memory cell transistor MT. And the source line SL receives the erase voltage VERA. Therefore, each bit line BL receives the erase voltage VERA via the NAND string NS connected to the bit line BL, and receives charging based on the erase voltage VERA. During data erasure, each bit line BL does not receive voltage from the sense amplifier 17, nor is it connected to any other node via a turned-on transistor.

[0140] The block decoder 111 connected to any non-selected block BLKns is also in an inactive state. Therefore, in each non-selected block BLKns, all select gate lines SGDL, all word lines WL, and select gate line SGSL are electrically floating. As a result, the select gate transistors DT and ST and the memory cell transistor MT of the non-selected block BLKns are turned off.

[0141] Since the block decoder 111 connected to the selection block BLKs is in an activated state, the selection block BLKs receives a voltage from each driver circuit SGDdr (SGDdr_0 to SGDdr_4). Each driver circuit SGDdr outputs an erase selection voltage VSGE. Thus, each selection gate line SGDL receives the erase selection voltage VSGE.

[0142] Since the block decoder 111 connected to the selection block BLKs is in an activated state, the selection block BLKs receives a voltage from each driver circuit CGdr (CGdr_0 to CGdr_n-1). In addition, each driver circuit CGdr outputs an erase bias voltage VWLE. Thus, each word line WL receives the erase bias voltage VWLE.

[0143] The block decoder 111 connected to the selection block BLKs is in an active state, so the selection block BLKs is in a state of receiving a voltage from the driver circuit SGSdr. In addition, the driver circuit SGSdr outputs the erase selection voltage VSGE. As a result, the selection gate line SGSL receives the erase selection voltage VSGE.

[0144] Fig.11 The edge time indicates voltages applied to several wirings during the data erasing period in the memory device of the first embodiment. Fig.11 The bias block BLKB and the selection block BLKs are shown among the bias block BLKB, the non-selection blocks BLKns, and the selection blocks BLKs.

[0145] like Fig.11 As shown, in Fig.11 At the start time point of the range shown, the ground voltage VSS is applied to any wiring.

[0146] From time t1, the erase voltage transfer voltage VERAH is applied to the selection gate line SGDL, the word line WL, and the selection gate line SGSL of the bias block BLKB. In addition, from time t1, the erase voltage VERA is applied to the source line SL. The application of the erase voltage VERA may also precede the application of the erase voltage transfer voltage VERAH. By applying the erase voltage VERA and the erase voltage transfer voltage VERAH, the voltage of the source line SL is transferred in the bias block BLKB from time t1, thereby applying the erase voltage VERA to the bit line BL.

[0147] From time t2, an erase selection voltage VSGE is applied to the selection gate line SGSL of the selection block BLKs. As a result, from time t2, an erase voltage VERA is applied to the source line SL and an erase selection voltage VSGE is applied to the selection gate line SGSL. By such voltage application, the SL-side GIDL current flows from the selection gate transistor ST to the inner side of the NAND string NS. Electron-hole pairs are generated by the SL-side GIDL current.

[0148] In addition, from time t2, the erase voltage VERA is applied to each bit line BL and the erase selection voltage VSGE is applied to each selection gate line SGDL. By such voltage application, the BL side GIDL current flows from the selection gate transistor DT to the inner side of the NAND string NS. Electron-hole pairs are generated by the BL side GIDL current.

[0149] The holes generated by the BL-side GIDL current and the SL-side GIDL current move in the semiconductor 51 toward the inner side (the center of the NAND string NS) of the memory cell transistor MT connected in series. The word line WL of the selection block BLKs continues to receive the erase bias voltage VWLE. Therefore, the holes in the semiconductor 51 are attracted by the erase bias voltage VWLE applied to the word line WL and invade the charge storage film 54. The invading holes recombine with the electrons in the charge storage film 54. Through the recombination, the electrons in the charge storage film 54 disappear, and the amount of electrons in the charge storage film 54 decreases. As a result, the threshold voltage of the memory cell transistor MT of the selection block BLKs is lowered, and the data is erased.

[0150] From time t3 , the ground voltage VSS is applied to the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB and the selection gate lines SGDL and SGSL of the selection block BLKs.

[0151] 1.2.2. Data Writing

[0152] Fig.12 The following diagram shows voltages applied to several wirings during data writing (data writing operation) in the memory device according to the first embodiment.

[0153] During data writing, the driver circuits SGDdr_0 to SGDdr_4 output the programming selection voltage VSGD or the ground voltage VSS. Sometimes, the string cells SU of the cell group CU including the access object of data writing or data reading in the selection block BLKs among the five string cells SU included in each block BLK are referred to as selection string cells SUs. Sometimes, the string cells SU other than the selection string cells SUs are referred to as non-selection string cells SU. The driver circuit SGDdr connected to the selection string cell SUs outputs the programming selection voltage VSGD. The driver circuit SGDdr connected to the non-selection string cell SU outputs the ground voltage VSS.

[0154] During data writing, the driver circuit CGdrv outputs a program voltage VPGM or a program pass voltage VPASS. Data writing includes multiple program loops, and the program voltage VPGM has different magnitudes in different program loops.

[0155] During data writing, the driver circuit SGSdr outputs a program selection voltage VSGS.

[0156] Each bit line BL receives the ground voltage VSS or the power supply voltage VDDSA through the sense amplifier 17. The bit line BL connected to the NAND string (selection NAND string) NS including the memory cell transistor MT whose threshold voltage is increased by data writing receives the ground voltage VSS. The bit line BL connected to the NAND string (non-selection NAND string) NS including the memory cell transistor MT whose threshold voltage is not increased by data writing receives the power supply voltage VDDSA.

[0157] The source line SL receives the power supply voltage VDDSA through the driver 15 .

[0158] It is required that the bias block BLKB does not participate in data writing and does not hinder data writing in the selection block BLKs. For this purpose, during data reading, each selection gate line SGDL, each word line WL and the selection gate line SGSL of the bias block BLKB are electrically floating. This can be done, for example, by electrically disconnecting the node in the driver circuit BLKBdr from the wiring BLKBI. The selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB are electrically floating, so the selection gate transistors DT and ST of the bias block BLKB and the memory cell transistor MT are turned off.

[0159] The block decoder 111 connected to any non-selected block BLKns is in an inactive state. Therefore, in each non-selected block BLKns, each select gate line SGDL receives the ground voltage VSS, and each word line WL and select gate line SGSL are electrically floating. Therefore, the select gate transistors DT and ST and the memory cell transistor MT of the non-selected block BLKns are turned off.

[0160] On the other hand, the selection block BLKs receives voltages from the driver circuits SGDdr, CGdr, and SGSdr via the block decoder 111 connected to the selection block BLKs. Thus, the selection gate line SGDL of the selection block BLKs receives the programming selection voltage VSGD or the ground voltage VSS. In addition, the word line WL of the selection block BLKs receives the programming voltage VPGM or the programming pass voltage VPASS. In addition, the selection gate line SGSL of the selection block BLKs receives the programming selection voltage VSGS.

[0161] By applying the voltage as described above, data is written to the cell group CU of the selected block BLKs. The selection gate transistor DT of the selected NAND string NS is turned on, and electrons are supplied from the bit line BL to the semiconductor 51 of the selected NAND string NS. The electrons are attracted by the programming voltage VPGM and injected into the charge storage film 54 of the storage cell transistor MT in the selected NAND string NS and the cell group CU where data is written. On the other hand, the selection gate transistor DT of the non-selected NAND string NS is not turned on. Thus, the supply of electrons from the bit line BL to the semiconductor 51 of the non-selected NAND string NS is suppressed. Therefore, the injection of electrons into the charge storage film 54 of the storage cell transistor MT in the selected NAND string NS and the cell group CU where data is written is suppressed.

[0162] 1.2.2. Data Reading

[0163] Fig.13 The following diagram shows voltages applied to several wirings during data reading (data reading operation) in the memory device according to the first embodiment.

[0164] During data reading, the driver circuit SGDdr connected to the selected string unit SUs outputs a read selection voltage VSG, and the driver circuit SGDdr connected to the non-selected string unit SU outputs a ground voltage VSS.

[0165] During data reading, the driver circuit CGdrv outputs a read voltage VCG or a read pass voltage VREAD.

[0166] During data reading, the driver circuit SGSdr outputs a program selection voltage VSGS.

[0167] The source line SL receives a read bias voltage VCELSRC through the driver 15. Each bit line BL receives a read bias voltage VBL through the sense amplifier 17.

[0168] It is required that the bias block BLKB does not participate in data reading and does not hinder data reading in the selection block BLKs. For this purpose, during data reading, each selection gate line SGDL, each word line WL and the selection gate line SGSL of the bias block BLKB are electrically floating. The selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB are electrically floating, so the selection gate transistors DT and ST of the bias block BLKB and the memory cell transistor MT are turned off.

[0169] The block decoder 111 connected to any non-selected block BLKns is in an inactive state. Therefore, in each non-selected block BLKns, each select gate line SGDL receives the ground voltage VSS, and each word line WL and select gate line SGSL are electrically floating. Therefore, the select gate transistors DT and ST and the memory cell transistor MT of the non-selected block BLKns are turned off.

[0170] On the other hand, the selection block BLKs receives voltages from the driver circuits SGDdr, CGdr, and SGSdr via the block decoder 111 connected to the selection block BLKs. As a result, the selection gate line SGDL of the selection block BLKs receives the ground voltage VSS or the read selection voltage VSG, and the selection gate line SGSL of the selection block BLKs receives the read selection voltage VSG. In addition, the word line WL of the selection block BLKs receives the read voltage VCG or the read pass voltage VREAD.

[0171] By applying the voltage as described above, data is read from the cell group CU of the data reading object of the selection block BLKs. By receiving the read selection voltage VSG, the selection gate transistors DT and ST of the selection NAND string NS of the selection block BLKs are turned on. In addition, by receiving the read pass voltage VREAD, the storage cell transistors MT of the cell group CU other than the data reading object cell group CU are turned on. By receiving the read voltage VCG, the storage cell transistors MT in the data reading object cell group CU having a threshold voltage less than the magnitude of the read voltage VCG are turned on. As a result, in the NAND string NS including the storage cell transistor MT having a threshold voltage less than the magnitude of the read voltage VCG, current flows from the bit line BL to the source line SL. On the other hand, even if the read voltage VCG is received, the storage cell transistor MT in the data reading object cell group CU having a threshold voltage greater than the read voltage VCG continues to be cut off. As a result, in the NAND string NS including the storage cell transistor MT having a threshold voltage greater than the read voltage VCG, the flow of current from the bit line BL to the source line SL is suppressed or prevented. Based on whether or not the current flows, the sense amplifier determines the data stored in the cell group CU to be read from.

[0172] 1.3. Advantages (effects)

[0173] According to the first embodiment, as described below, a storage device having a smaller area can be provided.

[0174] In order to erase data, it is necessary to inject holes into each semiconductor of the NAND string. For this purpose, it is necessary to increase the voltage at one end and / or the other end of the NAND string. One end of the NAND string is connected to the source line, and the other end of the NAND string is connected to the bit line. The source line is commonly connected to multiple NAND strings. Therefore, increasing the voltage at one end of multiple NAND strings can be done by increasing the voltage of a source line. As a result, hole generation by increasing the voltage of the source line is relatively easy.

[0175] In order to more efficiently inject holes, the hole injection can be performed by using the voltage increase of the other end of the NAND string. For this purpose, it is necessary to increase the voltage of the bit line. In the storage device, multiple independent bit lines are set. Therefore, when charging the bit line, it is necessary to set a driver circuit for charging the bit line for each bit line. However, since a large number of bit lines are set, setting a driver circuit for each bit line may increase the area of ​​the storage device.

[0176] According to the first embodiment, a bias block BLKB is provided. The bias block BLKB is not used for data storage. However, instead, during data erasing, the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB receive the erase voltage transfer voltage VERAH. Thus, during data erasing, the NAND string NS of the bias block BLKB is in a state capable of transmitting the erase voltage VERA. And, during data erasing, the source line SL receives the erase voltage VERA. The erase voltage VERA of the source line SL is transmitted in the NAND string NS of the bias block BLKB in a state capable of transmitting the erase voltage VERA. As a result, each bit line BL is charged with the erase voltage VERA via the bias block BLKB. Therefore, there is no need to provide a driver circuit for charging the erase voltage VERA for each bit line BL. Thus, a storage device having a small area and capable of performing efficient hole injection using the bit line BL can be provided.

[0177] 1.4. Modifications

[0178] Although an example of using both the BL side GIDL current and the SL side GIDL current is described, only the BL side GIDL current may be used. Alternatively, only the SL side GIDL current may be used. In this case, the region of the semiconductor 51 and the conductor 25 group including the end portion on the conductor 27 side (upper side) is not doped with phosphorus as an impurity.

[0179] Reference Fig. 9 , Fig.11 as well as Fig.12An example is described in which the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB are set to float during data erasing, data writing, and data reading. During one or more of data erasing, data writing, and data reading, one or more of the selection gate lines SGDL and SGSL and the word line WL of the bias block BLKB may receive the ground voltage VSS.

[0180] The example in which the GIDL current is used for data erasure is described. Data erasure is not limited to the use of the GIDL current. In this case, the conductor 21 has a p-type conductivity type, for example, contains silicon doped with boron, or is formed of silicon doped with boron. Thus, by referring to Fig. 9 The application of the overvoltage injects holes not depending on the GIDL current into the semiconductor 51 of the selection block BLKs. Also, holes not depending on the GIDL current are injected into the semiconductor 51 of the selection block BLKs from the bit line BL receiving the erase voltage VERA via the bias block BLKB.

[0181] In each NAND string NS, a plurality of selection gate transistors ST may also be provided between the source line SL and the memory cell transistor MT_0. In this case, a plurality of conductors 22 are provided. Furthermore, the distance D of the range containing high concentration impurities in the semiconductor 51 is greater than the distance from the interface with the conductor 21 to the upper surface of the bottom conductor 22. Thus, the bottom selection gate transistor ST exclusively contributes to the generation of the GIDL current, and the other selection gate transistors ST function as switches.

[0182] In each NAND string NS, a plurality of selection gate transistors DT may also be provided between the source line SL and the memory cell transistor MT_n-1. In this case, a plurality of conductors 24 are provided. Furthermore, the distance D of the range containing high concentration impurities in the semiconductor 51 is greater than the distance from the upper surface of the conductor 25 to the lower surface of the uppermost conductor 24. Thus, the uppermost selection gate transistor DT exclusively contributes to the generation of the GIDL current, and the other selection gate transistors DT function as switches.

[0183] Reference Figure 5An example is described in which one driver circuit BLKBdr is provided, and one driver circuit BLKBdr drives all selection gate lines SGDL, all word lines WL, and selection gate lines SGSL of the bias block BLKB. The selection gate lines SGDL, word lines WL, and selection gate lines SGSL of the bias block BLKB may also be driven by a plurality of driver circuits BLKBdr. In this case, the groups of the selection gate lines SGDL, word lines WL, and selection gate lines SGSL of the bias block BLKB are divided into a plurality of groups, each of which is connected to one driver circuit BLKBdr. Furthermore, all driver circuits BLKBdr output the erase voltage transfer voltage VERAH during data erase.

[0184] The select gate transistors DT and ST and the memory cell transistor MT of the bias block BLKB may be normally-on. Fig.14 , Fig.15 as well as Fig.16 An example of voltage application in such a case is shown in FIG. Fig.14 The following is a diagram showing voltages applied to several wirings during a data erasure period in a memory device according to a modification of the first embodiment. Fig.15 The following is a diagram showing voltages applied to several wirings during a data write period in a memory device according to a modification of the first embodiment. Fig.16 The following mainly describes the voltages applied to several wirings during data reading in a memory device according to a modification of the first embodiment. Fig.10 , Fig.12 as well as Fig.13 The above mentioned approaches are different points.

[0185] like Fig.14 As shown, during data erasing, all selection gate lines SGDL, all word lines WL, and selection gate line SGSL of bias block BLKB receive erasure voltage VERA from driver circuit BLKdr. Since selection gate transistors DT and ST of bias block BLKB and memory cell transistor MT are normally-on, they are in a state capable of transmitting erasure voltage VERA under application of erasure voltage VERA.

[0186] like Fig.15As shown, during the data writing period, the selection gate line SGDL of the bias block BLKB receives the voltage VNG. The voltage VNG has a negative magnitude and has a magnitude that can maintain the selection gate transistor DT to be turned off by being applied to the normally-on selection gate transistor DT. The voltage VNG is generated by the voltage generation circuit 14 and supplied by the driver circuit SGDdr. By receiving the voltage VNG at the gate, the selection gate transistor DT is turned off during the data writing period. Therefore, it is possible to suppress or prevent the current from flowing in the selection gate transistor DT, and further, it is possible to suppress or prevent the bias block BLKB from interfering with the data writing.

[0187] like Fig.16 As shown, during the data reading period, the selection gate line SGDL of the bias block BLKB receives the voltage VNG. By receiving the voltage VNG at the gate, the selection gate transistor DT is turned off during the data reading period. Therefore, it is possible to suppress or prevent the current from flowing in the selection gate transistor DT, and further, it is possible to suppress or prevent the bias block BLKB from interfering with the data reading.

[0188] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and / or their modifications are included in the scope and purpose of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A storage device comprising: 1st wiring; 2nd wiring; a first string, one end of which is connected to the first wiring and the other end of which is connected to the second wiring, comprising a first memory cell transistor; a second string, one end of which is connected to the first wiring and the other end of which is connected to the second wiring, and includes a second memory cell transistor; a first power supply line connected to the gate of the first memory cell transistor via the first transistor and connected to the gate of the second memory cell transistor via the second transistor; a third string, one end of which is connected to the first wiring and the other end of which is connected to the second wiring, and includes a third memory cell transistor; as well as The second power supply line is connected to the gate of the third memory cell transistor and applies a voltage different from that of the first power supply line during data erasing.

2. The storage device according to claim 1, The first string also includes: a first selection transistor between the first memory cell transistor and the first wiring, and a second selection transistor between the first memory cell transistor and the second wiring, The storage device is configured as follows: applying a first voltage to the second wiring, applying a second voltage higher than the first voltage to the second power line, applying a third voltage lower than the first voltage to the gate of the first selection transistor and the gate of the second selection transistor, A fourth voltage lower than the first voltage is applied to the gate of the first memory cell transistor.

3. The storage device according to claim 2, wherein: applying a fifth voltage lower than the first voltage, the second voltage, and the third voltage to the first wiring, applying a sixth voltage higher than the fifth voltage to the second wiring, applying a seventh voltage higher than the fifth voltage to the gate of the first selection transistor, applying an eighth voltage higher than the fifth voltage and lower than the second voltage to the gate of the first memory cell transistor, The second power supply line is electrically floated or the fifth voltage is applied thereto.

4. The storage device according to claim 2, wherein: applying a ninth voltage to the first wiring, applying a tenth voltage lower than the ninth voltage to the second wiring, applying an eleventh voltage to the gate of the first selection transistor and the gate of the second selection transistor, applying a twelfth voltage to the gate of the first memory cell transistor, The second power line is electrically floated or applied with a fifth voltage lower than the tenth voltage.

5. The storage device according to claim 1, The third string also includes: a third selection transistor between the third memory cell transistor and the first wiring, and a fourth selection transistor between the third memory cell transistor and the second wiring, A gate of the third selection transistor and a gate of the fourth selection transistor are connected to the second power supply line.

6. The storage device according to claim 5, The first string also includes: a first selection transistor between the first memory cell transistor and the first wiring, and a second selection transistor between the first memory cell transistor and the second wiring, The storage device is configured as follows: applying a first voltage to the second wiring, applying a second voltage higher than the first voltage to the second power line, applying a third voltage lower than the first voltage to the gate of the first selection transistor and the gate of the second selection transistor, A fourth voltage lower than the first voltage is applied to the gate of the first memory cell transistor.

7. The storage device according to claim 6, wherein: applying a fifth voltage lower than the first voltage, the second voltage, and the third voltage to the first wiring, applying a sixth voltage higher than the fifth voltage to the second wiring, applying a seventh voltage higher than the fifth voltage to the gate of the first selection transistor, applying an eighth voltage higher than the fifth voltage and lower than the second voltage to the gate of the first memory cell transistor, The second power supply line is electrically floated or the fifth voltage is applied thereto.

8. The storage device according to claim 6, wherein: applying a ninth voltage to the first wiring, applying a tenth voltage lower than the ninth voltage to the second wiring, applying an eleventh voltage to the gate of the first selection transistor and the gate of the second selection transistor, applying a twelfth voltage to the gate of the first memory cell transistor, The second power line is electrically floated or applied with a fifth voltage lower than the tenth voltage.

9. The storage device according to claim 1, The third string further comprises: a plurality of third memory cell transistors including the third memory cell transistor and connected in series, The gates of the third memory cell transistors are connected to the second power supply line.

10. The storage device according to claim 9, The first string also includes: a first selection transistor between the first memory cell transistor and the first wiring, and a second selection transistor between the first memory cell transistor and the second wiring, The storage device is configured as follows: applying a first voltage to the second wiring, applying a second voltage higher than the first voltage to the second power line, applying a third voltage lower than the first voltage to the gate of the first selection transistor and the gate of the second selection transistor, A fourth voltage lower than the first voltage is applied to the gate of the first memory cell transistor.

11. The storage device according to claim 10, wherein: applying a fifth voltage lower than the first voltage, the second voltage, and the third voltage to the first wiring, applying a sixth voltage higher than the fifth voltage to the second wiring, applying a seventh voltage higher than the fifth voltage to the gate of the first selection transistor, applying an eighth voltage higher than the fifth voltage and lower than the second voltage to the gate of the first memory cell transistor, The second power supply line is electrically floated or the fifth voltage is applied thereto.

12. The storage device according to claim 10, wherein: applying a ninth voltage to the first wiring, applying a tenth voltage lower than the ninth voltage to the second wiring, applying an eleventh voltage to the gate of the first selection transistor and the gate of the second selection transistor, applying a twelfth voltage to the gate of the first memory cell transistor, The second power line is electrically floated or applied with a fifth voltage lower than the tenth voltage.

13. A storage device comprising: 1st wiring; 2nd wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first memory cell transistor between the first selection transistor and the second selection transistor; a first driver connected to one of the gate of the first selection transistor, the gate of the second selection transistor, and the gate of the first memory cell transistor via a first transistor; a third selection transistor connected to the first wiring; a fourth selection transistor connected to the second wiring; a second memory cell transistor between the third selection transistor and the fourth selection transistor; as well as The second driver is connected to one of the gate of the third selection transistor, the gate of the fourth selection transistor, and the gate of the second memory cell transistor without via a transistor.

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