Zoned wafer processing and hybrid bonding of layers formed on different wafers in semiconductor components

Abstract

A method for forming a semiconductor component includes forming a first set of layers on a first wafer, where one or more layers in the first set include one or more devices of the semiconductor component. The method further includes forming a second set of layers on a second wafer, wherein one or more layers in the second set include connections between one or more of the devices of the semiconductor assembly. The method additionally includes coupling layers in the first set to layers in the second set using a metal-metal hybrid bond.

Description

Background Art

[0001] As the number of components, such as transistors, in a semiconductor assembly increases, the number of layers used to interconnect the components of the semiconductor assembly also increases. Forming a greater number of layers increases the cycle time for semiconductor assembly manufacturing. In addition to increasing the overall time to manufacture a semiconductor assembly, increasing the number of layers interconnecting the components of a semiconductor assembly also increases the likelihood of manufacturing defects occurring when creating the semiconductor assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 It is a cross-sectional view of a conventional manufacturing process of a semiconductor component.

[0003] Figure 2 A process flow for fabricating a semiconductor component including layers connected by hybrid metal-metal bonds is provided according to some implementations.

[0004] Figure 3 A process flow for fabricating a semiconductor component including layers connected by hybrid metal-metal bonds is provided according to some implementations.

[0005] Figure 4 A process flow is provided for manufacturing a semiconductor component including layers connected by a hybrid metal-metal bond and a transition layer according to some implementations.

[0006] Figure 5 is a cross-sectional view of an example coupling of conductive traces in different layers with conductive traces in a transition layer according to some implementations.

[0007] Figure 6 is an example semiconductor component including layers connected by hybrid metal-metal bonds according to some implementations.

[0008] Figure 7 is another example semiconductor component including layers connected by hybrid metal-metal bonds according to some implementations.

[0009] Figure 8 is a cross-sectional view of an example integrated circuit device including a semiconductor component including layers connected by hybrid metal-metal bonds according to some implementations.

[0010] Fig. 9 is an example computing device according to some specific implementations.

[0011] Fig.10 is a flow chart illustrating an example method for fabricating an integrated circuit device component including layers connected by hybrid metal-metal bonds, according to some implementations. DETAILED DESCRIPTION

[0012] As the number of components, such as transistors, included in a semiconductor component increases, the semiconductor component includes more and more layers to connect the various components. For example, the semiconductor component includes various metal interconnect layers to connect the different components. As the number of components increases, the number of metal layers included in the semiconductor component also increases to connect the different components.

[0013] Although increasing the number of interconnect layers (such as metal interconnect layers) enables the power or performance of a semiconductor component to be increased, increasing the number of interconnect layers also increases the cycle time of semiconductor component manufacturing. In addition, increasing the number of interconnect layers increases the likelihood of manufacturing defects resulting from creating the interconnect layers. Additionally, conventional methods for creating interconnect layers subject components of the semiconductor component to heat, so increasing the number of interconnect layers increases the amount of heat exposure of the components of the semiconductor component, which may affect the subsequent performance of the components of the semiconductor component.

[0014] Figure 1 This is a cross-sectional view of the conventional manufacturing process of a semiconductor component. Figure 1 As shown, layers 105-125 are applied to wafer 100. In various implementations, first wafer 100 includes materials such as silicon, silicon dioxide, gallium arsenide, aluminum oxide, or other suitable materials. A subset of layers 105-125 are layers that form devices such as transistors, capacitors, and resistors that form semiconductor components. For example, layers 105 and 110 are layers that form devices that make up the semiconductor components. Other layers applied to wafer 100 include connections between devices that make up the semiconductor components. Figure 1 In the example of , layers 115-125 include connections between devices in the semiconductor component. Layers 115-125 include conductive materials (such as metals) and conductive paths for forming connections between devices. Figure 1 In the embodiment of the present invention, each layer is applied separately, wherein the layers are applied in series. For example, layer 110 is not applied until layer 105 is fully applied to wafer 100. Similarly, layer 115 is not applied until layer 110 is fully applied. As the number of layers 105-125 increases, applying the layers sequentially to wafer 100 in such a manner increases the total time to manufacture semiconductor components. Therefore, increasing the number of connections between devices increases the number of layers 115-125 including connections between devices, thereby increasing the time to manufacture semiconductor components. In addition, the formation of layers 115-125 subjects the existing layers of the semiconductor component to heat, so that increasing the number of interconnect layers increases the amount of heat exposure of the devices in the semiconductor component. Such an increase in heat exposure increases the likelihood of device performance degradation.

[0015] To this end, the present specification sets forth various specific implementations of a method in which a layer group of a semiconductor component is formed on a first wafer, and a second layer group of the semiconductor component is formed on a second wafer. The layers in the second layer group are bonded to the layers in the first layer group by hybrid bonding to form the semiconductor component. As further described herein, forming different layer groups on different wafers allows the methods herein to form different layer groups in parallel rather than forming layers individually in series on a single wafer, thereby reducing overall manufacturing time. Additionally, forming different layer groups on different wafers allows for a reduction in the amount of heat applied to the layers of the device that includes the semiconductor component by forming the layers including the device on a different wafer than a wafer on which one or more layers including connections between the devices are formed.

[0016] The present specification proposes various specific implementations for forming a semiconductor component, including: forming a first layer group on a first wafer, wherein one or more layers in the first group include one or more devices of the semiconductor component. The method further includes: forming a second layer group on a second wafer, wherein one or more layers in the second group include connections between one or more of the devices of the semiconductor component. The method additionally includes: coupling the layers in the first group to the layers in the second group using metal-metal hybrid bonding.

[0017] In some implementations, the layer in the first group is coupled to one or more conductive traces included in the transition layer using metal-metal hybrid bonding. In some implementations, the layer in the second group is coupled to the one or more conductive traces included in the transition layer using metal-metal hybrid bonding. In some implementations, the spacing of the one or more conductive traces included in the transition layer is different from the spacing of conductive traces included in the layer in the first group. Additionally, in some implementations, the spacing of the one or more conductive traces included in the transition layer is different from the spacing of conductive traces included in the layer in the second group.

[0018] In some implementations, the first layer group includes a layer subgroup, the layer subgroup includes connections between devices of the semiconductor component. In some implementations, the layer in the first group includes a layer in the layer subgroup, the layer includes connections between one or more of the devices of the semiconductor component.

[0019] In some implementations, the layers in the second group include at least one passive component. In some implementations, the passive component includes a capacitor. In some implementations, the capacitor is an ultra-high density metal-insulator-metal capacitor. In some implementations, the passive component includes an inductor.

[0020] The specification also describes a semiconductor device that includes a first layer group, wherein one or more layers in the first group include one or more devices. The semiconductor device further includes a second layer group, wherein the layers in the second group are coupled to the layers in the first group using metal-metal hybrid bonding. The one or more layers in the second group include connections between one or more of the devices.

[0021] In some implementations, the semiconductor device further includes a transition layer, the transition layer including one or more conductive traces, wherein the layer in the first group is coupled to the one or more conductive traces using metal-metal hybrid bonding, and the layer in the second group is coupled to the one or more conductive traces using metal-metal hybrid bonding. In some implementations, the one or more conductive traces included in the transition layer have a spacing different from the spacing of the conductive traces included in the layer in the first group. Additionally, in some implementations, the spacing of the one or more conductive traces included in the transition layer has a spacing different from the spacing of the conductive traces included in the layer in the second group.

[0022] In some implementations, the first layer group includes a layer subgroup, the layer subgroup includes a connection between one or more of the devices. In some implementations, the layer in the first group coupled to the second group using metal-metal hybrid bonding is a layer in the layer subgroup, the layer including a connection between one or more of the devices.

[0023] In some implementations, the layers in the second layer group include at least one passive component. In some implementations, the passive component is a capacitor. In some implementations, the capacitor is an ultra-high density metal-insulator-metal capacitor. In some implementations, the passive component includes an inductor.

[0024] The following disclosure provides many different implementations or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the formation of a first feature on or on a second feature in the following description includes a specific implementation in which the first feature and the second feature are formed as direct contacts, and includes a specific implementation in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are in direct contact. In addition, for ease of description, spatially related terms such as "below", "below", "lower", "above", "upper", "back", "front", "top", "bottom", etc. are used in this article to describe the relationship between an element or feature and another element or feature as illustrated in the accompanying drawings. Similarly, terms such as "front surface" and "rear surface" or "top surface" and "rear surface" are used in this article to more easily identify various components, and identify those components, for example, located on the opposite side of another component. Spatially related terms are intended to include different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings.

[0025] Figures 2 to 4 Steps in an example manufacturing process for a semiconductor component including layers connected by hybrid metal-metal bonds are shown. Figure 2 Initially, layers 205, 210, 215 are applied to a first wafer 200. In various implementations, the first wafer 200 includes materials such as silicon, silicon dioxide, gallium arsenide, aluminum oxide, or other suitable materials. The layers 205, 210, 215 are referred to herein as a first layer group 220, and thus the first layer group 220 is formed on the first wafer 200. One or more layers in the first layer group 220 include devices of a semiconductor component. Example components of the layers included in the first group 220 include transistors, resistors, capacitors, or other suitable devices. Thus, one or more layers in the first group 220 include "front end of line" (FEOL) layers of the semiconductor component, which correspond to layers in a manufacturing process that occurs before forming interconnect layers (such as metal interconnect layers), and are layers during which the devices that make up the semiconductor component are manufactured. Thus, the FEOL layers of the semiconductor component correspond to layers in a manufacturing process that form devices (e.g., transistors, capacitors, resistors, etc.) that make up the semiconductor component.

[0026] In some implementations, one or more layers in the first group 220 are optionally "middle of the line" (MOL) layers that include local connections between devices of a semiconductor component (e.g., devices formed in one or more FEOL layers) and one or more interconnect layers between different layers of a semiconductor component. For example, the MOL layers include gate contacts for transistors in one or more FEOL layers and interconnects between different layers. In some implementations, the MOL layers provide connections between devices included in the FEOL layers, wherein the one or more MOL layers allow connections between conductive elements in "back end of the line" (BEOL) layers (as further described below) to allow for tighter spacing between conductive elements in the BEOL layers.

[0027] In some implementations, a subset of the first layer group 220 includes connections between devices, also referred to as "back end of line" (BEOL) layers. Thus, during the manufacturing process, the BEOL layers are formed after the layers that form the devices that make up the semiconductor component (the FEOL layers further described above), where the BEOL layers include one or more connections between the devices that make up the semiconductor component. In various implementations, the BEOL layers begin with a first layer that includes connections between devices, and include subsequent layers that include connections between devices. For example, one or more layers in the first layer group 220 include metal connections that couple the devices of the semiconductor component to each other. In different implementations, the first layer group 220 includes different numbers of layers that include connections between the devices of the semiconductor component. For example, Figure 2 The layer 205 in the example is a FEOL layer of a device including a semiconductor component, Figure 2 The layer 210 in the example is the MOL layer, and Figure 2 Layer 215 in the example of is a BEOL layer that includes connections between devices in layer 205. In another example, Figure 2 Layer 205 in the example includes devices of the semiconductor component, while layer 210 and layer 215 include connections between the devices included in layer 205 .

[0028] like Figure 2 As shown, a second wafer 230 is used in the manufacturing process. The second wafer 230 is separate and different from the first wafer 200. In various implementations, the second wafer 230 includes a material such as silicon, silicon dioxide, gallium arsenide, aluminum oxide, or other suitable materials. In some implementations, the second wafer 230 and the first wafer 200 are a common material, while in other implementations, the second wafer 230 and the first wafer 200 are different materials.

[0029] Layers 235, 240, and 245 are formed on the second wafer 230, and the layers 235, 240, and 245 form a second layer group 250 on the second wafer 230. In various implementations, one or more layers 235, 240, and 245 in the second group 250 include connections between devices included in one or more layers 205, 210, 215 in the first group 220. Thus, in various implementations, the second group 250 includes one or more BEOL layers. In other implementations, each layer 205, 210, 215 of the second group 250 is a BEOL layer that includes one or more connections between devices of the semiconductor assembly.

[0030] In various implementations, the first layer group 220 is applied to the first wafer 200 while the second layer group 250 is applied to the second wafer 230. Forming the first layer group 220 in parallel on the first wafer 200 and the second layer group 250 in parallel on the second wafer 230 in this manner reduces the time used to form the different layers 205, 210, 215, 235, 240, and 245 compared to a process in which the layers are formed sequentially on a single wafer.

[0031] In some implementations, the number of layers included in the second group 250 is determined to increase the parallel formation of the layers on the second wafer 230 and the layers on the first wafer 200. For example, the first layer group 220 includes a plurality of BEOL layers that include connections between devices of the semiconductor assembly, and the second layer group 250 also includes a plurality of BEOL layers that include connections between devices of the semiconductor assembly. This allows the layers that include connections between devices of the semiconductor assembly to be formed in parallel on the first wafer 200 and the second wafer 230, thereby allowing the total number of layers that include connections between devices to be increased while reducing the time for forming the total number of layers that include connections compared to a technique that forms each layer that includes connections in series on a single wafer, as further described above. In other implementations, the FEOL layers that constitute the devices of the semiconductor assembly are formed on the first wafer 200, while the BEOL layers that include connections between devices in the FEOL layers are formed on the second wafer 230. Forming devices on the first wafer 200 and forming connections between the devices on the second layer 230 in such a manner reduces the amount of heat applied to the devices during the formation of the connections between the devices, thereby preventing device performance degradation due to heat exposure.

[0032] In some implementations, the layers in the second layer group 250 include a layer subgroup that includes connections between devices of semiconductor components, while the layers in the first layer group 230 include another layer subgroup that includes connections between devices of semiconductor components. In some implementations, the layer subgroup that includes connections between devices of semiconductor components includes a connection spacing that is different from the other layer subgroups. Therefore, in various implementations, the first layer group 230 includes layers having one or more connection spacings that meet one or more standards, while the second layer group 250 includes layers having one or more connection spacings that meet one or more alternative standards. However, in other implementations, including layers that include connections between devices in the first layer group 230 in the layers of the second layer group 250 is based on other standards.

[0033] exist Figure 3 , the layers formed on the second wafer 230 in the second layer group 250 are coupled to the layers formed on the first wafer 200 in the first layer group 220. For ease of explanation, Figure 3 Layer 245 in the second layer group 250 is shown coupled to layer 215 in the first layer group 220. Thus, in some implementations, the most recently formed layer in the second layer group 250 is coupled to the most recently formed layer in the first layer group 220. In various implementations, layer 245 in the second layer group 250 includes connections between devices of the semiconductor component, while layer 215 in the first layer group 220 includes additional connections between devices of the semiconductor component; thus, in some implementations, layer 245 and layer 215 are both BEOL layers. The layers in the second group 250 are coupled to the layers in the first group 220 via metal-metal hybrid bonding. For example, the metal-metal hybrid bonding includes a dielectric bond having an embedded connecting material (e.g., a metal), wherein the embedded connecting material is coupled to one or more connecting traces in the layer in the first group 220 and is coupled to one or more connecting traces in the layer in the second group 250. For ease of illustration, Figure 3 Hybrid metal-metal bonds 300 are shown that couple layers 245 in the second layer group 250 to layers 215 in the first layer group.

[0034] Figure 4 An alternative coupling of the layers of the second layer group 250 formed on the second wafer 230 with the layers of the first layer group 220 formed on the first wafer 200 is shown. Figure 4In the example of , the transition layer 400 is formed between a layer in the second layer group 250 formed on the second wafer 230 and a layer in the first layer group 220 formed on the first wafer 200. A surface of the transition layer 400 is bonded to a layer in the second layer group 250, and an opposite surface of the transition layer 400 is bonded to a layer in the first layer group 220, wherein the surface and the opposite surface are parallel to each other and separated by a distance. The transition layer 400 includes conductive traces 405, which include a conductive material (e.g., copper) included in another material (such as a dielectric material). A conductive trace or other connection in a layer in the first group 220 is coupled to a conductive trace 405 in the transition layer 400, and a conductive trace in the transition layer 400 is coupled to another conductive trace or other connection in a layer in the second group 250. In various implementations, the transition layer 400 includes a plurality of conductive traces 405, thereby allowing different conductive traces in a layer in the first group 220 to be coupled to different conductive traces in a layer in the second group 250. Conductive traces 405 in transition layer 400 are coupled to conductive traces in layers in first group 220 using hybrid metal-metal bonds, as further described above. Similarly, conductive traces 405 in transition layer 400 are coupled to conductive traces 405 in layers in second group 250 using hybrid metal-metal bonds to couple conductive traces in layers in first group 220 to conductive traces in layers in second group 250 via conductive traces 405 in transition layer 400.

[0035] Figure 5 A cross-sectional view of an example coupling of conductive traces in different layers with conductive traces in transition layer 400 is shown. For ease of illustration, Figure 5 The layer 215 in the first layer group 220 coupled to the transition layer 400 and the layer 245 in the second layer group 250 coupled to the transition layer 400 are shown. Figure 5 As shown, layer 215 includes conductive trace 500. Similarly, transition layer 400 includes conductive trace, and layer 245 includes conductive trace 510. Figure 5In the illustrated implementation, the spacing between the conductive traces 505 in the transition layer 400 is different from the spacing between the conductive traces 500 in the layer 215 and is different from the spacing between the conductive traces 510 in the layer 245. In other implementations, the spacing between the conductive traces 500 in the layer 215 is different from at least one of the spacing between the conductive traces 500 in the layer 215 and the spacing between the conductive traces 510 in the layer 245. For example, the spacing between the conductive traces 500 in the transition layer 400 is less than the spacing between the conductive traces 500 in the layer 215 and the spacing between the conductive traces 510 in the layer 245. In the foregoing examples, the reduced spacing between the conductive traces 500 in the layer 215 allows the transition layer 400 to fan out the spacing between the conductive traces in one of the layers 215 and 245 to facilitate metal-metal hybrid bonding and then transition back to a spacing corresponding to the spacing between the conductive traces in the layer 215 or the layer 245.

[0036] refer to Figure 6 , depicts an example semiconductor component 600 including layers connected by hybrid metal-metal bonds. Figure 6 In the example shown, the semiconductor component includes a first wafer 200 and a first layer group 220 formed on the first wafer 200. Figure 6 In the example of FIG. 1 , the layer 215 in the first layer group is coupled to the transition layer 400, and the transition layer 400 is coupled to the layer 245 in the second layer group 250 formed on the second wafer 230, as shown in FIG. Figure 2 and Figure 2 As shown. The conductive traces in layer 215 are bonded to the conductive traces in transition layer 400 using a hybrid metal-metal bond, wherein the conductive traces in transition layer 400 are coupled to the conductive traces in layer 245 using a hybrid metal-metal bond. However, in other specific implementations, the conductive traces in layer 215 are directly bonded to the conductive traces in layer 245 using a hybrid metal-metal bond, so that layer 215 is directly bonded to layer 245 without transition layer 400. Since layer 215 is coupled to layer 245, the remaining layers in second layer group 250 are also included in semiconductor component 600. As shown in FIG. Figure 6 As shown, when the semiconductor component 600 after the layer 215 is bonded to the layer 245 , the second wafer 230 on which the second layer group 250 is formed is removed.

[0037] Figure 7 Another example semiconductor component 700 is shown that includes layers connected by hybrid metal-metal bonds. Figure 7, one or more devices 705 constituting the semiconductor component 700 are shown in the layer 205 in the first layer group 220. For example, the device 705 includes one or more transistors. However, in various implementations, one or more of the devices 705 are other components (e.g., resistors, capacitors, etc.). In various implementations, at least one of the devices 705 is an active device (e.g., a transistor, a diode, etc.). In various implementations, different devices 705 are connected to each other through one or more layers in the first layer group 220, through one or more layers in the second layer group 250, or through a combination of layers in the first layer group 220 and the second layer group 250. Therefore, one or more layers in the second layer group 250 include conductive traces configured to be coupled to the one or more devices 705. In some implementations, a subset of the first layer group 220 also includes conductive traces configured to be coupled to the one or more devices 705.

[0038] exist Figure 7 In the illustrated example semiconductor component 700, for ease of illustration, one or more layers in the second layer group 250 include one or more passive components 710. Example passive components 710 include capacitors, resistors, inductors, or other suitable devices. For example, in some implementations, the passive component 710 is a capacitor. In a more specific example, the passive component 710 is an ultra-high density metal-insulator-metal capacitor. However, in different implementations, different passive components 710 or combinations of passive components 710 are included in one or more layers in the second layer group 250. In various implementations, the passive components 710 are connected to each other or to the device 705 through one or more layers in the second layer group 250 or through a combination of layers in the first layer group 220 and the second layer group 250. Therefore, one or more layers in the second layer group 250 include conductive traces configured to be coupled to one or more devices 705 or one or more passive components 710. In some implementations, a subset of the first layer group 220 further includes conductive traces configured to be coupled to one or more devices 705 or to one or more passive components 710. In various implementations, including the passive components 710 in one or more layers in the second group 250 is optional. Including the one or more passive components 710 in one or more layers in the second layer group 250 allows for including the passive components 710 without increasing the cycle time for manufacturing the semiconductor component 700 because the passive components 710 can be included in a layer formed on a different wafer than the wafers that form the devices 705 and the layers in the first layer group 220, as opposed to forming the layers sequentially on a single wafer where the passive components 710 are formed in the last layer of interconnections between the devices of the semiconductor component, which increases the overall time to complete the semiconductor component manufacturing.

[0039] 8 is a cross-sectional view of an example integrated circuit device 800 including a semiconductor component including layers connected by hybrid metal-metal bonds according to some implementations of the present disclosure. The example integrated circuit device 800 can be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, smart phones, etc. (e.g., Fig. 9 shown). Figure 8 The example integrated circuit device 800 includes a die 805. The die 805 is a piece of semiconductor material (such as silicon) on which a functional integrated circuit is fabricated. As an example, the die 805 includes a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or other processors as can be understood. In various specific implementations, the die 805 includes a semiconductor component that includes layers connected by hybrid metal-metal bonds, as described above in conjunction with Figures 2 to 6 Further described.

[0040] As an example, die 805 includes Fig. 9 The processor 905 of the computing device 900 shown. The computing device 900 is implemented as, for example, a desktop computer, a laptop computer, a server, a game console, a smart phone, a tablet computer, etc. In addition to one or more processors 905, the computing device 900 also includes a memory 910. The memory 910 includes a random access memory (RAM) or other volatile memory. The memory 910 also includes non-volatile memory, such as disk storage, solid-state storage, etc.

[0041] In some implementations, the computing device 900 also includes one or more network interfaces 915. In some implementations, the network interface 915 includes a wired network interface 915, such as Ethernet or another wired network connection as will be appreciated. In some implementations, the network interface 915 includes a wireless network interface 915, such as WiFi, Cellular or other wireless network interface 915 as can be understood. In some specific implementations, the computing device 900 includes one or more input devices 920 for accepting user input. Example input devices 920 include keyboards, touch pads, touch screen interfaces, etc. It should be understood by those skilled in the art that in some specific implementations, the input device 920 includes peripheral devices such as external keyboards, mice, etc.

[0042] In some implementations, the computing device 900 includes a display 925. In some implementations, the display 925 includes an external display connected via a video or display port. In some implementations, the display 925 is disposed within a housing of the computing device 900. For example, the display 925 includes a screen of a tablet computer, a laptop computer, a smart phone, or other mobile device. In implementations where the display 925 includes a touch screen, the display 925 also serves as an input device 920.

[0043] The die 805 is coupled to a substrate 810. The substrate 810 is a portion of a material that mechanically supports a coupled component, such as the die 805. In some implementations, the substrate 810 is also electrically coupled to various components mounted to the substrate 810 via conductive traces, tracks, pads, and the like. For example, the substrate 810 electrically couples the components of the die 805 to one or more other components via connecting traces and solder joints formed by solder balls coupled to conductive pads. In some implementations, the substrate 810 includes a printed circuit board (PCB), while in other implementations, the substrate 810 is another semiconductor device, such as the die 805 (which may include active components). In some implementations, the die 805 is coupled to the substrate 810 via a socket (not shown), wherein the die 805 is soldered to the socket or otherwise mounted in the socket. In other implementations, such as Figure 8 As shown, die 805 is directly coupled to substrate 810 via direct solder connections or other connections as will be appreciated. In some implementations, die 805 can be coupled to substrate 810 using land grid array (LGA), pin grid array (PGA), or other packaging technologies as will be appreciated.

[0044] For further explanation, Fig.10 A flow chart illustrating an example method for fabricating an integrated circuit device assembly including layers connected by hybrid metal-metal bonds is presented. Fig.10 The method shown includes forming 1005 a first layer group 220 on a first wafer 200, as described above in conjunction with Figure 2 As shown. One or more layers in the first group 220 include devices that constitute an integrated circuit device component. For example, the layers in the first group 220 include one or more transistors. In various implementations, other devices, such as resistors, capacitors, diodes, inductors, or other devices, are included in the layers in the first group. In various implementations, different devices or combinations of devices that constitute an integrated circuit device component are included in the layers formed 1005 on the first wafer 200. In various implementations, different numbers of layers in the first group 220 include devices that constitute an integrated circuit device component. In some implementations, a subset of the layers in the first group 220 include connections between devices that constitute an integrated circuit device component.

[0045] A second layer group 250 is formed 1010 on a second wafer 230, wherein one or more layers in the second layer group 250 include connections between devices that constitute an integrated circuit device component. The second wafer 230 is different from the first wafer 200, so the first layer group and the second layer group are formed on different wafers. For example, one or more layers in the second group 250 include conductive traces that are configured to couple connections of a device that includes an integrated circuit device component in a layer in the first group 220 to another device included in a layer in the first group 220 (or another device in a different layer of the first group 220). In some specific implementations, the layers in the second group 250 include connections for coupling devices in the layers in the first group 220 to components in the layers in the second group 250. The above is combined with Figure 2 The formation of the second layer group 250 is further described.

[0046] In some implementations, one or more layers in the second group 250 include one or more passive components, as described above in conjunction with Figure 7 As further described. Example passive components include capacitors, resistors, inductors, or other suitable devices. For example, in some implementations, the passive component is a capacitor. In a more specific example, the passive component is an ultra-high density metal-insulator-metal capacitor. However, in different implementations, different passive components or combinations of passive components are included in one or more layers in the second layer group 250. In various implementations, one or more layers in the second group 250 include connections between passive components or connections between passive components and one or more devices included in one or more layers in the first group 220. In some implementations, passive components are included in multiple layers in the second group 250.

[0047] The layers in the second group 250 are coupled 1015 to the layers in the first group 220 using metal-metal hybrid bonding. For example, the metal-metal hybrid bonding includes a dielectric bond having an embedded connecting material (e.g., a metal), wherein the embedded connecting material is coupled to one or more connecting traces in the layers in the first group 220 and to one or more connecting traces in the layers in the second group 250. In some implementations, the layers in the first group 220 are directly coupled to the layers in the second group 250 using metal-metal hybrid bonding. In other implementations, the conductive traces in the layers in the first group 220 are coupled to one or more conductive traces included in the transition layer 400 using metal-metal hybrid bonding, and the conductive traces in the layers in the second group 250 are coupled to one or more conductive traces included in the transition layer 400 using metal-metal hybrid bonding. In such implementations, the layers in the first group 220 are coupled to the transition layer 400, which is also coupled to the layers in the second group 250, as described above in conjunction with Figure 4 In various implementations, the spacing of the conductive traces in the transition layer 400 is different from the spacing of the conductive traces in the layers in the first group 220, or is different from the spacing of the conductive traces in the layers in the second group 250. In some implementations, the spacing of the conductive traces included in the transition layer 400 is different from the spacing of the conductive traces in the layers in the first group 220, and is different from the spacing of the conductive traces in the layers in the second group 250, as described above in conjunction with Figure 5 Further described.

[0048] In an implementation in which the layers in the first group 220 include a subset of layers including connections between devices that comprise the integrated circuit device assembly, the layers in the first group 220 that are coupled 1015 to the layers in the second group 250 are layers in the subset that include connections between devices that comprise the integrated circuit device assembly. Such implementations allow a subset of connections between devices that comprise the integrated circuit device assembly to be established via the first layer group 220 while additional connections between the c devices that comprise the integrated circuit device assembly are established using the second layer group 250. By forming the first layer group 220 on the first wafer 200 while forming the second layer group 250 on a different second wafer 230, this allows more connections between devices that comprise the integrated circuit device assembly to be established without increasing the time to manufacture the integrated circuit device assembly.

[0049] In view of the above explanation, the reader will recognize that manufacturing an integrated circuit device assembly including a layer in a first group formed on a first wafer (the layer is coupled to a layer in a second group formed on a second wafer using metal-metal hybrid bonding) allows more connections to be formed between devices constituting the integrated circuit device assembly without significantly increasing the manufacturing time of the integrated circuit device assembly. Such a manufacturing method allows different layers of the integrated circuit device assembly to be formed in parallel on different wafers, and the layers formed on different wafers are coupled to each other using metal-metal hybrid bonding. Additionally, forming different layer groups on different wafers prevents the performance of devices constituting the integrated circuit device assembly from being degraded by reducing the time that the devices are exposed to heat when forming layers with interconnections between devices, because one or more layers with interconnections between devices are formed on a wafer separate from the wafer including the devices constituting the integrated circuit device assembly.

[0050] It will be understood from the foregoing description that modifications and changes may be made in various specific implementations of the present disclosure. The descriptions in this specification are for illustrative purposes only and should not be interpreted in a limiting sense. The scope of the present disclosure is limited only by the language of the appended claims.

Claims

1. A method for forming a semiconductor component, the method comprising: forming a first group of layers on a first wafer, one or more layers in the first group comprising one or more devices of the semiconductor assembly; forming a second group of layers on a second wafer, one or more layers in the second group comprising connections between one or more of the devices of the semiconductor component; as well as Metal-metal hybrid bonding is used to couple the layers in the first group to the layers in the second group. 2 . The method according to claim 1 , wherein forming the first layer group on the first wafer and forming the second layer group on the second wafer are performed in parallel.

3. The method of claim 1 , wherein coupling the layers in the first group to the layers in the second group using metal-metal hybrid bonding comprises: coupling the layers in the first group to one or more conductive traces included in a transition layer using metal-metal hybrid bonding; as well as The layers in the second group are coupled to the one or more conductive traces included in the transition layer using metal-metal hybrid bonding. 4 . The method of claim 3 , wherein a pitch of the one or more conductive traces included in the transition layer is different than a pitch of conductive traces included in the layers of the first group. 5 . The method of claim 4 , wherein the pitch of the one or more conductive traces included in the transition layer is different than the pitch of conductive traces included in the layers of the second group. 6 . The method of claim 1 , wherein the first group of layers comprises a subgroup of layers comprising connections between one or more of the devices of the semiconductor component. 7 . The method of claim 6 , wherein the layers in the first group include layers in the subgroup of layers that include connections between one or more of the devices of the semiconductor component. 8 . The method of claim 1 , wherein the layers in the second set of layers on the second wafer include at least one passive component.

9. The method of claim 8, wherein the passive component comprises a capacitor.

10. The method of claim 9, wherein the capacitor comprises an ultra-high density metal-insulator-metal capacitor. The method of claim 8 , wherein the passive component comprises an inductor.

12. A semiconductor device, comprising: a first group of layers, one or more layers in the first group comprising one or more devices; and A second group of layers, the layers in the second group being coupled to the layers in the first group using metal-metal hybrid bonding, one or more layers in the second group comprising connections between one or more of the devices.

13. The semiconductor device according to claim 12, further comprising: A transition layer includes one or more conductive traces, the layers in the first group are coupled to the one or more conductive traces using metal-metal hybrid bonding, and the layers in the second group are coupled to the one or more conductive traces using metal-metal hybrid bonding.

14. The semiconductor device of claim 13, wherein a pitch of the one or more conductive traces included in the transition layer is different than a pitch of conductive traces included in the layers of the first group. 15 . The semiconductor device of claim 14 , wherein the pitch of the one or more conductive traces included in the transition layer is different than a pitch of conductive traces included in the layers of the second group. 16 . The semiconductor device of claim 12 , wherein the first group of layers comprises a subgroup of layers, the subgroup of layers comprising connections between one or more of the devices. 17 . The semiconductor device of claim 16 , wherein the layers in the first group include layers in the subgroup of layers, the layers including connections between one or more of the devices. 18 . The semiconductor device of claim 12 , wherein layers in the second layer group include at least one passive component. The semiconductor device of claim 18 , wherein the passive component comprises a capacitor.

20. The semiconductor device of claim 18, wherein the passive component comprises an inductor.

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