Semiconductor device

Abstract

The purpose of the present invention is to suppress damage to a bonding member that bonds a semiconductor chip to a wiring board. The semiconductor device includes a semiconductor chip (12) and an insulating circuit board (11), the insulating circuit board (11) includes a wiring board (11b2) on the front surface, the rear surface of the insulating circuit board (11) is set as the lower surface and is warped in a downward protruding manner, and the semiconductor chip (12) is bonded to a bonding region of the upper surface of the wiring board (11b2), which is inclined on the front surface due to the warpage, via a bonding member (14a). At this time, the semiconductor chip (12) is bonded to the bonding region such that an end portion of the back surface of the semiconductor chip (12), which is located on the apex (16b) side of the warpage of the insulating circuit board (11), is supported by a support portion (15) provided in the bonding region. At this time, the semiconductor chip (12) is substantially parallel to the bonding region of the wiring board (11b2) by the support section (15), and the thickness of the bonding member (14a) is substantially uniform. As a result, the occurrence of cracks with respect to the joining member (14a) is reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] The first semiconductor chip and the second semiconductor chip are respectively joined to the wiring portion via the first solder portion and the second solder portion. The thickness of the first solder portion is thinner than that of the second solder portion. Thus, in the case where the insulating substrate including the second semiconductor chip and the wiring portion is deformed due to thermal fluctuations, it is difficult for the second solder portion to absorb the deformation and cracks are likely to occur (for example, refer to patent document 1). In addition, when the semiconductor chip is joined to the circuit pattern via the bonding material, a non-angular and gentle protrusion is formed in the area of ​​the circuit pattern opposite to the semiconductor chip. Thus, the fatigue tolerance of the bonding material is improved (for example, refer to patent document 2).

[0003] The semiconductor device includes a conductor layer and a semiconductor element joined to the conductor layer via a solder layer, and the solder layer includes a wiring bump. Thus, the film thickness of the solder layer can be made uniform, and the generation of voids in the solder layer can be prevented (for example, refer to Patent Document 3). In addition, the semiconductor chip is joined to the mounting component of the mounting surface via solder, and two areas with different wettability are provided around the semiconductor chip. Thus, the positional displacement of the semiconductor chip, including rotation, is prevented (for example, refer to Patent Document 4).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2022-174923

[0007] Patent Document 2: Japanese Patent Application Publication No. 2020-009995

[0008] Patent Document 3: Japanese Patent Application Publication No. 2019-110317

[0009] Patent Document 4: Japanese Patent Application Publication No. 2009-218280 Summary of the invention

[0010] Technical issues

[0011] An object of the present invention is to provide a semiconductor device capable of suppressing damage to a bonding member for bonding a semiconductor chip to a wiring board.

[0012] Technical Solution

[0013] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor chip; and a substrate, which includes a wiring board on the front side and is warped to protrude downward with the back side being arranged below, wherein the semiconductor chip is joined to a joining area on the upper surface of the wiring board which is inclined at the front side due to the warping via a first joining component, and the semiconductor chip is joined to the joining area in a manner that a support portion provided in the joining area is used to support the end of the back side of the semiconductor chip located on the vertex side of the warping of the substrate.

[0014] The semiconductor chip may be substantially parallel to the bonding region of the wiring board.

[0015] The support portion may be formed on the vertex side of the bonding region of the wiring board in a protrusion shape.

[0016] The support portion may be formed in plurality on the vertex side of the bonding region of the wiring board.

[0017] The semiconductor chip may have a rectangular shape in a plan view, and the support portion may be formed corresponding to two corner portions on the vertex side of the semiconductor chip, respectively, with respect to the bonding region of the wiring board.

[0018] The support portion may be formed in the bonding region of the wiring board and include an inclined surface inclined so that a side closer to the apex is higher than a side farther from the apex in a side view.

[0019] The semiconductor chip may have a rectangular shape in a plan view, and the support portion may be formed along a side on the vertex side of the semiconductor chip at the bonding region with respect to the wiring board.

[0020] The support portion may be a roughened region in which the vertex side of the bonding region of the wiring board is roughened.

[0021] The support portion may include a plurality of the roughened regions.

[0022] The semiconductor chip may have a rectangular shape in a plan view, and the support portion may be formed corresponding to two corner portions on the vertex side of the semiconductor chip, respectively, with respect to the bonding region of the wiring board.

[0023] The support portion may be a conductive line formed on the vertex side of the bonding region of the wiring board.

[0024] The semiconductor chip may have a rectangular shape in a plan view, and the support portion may be formed along a side on the vertex side of the semiconductor chip at the bonding region with respect to the wiring board.

[0025] The support portion may be formed to correspond to two corner portions on the vertex side of the semiconductor chip, respectively, with respect to the bonding region of the wiring board.

[0026] The semiconductor device may further include a wiring member having a flat-plate-shaped bonding portion bonded to the main electrode on the front surface of the semiconductor chip via a second bonding member.

[0027] The bonding portion of the wiring member may be substantially parallel to the front surface of the semiconductor chip.

[0028] A protrusion may be formed on a bonding surface of the bonding portion that is bonded to the main electrode of the semiconductor chip.

[0029] It should be noted that the above-mentioned summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions.

[0030] Effects of the Invention

[0031] According to the disclosed technology, it is possible to suppress damage to a bonding member that bonds a semiconductor chip to a wiring board, thereby preventing a decrease in the reliability of a semiconductor device.

[0032] The above-mentioned object, other objects, features and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings which illustrate preferred embodiments as examples of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a top view of the semiconductor device according to the embodiment.

[0034] Figure 2 It is a side view of the semiconductor device according to the embodiment.

[0035] Figure 3 It is a top view of a semiconductor unit included in the semiconductor device according to the embodiment.

[0036] Figure 4 It is a plan view of an insulating circuit substrate included in the semiconductor device according to the embodiment.

[0037] Figure 5 This is a first side view of a semiconductor unit included in the semiconductor device according to the embodiment.

[0038] Figure 6 This is a second side view of the semiconductor unit included in the semiconductor device according to the embodiment.

[0039] Figure 7 It is a third side view of the semiconductor unit included in the semiconductor device according to the embodiment.

[0040] Figure 8 It is a fourth side view of the semiconductor unit included in the semiconductor device according to the embodiment.

[0041] Fig. 9 This is a plan view (part 1) showing another warped insulating circuit substrate included in the semiconductor device according to the embodiment.

[0042] Fig.10 This is a second side view (part 1) of a semiconductor unit in which another warpage occurs, which is included in the semiconductor device according to the embodiment.

[0043] Fig.11 This is a fourth side view (part 1) of a semiconductor unit in which another warpage occurs, which is included in the semiconductor device according to the embodiment.

[0044] Fig.12 This is a plan view (part 2) showing another warped insulating circuit substrate included in the semiconductor device according to the embodiment.

[0045] Fig.13 This is a second side view (part 2) of a semiconductor unit including the semiconductor device according to the embodiment in which another warpage occurs.

[0046] Fig.14 This is a fourth side view (part 2) of a semiconductor unit including the semiconductor device according to the embodiment and in which another warpage occurs.

[0047] Fig.15 is a cross-sectional view of a semiconductor device according to an embodiment.

[0048] Fig.16 This is a rear view of a cooling device included in the semiconductor device according to the embodiment.

[0049] Fig.17 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment.

[0050] Fig.18 This is a diagram for explaining the installation process included in the method for manufacturing a semiconductor device according to the embodiment.

[0051] Fig.19 This is a diagram illustrating a setting step included in the method for manufacturing a semiconductor device according to a reference example.

[0052] Fig. 20 It is a diagram for explaining a first bonding step included in the method for manufacturing a semiconductor device according to a reference example.

[0053] Fig.21 This is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (Variation 1).

[0054] Fig. 22 This is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (Variation 2).

[0055] Fig.23 This is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (Variation 3).

[0056] Fig.24 This is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (Variation 4).

[0057] Explanation of symbols

[0058] 1 ... semiconductor device; 2 ... semiconductor module; 3 ... cooling device; 10, 10a, 10b, 10c ... semiconductor unit; 11 ... insulating circuit substrate; 11a ... insulating plate; 11a1, 11a2, 11a3, 11a4 ... side surface; 11a5, 11a6, 11a7, 11a8 ... corner; 11b1, 11b2, 11b3 ... wiring board; 11c ... metal plate; 11d ... bonding area ; 12…semiconductor chip; 12a…control electrode; 12b…main electrode; 13a, 13b…lead frame; 13a1, 13b1…main electrode joint; 13a2, 13b2…first vertical joint; 13a3, 13b3…horizontal joint; 13a4, 13b4…second vertical joint; 13a5, 13b5…wiring joint; 13a6, 13b6…boss; 14a, 14b ...joining member; 15...supporting portion; 16a, 16b, 16c, 16d...apex; 20...housing; 21...frame; 21a, 21b, 21c, 21d...outer wall; 21e, 21f, 21g...unit storage portion; 21i...fixing hole; 22a, 22b, 22c...first connecting terminal; 23a, 23b, 23c...second connecting terminal; 24a...U phase output terminal; 24b...V phase output terminal; 24c…W phase output terminal; 25a, 25b, 25c…control terminal; 26…lead wire; 27…sealing member; 30a, 30c…long side; 30b, 30d…short side; 30e…fastening hole; 31…top plate; 32…side wall; 33…cooling base plate; 33a…inlet; 33a1, 33b1…sealing area; 33b…outlet; 33d…bottom surface; 34…heat sink fin. DETAILED DESCRIPTION

[0059] Hereinafter, the embodiment will be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "upper surface" represent the XY plane facing the upper side (+Z direction) in the semiconductor device 1 of the figure. Similarly, "up" represents the direction of the upper side (+Z direction) in the semiconductor device 1 of the figure. "Back" and "lower surface" represent the XY plane facing the lower side (-Z direction) in the semiconductor device 1 of the figure. Similarly, "lower" represents the direction of the lower side (-Z direction) in the semiconductor device 1 of the figure. The same directionality is also meant in other drawings as needed. "Front", "upper surface", "up", "back", "lower surface", "lower", and "side" are only expressions for the convenience of determining the relative positional relationship, and do not limit the technical idea of ​​the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. That is, the directions of "up" and "down" are not limited to the direction of gravity. In addition, in the following description, "main component" means the case of including 80vol% or more. In addition, "substantially the same" means that it is within the range of ±10%. In addition, "perpendicular" and "parallel" only need to be within the range of ±10°.

[0060] [Implementation Method]

[0061] use Figure 1 and Figure 2 A semiconductor device 1 according to an embodiment will be described. Figure 1 It is a top view of the semiconductor device according to the embodiment. Figure 2 1 is a side view of a semiconductor device according to an embodiment of the present invention. Figure 2 is Figure 1 Side view of the XZ plane viewed in the +Y direction.

[0062] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, 10c and a housing 20 for housing the semiconductor units 10a, 10b, 10c. The semiconductor units 10a, 10b, 10c housed in the housing 20 are sealed by a sealing member (not shown). It should be noted that the semiconductor units 10a, 10b, 10c are all formed in the same configuration. When the semiconductor units 10a, 10b, 10c are not distinguished, they are described as the semiconductor unit 10. The details of the semiconductor unit 10 will be described later.

[0063] First, the housing 20 includes a frame 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b, 25c.

[0064] The frame 21 is roughly rectangular in plan view and is surrounded by outer walls 21a, 21b, 21c, and 21d. The outer walls 21a and 21c correspond to the long sides of the frame 21 in plan view, and the outer walls 21b and 21d correspond to the short sides of the frame 21. In plan view, the corners of the connecting parts of the outer walls 21a, 21b, 21c, and 21d do not need to be right angles. Figure 1 As shown, the corners may also be chamfered. Fixing holes 21i penetrating the frame 21 are formed at the corners of the front surface of the frame 21. It should be noted that the fixing holes 21i formed at such corners of the frame 21 may be formed at a position lower than the front surface of the frame 21 (in the -Z direction).

[0065] The frame 21 includes unit storage parts 21e, 21f, and 21g along the outer walls 21a and 21c on the front. The unit storage parts 21e, 21f, and 21g are opened in a rectangular shape when viewed from above. The semiconductor units 10a, 10b, and 10c are respectively stored in the unit storage parts 21e, 21f, and 21g. As described in detail later, the semiconductor units 10a, 10b, and 10c are respectively joined to the top plate 31 of the cooling device 3 described later. The frame 21 is mounted on the top plate 31 of such a cooling device 3. When installed, the unit storage parts 21e, 21f, and 21g of the frame 21 respectively surround (store) the semiconductor units 10a, 10b, and 10c arranged in the cooling device 3. It should be noted that an inlet 33a and an outlet 33b are formed on the bottom surface 33d of the cooling device 3 (the surface opposite to the top plate 31 on which the semiconductor unit 10 is mounted). The cooling device 3 will be described in detail later.

[0066] The frame 21 includes first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c on the front side of the outer wall 21a and along the outer wall 21a when viewed from above. The outer end portions of one side of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c are exposed on the front side of the outer wall 21a. The inner end portions of the other side are exposed in the unit storage portions 21e, 21f, 21g and are electrically connected to the semiconductor units 10a, 10b, 10c. It should be noted that the area on the front side of the frame 21 that is opposite to the openings of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c can accommodate nuts that are opposite to the openings.

[0067] On the front side of the outer wall 21a, along the outer wall 21c, a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c are provided. The outer ends of one side of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are exposed from the outer wall 21c. The inner ends of the other sides are exposed in the unit storage parts 21e, 21f, and 21g and are electrically connected to the semiconductor units 10a, 10b, and 10c.

[0068] Thus, in the front of the frame 21, the first connection terminal 22a and the second connection terminal 23a are arranged with the W-phase output terminal 24c across the unit storage portion 21e when viewed from above. Similarly, the first connection terminal 22b and the second connection terminal 23b are arranged with the V-phase output terminal 24b across the unit storage portion 21f. Similarly, the first connection terminal 22c and the second connection terminal 23c are arranged with the U-phase output terminal 24a across the storage portion 21g.

[0069] In addition, the frame 21 is provided with control terminals 25a, 25b, and 25c along the outer wall 21c on the side of the +Y direction side of the unit storage parts 21e, 21f, and 21g when viewed from above. The control terminals 25a, 25b, and 25c are respectively provided in two. The control terminals 25a, 25b, and 25c are, for example, L-shaped, including an outer end and an inner end. The outer ends of the control terminals 25a, 25b, and 25c extend vertically upward (in the +Z direction) from the front of the frame 21. The other ends of the control terminals 25a, 25b, and 25c are exposed in the unit storage parts 21e, 21f, and 21g. It should be noted that the shape and number of configurations of the control terminals 25a, 25b, and 25c are not limited thereto and can be appropriately changed.

[0070] Such a frame 21 includes first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b, 25c, and is integrally molded by injection molding using a thermoplastic resin. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0071] In addition, the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy having at least one of these as a main component. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c may also be plated. At this time, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0072] The sealing member 27 (see Fig. 9 ) can be a thermosetting resin. Thermosetting resins are, for example, epoxy resins, phenolic resins, maleimide resins, and polyester resins. Epoxy resin is preferred. In addition, fillers can also be added to the sealing component 27. The fillers can be ceramics that are insulating and have high thermal conductivity.

[0073] Next, use Figure 3 and Figure 4 The semiconductor units 10a, 10b, and 10c will be described. Figure 3 1 is a top view of a semiconductor unit included in a semiconductor device according to an embodiment. Figure 4 yes Figure 3 FIG. 1 is a top view of an insulating circuit substrate 11 of a semiconductor unit 10 .

[0074] The semiconductor unit 10 includes an insulating circuit substrate 11, two semiconductor chips 12, and lead frames 13a and 13b. The semiconductor chips 12 are connected to each other by a bonding member 14a (see Figures 5 to 8 ) is bonded to the insulating circuit substrate 11. The lead frames 13a and 13b are connected by bonding members 14b (see Figures 5 to 8 ) is bonded to the main electrode on the front side of the semiconductor chip 12.

[0075] like Figure 4 As shown, the insulating circuit substrate 11 includes an insulating plate 11a, wiring plates 11b1, 11b2, 11b3, and a metal plate 11c (see Figures 5 to 8 ). In addition, it includes a support portion 15. It should be noted that Figure 4The dotted-line region (vertices 16a to 16d) shows the positions of the warped vertices 16a to 16d generated in the insulating circuit substrate 11 when viewed from above. When warped vertices 16b and 16d are generated, the support portion 15 is formed at these positions. The warped vertices 16a to 16d do not necessarily need to be generated at these positions at the same time. At least one of them may be generated. In addition, Figure 4 The positions of the apexes 16a to 16d of the warp shown are only examples. It should be noted that other examples of the positions of the warp generated in the insulating circuit substrate 11 in a plan view will be described later.

[0076] The insulating plate 11a and the metal plate 11c are rectangular in plan view. The corners of the insulating plate 11a and the metal plate 11c may be R-chamfered or C-chamfered. The size of the metal plate 11c is smaller than that of the insulating plate 11a in plan view, and the metal plate 11c is formed inside the insulating plate 11a.

[0077] The insulating plate 11a includes side surfaces 11a1 to 11a4 that surround the front surface in sequence. Side surfaces 11a1 and 11a3 correspond to the short sides of the insulating plate 11a when viewed from above. Side surfaces 11a2 and 11a4 correspond to the long sides of the insulating plate 11a when viewed from above. In addition, the insulating plate 11a includes four corners 11a5 to 11a8, respectively. Corner 11a5 is formed by side surfaces 11a1 and 11a2. Corner 11a6 is formed by side surfaces 11a2 and 11a3. Corner 11a7 is formed by side surfaces 11a3 and 11a4. Corner 11a8 is formed by side surfaces 11a4 and 11a1. Such an insulating plate 11a is made of a material having excellent insulation and thermal conductivity. Such an insulating plate 11a is made of ceramics. Examples of ceramics are alumina, aluminum nitride, and silicon nitride.

[0078] Wiring boards 11b1, 11b2, 11b3 are formed on the front surface of insulating board 11a. Wiring boards 11b1, 11b2, 11b3 are made of metal with excellent conductivity. Such metal is, for example, copper, aluminum, or an alloy having at least one of these as a main component. In addition, the thickness of wiring boards 11b1, 11b2, 11b3 is not less than 0.1 mm and not more than 2.0 mm. In order to improve corrosion resistance, the surfaces of wiring boards 11b1, 11b2, 11b3 may also be plated. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0079] The wiring board 11b1 occupies half of the area on the side of the side 11a4 of the front side of the insulating board 11a and occupies the entire area from the side 11a1 to the side 11a3. A bonding area 11d is set on the upper surface of the wiring board 11b1. The bonding area 11d is bonded to the semiconductor chip 12, corresponding to the shape of the semiconductor chip 12 when viewed from above. In addition, the dotted area shown on one side of the -Y direction of the front side of the wiring board 11b1 is bonded to the inner ends of the first connecting terminals 22a, 22b, and 22c. The bonding at this time can be a bonding component, laser welding, or ultrasonic bonding. Alternatively, the dotted area shown on the wiring board 11b1 and the inner ends of the first connecting terminals 22a, 22b, and 22c can also be bonded via a conductive block.

[0080] The wiring board 11b2 occupies half of the side surface 11a2 of the front surface of the insulating plate 11a. In addition, the wiring board 11b2 occupies the front surface of the insulating plate 11a from the side surface 11a3 to the front of the side surface 11a1. A bonding area 11d is set on the front surface of the wiring board 11b2. In addition, a support portion 15 is provided in the bonding area 11d of the wiring board 11b2.

[0081] The support portion 15 is in the shape of a protrusion. Such a support portion 15 may be, for example, in the shape of a column. The columnar shape may include a cylindrical shape, a quadrangular prism shape, a triangular prism shape, and may also include a truncated cone shape. The support portions 15 are respectively provided at the corners of the joining area 11d on the side of the vertices 16b and 16d described later of the joining area 11d. A plurality of support portions 15 may be formed on the side of the vertices 16b and 16d described later of the joining area 11d. It should be noted that the formation position of the support portion 15 depends on the position of the vertices of the warp as described later. The support portion 15 is formed on the side of the vertices 16b and 16d described later of the joining area 11d. Figure 4 In addition, there is a case where the support portion 15 is not formed depending on the position of the apex of the warp. The formation position of the support portion 15 formed according to the position of the apex of the warp will be described later.

[0082] In addition, the support portion 15 is preferably made of a conductive material. Such metals are, for example, copper, aluminum, or an alloy having at least one of these as a main component. Alternatively, the support portion 15 may be disposed on the wiring board 11b2, and the support portion 15 may be bonded to the wiring board 11b2. Thus, the main electrode on the back of the semiconductor chip 12 is electrically connected to the wiring board 11b2. In addition, the semiconductor chip 12 may be clamped from the back of the semiconductor chip 12.

[0083] In addition, the dotted line area shown on one side of the +Y direction of the front side of the wiring board 11b2 is joined to the inner end of each of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c. The joining at this time can be a joining component, laser welding, or ultrasonic joining. Alternatively, the dotted line area shown on the wiring board 11b2 and the inner end of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c can also be joined via a conductive block.

[0084] The wiring board 11b3 occupies the area surrounded by the wiring boards 11b1 and 11b2 on the front side of the insulating board 11a. The dotted area shown on the wiring board 11b3 is joined to the ends of the second connection terminals 23a, 23b, and 23c. The joining at this time can be a joining component, laser welding, or ultrasonic joining. Alternatively, the area surrounded by the dotted line shown on the wiring board 11b3 and the ends of the second connection terminals 23a, 23b, and 23c can also be joined via a conductive block.

[0085] Such wiring boards 11b1, 11b2, 11b3 are formed on the front surface of the insulating plate 11a as shown below. A metal layer is formed on the front surface of the insulating plate 11a, and the metal layer is etched or processed to obtain wiring boards 11b1, 11b2, 11b3 of a predetermined shape. Alternatively, wiring boards 11b1, 11b2, 11b3 cut out from the metal layer in advance may be crimped to the front surface of the insulating plate 11a. The corners of the wiring boards 11b1, 11b2, 11b3 may be R-chamfered or C-chamfered. It should be noted that the wiring boards 11b1, 11b2, 11b3 are examples. The number, shape, size, and position of the wiring boards 11b1, 11b2, 11b3 may be appropriately selected as needed.

[0086] like Figures 5 to 8 As referred to in , the metal plate 11c is formed on the back side of the insulating plate 11a. The metal plate 11c is rectangular in shape. The area of ​​the metal plate 11c when viewed from above is smaller than the area of ​​the insulating plate 11a, and larger than the area of ​​the region where the wiring boards 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may also be R-chamfered or C-chamfered. The metal plate 11c is smaller in size than the insulating plate 11a, and is formed on the entire surface of the insulating plate 11a except for the edges. The metal is, for example, copper, aluminum, or an alloy including at least one of these. In order to improve corrosion resistance, the surface of the metal plate 11c may also be plated. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0087] As the insulating circuit substrate 11 having such a structure, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. The insulating circuit substrate 11 may be mounted on the front surface of the cooling device 3 via a bonding member (not shown). The heat generated by the semiconductor chip 12 can be conducted to the cooling device 3 via the wiring boards 11b1, 11b2, the insulating plate 11a, and the metal plate 11c to dissipate the heat.

[0088] The joining parts 14a and 14b are solders. Lead-free solder is used as the solder. For example, the lead-free solder is mainly composed of an alloy including at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. In addition, additives may be included in the solder. The additives are, for example, nickel, germanium, cobalt, or silicon. By including additives, the solder improves wettability, gloss, and bonding strength, thereby improving reliability.

[0089] In addition, the joining component (not shown) joining the semiconductor unit 10 and the cooling device 3 may be solder, brazing material, or thermal interface material. Lead-free solder is used as the solder. The brazing material may be, for example, at least one of an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy as a main component. The thermal interface material may be, for example, an adhesive material including an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, a phase change material, and the like. By installing the cooling device 3 via such a brazing material or a thermal interface material, the heat dissipation of the semiconductor unit 10 can be improved.

[0090] The semiconductor chip 12 includes a power device element made of silicon. The thickness of the semiconductor chip 12 is, for example, greater than 40 μm and less than 250 μm. The power device element is an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT has the functions of an IGBT as a switching element and a FWD (Free Wheeling Diode) as a diode element. The front side of such a semiconductor chip 12 is provided with a control electrode 12a (gate electrode) and an output electrode (emitter electrode) as a main electrode 12b. The back side of the semiconductor chip 12 is provided with an input electrode (collector electrode) as a main electrode, which is omitted from the figure. It should be noted that the control electrode 12a can be arranged along one side (or the central part of one side) of the front side of the semiconductor chip 12. The output electrode is arranged in the central part of the front side of the semiconductor chip 12. The input electrode is arranged in a manner including the central part of the back side of the semiconductor chip.

[0091] In addition, the semiconductor chip 12 can also use a set of switching elements and diode elements instead of RC-IGBT. The switching element is, for example, IGBT, power MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor). Such a semiconductor chip 12, for example, has an input electrode (drain electrode, or collector electrode) as a main electrode on the back, and a control electrode 12a (gate electrode) and an output electrode (source electrode, or emitter electrode) as a main electrode 12b on the front. Diode elements are, for example, SBD (Schottky Barrier Diode) and PiN (P-intrinsic-N: P-intrinsic-N) diodes, which are used as FWD. Such a semiconductor chip 12 has an output electrode (cathode electrode) as a main electrode on the back, and an input electrode (anode electrode) as a main electrode on the front.

[0092] In addition, the semiconductor chip 12 may include a switching element composed of a power MOSFET. The semiconductor chip 12 includes a power MOSFET and a FWD. Such a semiconductor chip 12 includes a control electrode 12a (gate electrode) and an output electrode (source electrode) as a main electrode 12b on the front side. The semiconductor chip 12 includes an input electrode (drain electrode) as a main electrode on the back side. Such a semiconductor chip 12 may preferably be composed of silicon carbide.

[0093] The lead frame 13a is wired so that the main electrode 12b of the semiconductor chip 12 (on the wiring board 11b2) is electrically connected to the wiring board 11b3. The lead frame 13b is wired so that the main electrode 12b of the semiconductor chip 12 (on the wiring board 11b1) is electrically connected to the wiring board 11b2. The semiconductor unit 10 may be a device constituting a single-phase inverter circuit.

[0094] The lead frames 13a and 13b integrally include main electrode joints 13a1 and 13b1, first vertical joints 13a2 and 13b2, horizontal joints 13a3 and 13b3, second vertical joints 13a4 and 13b4, and wiring joints 13a5 and 13b5. It should be noted that the lead frames 13a and 13b are of the same thickness as a whole and are in the shape of a flat plate. The lead frames 13a and 13b can be formed by bending these parts. The lead frames 13a and 13b are made of a metal with excellent electrical conductivity. Such metals are, for example, copper, aluminum, or an alloy having at least one of these as a main component. In addition, the thickness of the lead frames 13a and 13b is greater than 0.1 mm and less than 2.0 mm. In order to improve corrosion resistance, the surface of the lead frames 13a and 13b can also be plated. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0095] The main electrode joints 13a1 and 13b1 are in the form of flat plates. The main electrode joints 13a1 and 13b1 are joined to the main electrode 12b of the semiconductor chip 12 (of the wiring boards 11b2 and 11b1) by the joining member 14a. It should be noted that the main electrode joints 13a1 and 13b1 are in the form of a rectangle in plan view, similar to the main electrode 12b. Bosses 13a6 and 13b6 are formed on the backs of the main electrode joints 13a1 and 13b1, respectively (see FIG. Figures 5 to 8 ). The bosses 13a6 and 13b6 may be formed at, for example, four corners of the back surface of the rectangular main electrode joint portions 13a1 and 13b1, respectively.

[0096] The lower ends of the first vertical connecting portions 13a2 and 13b2 are integrally connected to the ends of the main electrode joints 13a1 and 13b1, and the upper ends of the first vertical connecting portions 13a2 and 13b2 extend vertically upward (in the +Z direction) relative to the main electrode joints 13a1 and 13b1. The first vertical connecting portion 13a2 is joined to the end of the main electrode joint 13a1 on the wiring board 11b3 (in the -Y direction), and the main electrode joint 13a1 is joined to the semiconductor chip 12 arranged on the wiring board 11b2. The first vertical connecting portion 13b2 is joined to the end of the main electrode joint 13b1 on the wiring board 11b2 (in the -X direction), and the main electrode joint 13b1 is joined to the semiconductor chip 12 arranged on the wiring board 11b1.

[0097] The horizontal connecting parts 13a3 and 13b3 are integrally connected to the upper ends of the first vertical connecting parts 13a2 and 13b2, and extend to the wiring boards 11b3 and 11b2, respectively. The horizontal connecting parts 13a3 and 13b3 are in the shape of a plate. In addition, the horizontal connecting parts 13a3 and 13b3 extend along the ±Y direction and the ±X direction, respectively. One end and the other end of the horizontal connecting parts 13a3 and 13b3 can be staggered. At this time, the horizontal connecting parts 13a3 and 13b3 span the gaps between the wiring boards 11b2 and 11b3 and the wiring boards 11b1 and 11b2, respectively. The horizontal connecting parts 13a3 and 13b3 are parallel to the insulating circuit substrate 11. In addition, the horizontal connecting parts 13a3 and 13b3 can also be formed to have the same height. The heights of the first vertical connection parts 13a2, 13b2 and the second vertical connection parts 13a4, 13b4 are appropriately selected so that the horizontal connection parts 13a3, 13b3 are formed in this way.

[0098] The upper ends of the second vertical connecting parts 13a4 and 13b4 are integrally connected to the ends of the horizontal connecting parts 13a3 and 13b3, and the lower ends of the second vertical connecting parts 13a4 and 13b4 extend vertically downward (-Z direction) and are integrally connected to the wiring bonding parts 13a5 and 13b5.

[0099] The wiring joining portions 13a5 and 13b5 are joined to the wiring plates 11b3 and 11b2, respectively, and are integrally connected to the lower end portions of the second vertical connecting portions 13a4 and 13b4.

[0100] The first vertical connection portion 13a2, the horizontal connection portion 13a3 (excluding the bent portion), the second vertical connection portion 13a4, and the wiring joint portion 13a5 of the lead frame 13a are formed to have the same width. The width refers to the length in the direction (±X direction) orthogonal to the wiring direction (±Y direction) of the lead frame 13a.

[0101] The first vertical connection portion 13b2, the horizontal connection portion 13b3 (except the bent portion), and the second vertical connection portion 13b4 of the lead frame 13b are formed to have the same width. The width refers to the length in the direction (±Y direction) orthogonal to the wiring direction (±X direction) of the lead frame 13b.

[0102] In addition, the control electrodes 12a of the semiconductor chips 12 of the semiconductor units 10a, 10b, 10c housed in the unit housing portions 21e, 21f, 21g of the housing 20 are mechanically and electrically connected to the inner ends of the control terminals 25a, 25b, 25c by the wires 26 (see Figure 1 ). The wire 26 is mainly composed of a material with excellent electrical conductivity. Such a material is, for example, made of gold, copper, aluminum, or an alloy containing at least one of these. Preferably, the wire 26 can be an aluminum alloy containing a trace amount of silicon. In addition, the diameter of the wire 26 is, for example, not less than 100 μm and not more than 400 μm.

[0103] The semiconductor unit 10 having such a structure is warped and uneven in the insulating circuit substrate 11 due to heating during manufacturing described later. The warping depends on, for example, the volume and formation position of the wiring boards 11b1 to 11b3 and the metal plate 11c of the insulating circuit substrate 11, the semiconductor chip 12, the lead frames 13a and 13b, and the heating temperature and time.

[0104] Here, an example of the warping generated in the insulating circuit substrate 11 is described. Here, the vertices 16a and 16c of the warping are generated on the side surfaces 11a1 and 11a3 of the insulating circuit substrate 11. In addition, the vertices 16b and 16d of the warping are generated on the side surface 11a3 side of the side surfaces 11a2 and 11a4 of the insulating circuit substrate 11, respectively. Figures 5 to 8 These situations are explained.

[0105] Figures 5 to 8 1 to 4 are first to fourth side views of a semiconductor unit included in a semiconductor device according to an embodiment. Figure 5 Observe in the -Y direction Figure 3 A side view of the semiconductor unit 10 is obtained. Figure 6 Observe in the -X direction Figure 3 A side view of the semiconductor unit 10 is obtained. Figure 7 Observe in the +Y direction Figure 3 A side view of the semiconductor unit 10 is obtained. Figure 8 Observe in the +X direction Figure 3 It should be noted that, Figures 5 to 8 The warping is schematically illustrated. Figures 5 to 8 Although it is a side view, the support portion 15 and the bosses 13a6 and 13b6 are shown in a visually recognizable manner (these symbols are omitted in some cases). Figures 5 to 8 A portion of the warpage is sometimes expressed as being larger than the actual warpage.

[0106] For example, in a side view of the semiconductor unit 10 viewed in the -Y direction, Figure 5 As shown, the area where the wiring board 11b1 is formed is substantially flat. The area where the wiring board 11b2 is formed is deformed in the -Z direction compared to the area where the wiring board 11b1 is formed. In addition, at the vertex 16c near the center of the area where the wiring board 11b1 is formed, the bottom surface (-Z direction) of the insulating circuit substrate 11 is set to the bottom, and it is warped in a downward convex manner. At this time, the semiconductor chip 12 is set on the vertex 16c, and the semiconductor chip 12 is substantially parallel to the wiring board 11b2.

[0107] In the side view obtained by observing the semiconductor unit 10 in the -X direction, as shown in FIG. Figure 6 As shown, the entire region is warped convexly downward with vertex 16d of the region where wiring board 11b1 is formed as the vertex. At this time, the back surface of semiconductor chip 12 on the vertex 16d side is supported by support portion 15, and semiconductor chip 12 is substantially parallel to wiring board 11b1.

[0108] In the side view obtained by observing the semiconductor unit 10 in the +Y direction, Figure 7 As shown, the region where the wiring board 11b1 is formed is substantially flat. The region where the wiring board 11b3 is formed is warped so as to protrude downward at a vertex 16a slightly closer to the -X direction from the center of the region.

[0109] In the side view obtained by observing the semiconductor unit 10 in the +X direction, Figure 8 As shown, the entire semiconductor chip 12 is warped downwardly convexly with the vertex 16b of the area where the wiring board 11b2 is formed as the vertex. At this time, the back side of the vertex 16b of the semiconductor chip 12 is supported by the support portion 15, and the semiconductor chip 12 is substantially parallel to the wiring board 11b2. It should be noted that the warped vertices 16a, 16b, 16c, and 16d do not have to be generated at these positions at the same time. At least one may be generated.

[0110] In addition, the side surfaces 11a2 and 11a4 of the insulating circuit substrate 11 are Figure 4 Here, we use Figures 9 to 11 A case where warped apexes 16 b and 16 d are respectively generated in the center of the side surfaces 11 a 2 and 11 a 4 of the insulating circuit substrate 11 will be described.

[0111] Fig. 9 This is a plan view showing another warped insulating circuit substrate included in the semiconductor device according to the embodiment. Fig.10 This is a second side view of a semiconductor unit including the semiconductor device according to the embodiment and in which another warpage occurs. Fig.11 FIG. 4 is a fourth side view of a semiconductor unit including a semiconductor device according to an embodiment and having other warpage. Fig. 9 and Figure 4 Corresponding, showing relative to Figure 4 In the illustrated example, the side surfaces 11a2 and 11a4 of the insulating circuit substrate 11 have warping vertices at different positions (centers of the side surfaces 11a2 and 11a4). Fig.10 and Figure 6 Correspondingly, this is a side view of the semiconductor unit 10 viewed in the −X direction. Fig.11 and Figure 8 Correspondingly, it is a side view obtained by observing the semiconductor unit 10 in the +X direction. Fig.10 and Fig.11 The warping is schematically illustrated. Fig.10 and Fig.11 Although it is a side view, the support portion 15 and the bosses 13a6 and 13b6 are shown in a visually recognizable manner (these symbols are omitted in some cases). Fig.10 and Fig.11 A portion of the warpage is sometimes expressed as being larger than the actual warpage.

[0112] With respect to the side surface 11a2 of the insulating circuit substrate 11 included in the semiconductor unit 10, as shown in FIG. Fig. 9 As shown, a warped vertex 16b is generated in the center of the side surface 11a2 in the ±Y direction. In addition, a warped vertex 16d is generated in the center of the side surface 11a4 in the ±Y direction relative to the side surface 11a4 of the insulating circuit substrate 11 included in the semiconductor unit 10. It should be noted that the warped vertices 16b and 16d do not have to be generated at these positions at the same time. At least one may be generated. In addition, here, the support portion 15 may not be formed in the wiring board 11b2 bonding area 11d of the insulating circuit substrate 11.

[0113] In the side view obtained by observing the semiconductor unit 10 in the -X direction, as shown in FIG. Fig.10As shown, the area where the wiring board 11b1 is formed is warped convexly downward at the vertex 16d near the center of the area. At this time, the approximate center of the semiconductor chip 12 is located directly above the vertex 16d, and the semiconductor chip 12 is approximately parallel to the wiring board 11b1.

[0114] In the side view obtained by observing the semiconductor unit 10 in the +X direction, Fig.11 As shown, the area where the wiring board 11b2 is formed is warped convexly downward at the vertex 16b near the center of the area. At this time, the approximate center of the semiconductor chip 12 is located directly above the vertex 16b, and the semiconductor chip 12 is approximately parallel to the wiring board 11b2.

[0115] In addition, the side surfaces 11a2 and 11a4 of the insulating circuit substrate 11 are Figure 4 and Fig. 9 Here, we use Figure 2 to Figure 14 A case where warping vertices 16 b and 16 d are respectively generated on the side surface 11 a 1 side of the side surfaces 11 a 2 and 11 a 4 of the insulating circuit substrate 11 will be described.

[0116] Fig.12 This is a plan view showing another warped insulating circuit substrate included in the semiconductor device according to the embodiment. Fig.13 This is a second side view of a semiconductor unit including the semiconductor device according to the embodiment and in which another warpage occurs. Fig.14 FIG. 4 is a fourth side view of a semiconductor unit including a semiconductor device according to an embodiment and having other warpage. Fig.12 and Figure 4 and Fig. 9 Corresponding, showing relative to Figure 4 and Fig. 9 In the illustrated example, the side surfaces 11a2 and 11a4 of the insulating circuit substrate 11 have warping vertices at different positions (side surfaces 11a2 and 11a4 on the side surface 11a1 side). Fig.13 and Figure 6 and Fig.10 Correspondingly, this is a side view of the semiconductor unit 10 viewed in the −X direction. Fig.14 and Figure 8 and Fig.11 Correspondingly, it is a side view obtained by observing the semiconductor unit 10 in the +X direction. Fig.13 and Fig.14 The warping is schematically illustrated. Fig.13 and Fig.14 Although it is a side view, the support portion 15 and the bosses 13a6 and 13b6 are shown in a visually recognizable manner (these symbols are omitted in some cases). Fig.13 and Fig.14 A portion of the warpage is sometimes expressed as being larger than the actual warpage.

[0117] With respect to the side surface 11a2 of the insulating circuit substrate 11 included in the semiconductor unit 10, as shown in FIG. Fig.12 As shown, a warped vertex 16b is generated between the wiring boards 11b2 and 11b3 on the side 11a2. In addition, a warped vertex 16d is generated at a portion of the side 11a4 that is opposite to the vertex 16b with respect to the side 11a4 of the insulating circuit substrate 11 included in the semiconductor unit 10. It should be noted that the warped vertices 16b and 16d do not necessarily need to be generated at these locations at the same time. At least one of them may be generated.

[0118] A plurality of support portions 15 may be formed on the vertex 16b side of the bonding region 11d of the wiring board 11b2 of the insulating circuit substrate 11. In this case, the plurality of support portions 15 may be formed in parallel with the side surface 11a1.

[0119] In addition, a plurality of support portions 15 may be formed on the vertex 16d side of the bonding region 11d of the wiring board 11b1 of the insulating circuit substrate 11. In this case, the plurality of support portions 15 may be formed in parallel with the side surface 11a1.

[0120] In the side view obtained by observing the semiconductor unit 10 in the -X direction, as shown in FIG. Fig.13 As shown, the entire region is warped convexly downward with vertex 16d of the region where wiring board 11b1 is formed as the vertex. At this time, the back surface of semiconductor chip 12 on the vertex 16d side is supported by support portion 15, and semiconductor chip 12 is substantially parallel to wiring board 11b1.

[0121] In the side view obtained by observing the semiconductor unit 10 in the +X direction, Fig.14 As shown, the region between wiring boards 11b2 and 11b3 is warped convexly downward with vertex 16b as the vertex. At this time, the back surface of semiconductor chip 12 on the vertex 16b side is supported by support portion 15, and semiconductor chip 12 is substantially parallel to wiring board 11b2.

[0122] It should be noted that the warped vertices 16b and 16d do not necessarily have to be Figure 4 , Fig. 9 and Fig.12 The positions of the side surfaces 11a2 and 11a4 of the insulating circuit substrate 11 shown in the figure may be generated simultaneously or separately. In addition, the support portion 15 can be arbitrarily combined according to the vertices 16b and 16d of such warping. For example, in the case where only the vertex 16b is generated, or in the case where only the vertex 16d is generated, the support portion 15 is arranged on either of the wiring boards 11b1 and 11b2 corresponding to the positions of the vertices 16b and 16d. For example, in the case where the vertices 16b and 16d are in the diagonal direction ( Figure 4 Vertex 16c and Fig.12 Vertex 16d, or Fig.12 Vertex 16b and Figure 4 When the support portions 15 of the bonding region 11d of the wiring board 11b2 and the support portions 15 of the bonding region 11d of the wiring board 11b2 are simultaneously generated at the vertex 16d of the wiring board 11b2, the support portions 15 of the bonding region 11d of the wiring board 11b2 are arranged in a diagonal direction.

[0123] Next, use Fig.15 and Fig.16 The cooling device will be described. Fig.15 is a cross-sectional view of a semiconductor device according to an embodiment. Fig.16 1 is a rear view of a cooling device included in a semiconductor device according to an embodiment. Fig.15 yes Figure 1 Cross-sectional view at the single-point dashed line XX. Fig.16 yes Figure 1 The semiconductor device 1 Figure 4 make Figure 1 A back side view of the semiconductor device 1 obtained by rotating about a center line passing through the centers of the outer walls 21 a and 21 c.

[0124] The cooling device 3 includes an inlet 33a for allowing the refrigerant to flow into the interior and an outlet 33b for allowing the refrigerant circulating inside to flow out to the outside. The cooling device 3 cools the semiconductor unit 10 by allowing the heat from the semiconductor unit 10 to flow out through the refrigerant. The refrigerant used here is, for example, water, antifreeze (ethylene glycol aqueous solution), and long-term coolant. In addition, the cooling device 3 may include a pump and a heat dissipation device (radiator). The pump allows the refrigerant to flow into the inlet 33a of the cooling device 3, and allows the refrigerant flowing out of the outlet 33b to flow into the inlet 33a again, thereby circulating the refrigerant. The heat dissipation device receives the refrigerant flowing out of the cooling device 3, and dissipates the heat of the refrigerant that has conducted the heat of the semiconductor unit 10 to the outside.

[0125] Such a cooling device 3 has a top plate 31, a side wall 32 connected to the back of the top plate 31 in an annular shape, and a cooling bottom plate 33 opposite to the top plate 31 and connected to the back of the side wall 32. The top plate 31 is rectangular surrounded by long sides and short sides when viewed from above, and fastening holes are formed at four corners. The corners of the top plate 31 can be R-chamfered when viewed from above. Semiconductor units 10a, 10b, and 10c are joined to the front of the top plate 31 along the ±X direction. The side wall 32 is continuously formed in an annular manner on the back of the top plate 31. A plurality of heat dissipation fins 34 are formed in the area on the back of the top plate 31 corresponding to the area where the semiconductor units 10a, 10b, and 10c are arranged.

[0126] The cooling base plate 33 is in the shape of a flat plate and has the same shape as the top plate 31 when viewed from above. The cooling base plate 33 is in the shape of a rectangle surrounded by long sides 30a, 30c and short sides 30b, 30d when viewed from above, and fastening holes 30e corresponding to the top plate 31 are formed at the four corners. In addition, the corners of the cooling base plate 33 may also be R-chamfered. In addition, the front and bottom surfaces 33d of the cooling base plate 33 are parallel. The bottom surface 33d of the cooling base plate 33 is a flat surface without a height difference, and is formed in the same plane. In addition, the bottom surface 33d of the cooling base plate 33 and the front of the top plate 31 may also be parallel. The bottom surface 33d of the cooling base plate 33 is respectively formed with an inlet 33a and an outlet 33b for the refrigerant to flow in and out. It should be noted that the inlet 33a and the outlet 33b are provided with sealing areas 33a1 and 33b1 surrounding the bottom surface 33d of the cooling base plate 33. In the inlet 33a and the outlet 33b, a water supply head is installed via an annular rubber seal in the sealing areas 33a1 and 33b1 surrounding the inlet 33a and the outlet 33b. A water supply pipe connected to a pump is installed in the water supply head.

[0127] Next, use Fig.17 A method for manufacturing such a semiconductor device 1 will be described. Fig.17 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. First, a preparation step (step S1) is performed to prepare components of the semiconductor device 1. Components such as a semiconductor chip 12, an insulating circuit substrate 11, lead frames 13a, 13b, a housing 20, a cooling device 3, and a sealing material of a sealing member 27 are prepared. In addition to these, components required for manufacturing the semiconductor device 1 are also prepared. In addition, a manufacturing device and a manufacturing tool required for manufacturing the semiconductor device 1 can be prepared.

[0128] Next, the semiconductor chip 12 is placed on the insulating circuit substrate 11, and a placement step of sequentially placing the lead frames 13a and 13b is performed (step S2). Fig.18 This setting process will be described later. Fig.18 This is a diagram for explaining the installation process included in the method for manufacturing a semiconductor device according to the embodiment. Fig.18 The cross-sectional view of the arrangement structure in which the insulating circuit substrate 11, the semiconductor chip 12, and the lead frames 13a and 13b are arranged in this order is shown. Figure 3 The single dot dash line XX.

[0129] like Fig.18As shown, a semiconductor chip 12 is arranged on the wiring board 11b2 of the insulating circuit substrate 11 through a bonding member 14a through a setting process. The bonding member 14a before curing used here is, for example, solder paste or sheet solder. At this time, a support portion 15 is arranged between the back side of the semiconductor chip 12 on the +Y direction side and the wiring board 11b2. That is, the back side of the semiconductor chip 12 is supported by the support portion 15.

[0130] In addition, the main electrode joint portion 13a1 of the lead frame 13a is arranged on the main electrode 12b of the semiconductor chip 12 via the joint component 14b. The joint component 14b before solidification used here is, for example, solder paste or sheet solder. At this time, the main electrode joint portion 13a1 is arranged on the main electrode 12b of the semiconductor chip 12 via the boss 13a6 formed on the back side thereof. The wiring joint portion 13a5 of the lead frame 13a is arranged on the wiring board 11b3.

[0131] Next, the structure obtained in step S2 is heated to bond the components to each other to form the first bonding process of the semiconductor unit 10 (step S3). Fig.18 The bonding components 14a and 14b are heated in a state to melt and solidify. As a result, the semiconductor chip 12 is bonded to the wiring board 11b2 of the insulating circuit substrate 11 via the bonding component 14a. In addition, the main electrode bonding portions 13a1 and 13b1 of the lead frames 13a and 13b are bonded to the main electrodes 12b of the semiconductor chip 12 via the bonding component 14b. It should be noted that the wiring bonding portions 13a5 and 13b5 of the lead frames 13a and 13b are bonded to the wiring boards 11b3 and 11b2, for example, by ultrasonic bonding. In addition, by heating in the first bonding step, as Figures 5 to 8 As shown, warpage occurs in the insulating circuit substrate 11. It should be noted that the warpage occurring in the insulating circuit substrate 11 will be described later.

[0132] Next, a second bonding step (step S4) of bonding the semiconductor unit 10 to the top plate 31 of the cooling device 3 is performed. The semiconductor unit 10 is bonded to the top plate 31 of the cooling device 3 via the bonding member such as the above-mentioned solder and thermal interface material. Next, a housing mounting step (step S5) of mounting the housing 20 to the cooling device 3 is performed. The housing 20 is mounted on the top plate 31 of the cooling device 3 to which the semiconductor unit 10 is bonded using an adhesive, and the semiconductor units 10 are respectively housed in the unit housing portions 21e, 21f, and 21g of the housing 20. It should be noted that, for example, the first bonding step and the second bonding step may be performed simultaneously.

[0133] Next, a wiring / sealing process (step S6) is performed to wire the semiconductor unit 10 and seal it in the unit storage parts 21e, 21f, and 21g using the sealing member 27. For example, the inner ends of the first connection terminals 22a, 22b, and 22c exposed from the housing 20 to the unit storage parts 21e, 21f, and 21g are bonded to the wiring board 11b1 of the insulating circuit substrate 11 of the semiconductor unit 10 by ultrasonic bonding. Similarly, the inner ends of the second connection terminals 23a, 23b, and 23c are bonded to the wiring board 11b3 of the insulating circuit substrate 11 of the semiconductor unit 10. In addition, similarly, the inner ends of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c are bonded to the wiring board 11b2 of the insulating circuit substrate 11 of the semiconductor unit 10. In addition, the inner ends of the control terminals 25a, 25b, and 25c of the housing 20 are connected to the control electrode 12a of the semiconductor chip 12 using the wire 26. The semiconductor unit 10 is sealed by filling the sealing member 27 in the unit housing portions 21e, 21f, and 21g. Figure 1 and Figure 2 A semiconductor device 1 is shown.

[0134] Here, a semiconductor device of a reference example is described. The semiconductor device of the reference example is a device obtained by removing the support portion 15 from the semiconductor device 1, and is otherwise composed of the same components as the semiconductor device 1. Fig.17 Here, the Fig.19 and Fig. 20 The setting step (step S2 ) and the first bonding step (step S3 ) of the manufacturing method in the case of the reference example will be described. Fig.19 This is a diagram illustrating a setting step included in the method for manufacturing a semiconductor device according to a reference example. Fig. 20 It is a diagram for explaining a first bonding step included in the method for manufacturing a semiconductor device according to a reference example.

[0135] The semiconductor chip 12 is placed on the insulating circuit substrate 11, and a placement process of placing the lead frames 13a and 13b in sequence is performed (step S2). Fig.18 As shown, the semiconductor chip 12 is arranged only via the bonding member 14a on the wiring board 11b2 of the insulating circuit substrate 11. In addition, the main electrode bonding portion 13a1 of the lead frame 13a is arranged on the main electrode 12b of the semiconductor chip 12 via the bonding member 14b.

[0136] After that, the first joining process (step S3) of heating and joining these to form the semiconductor unit 10 is performed. As described above, the insulating circuit substrate 11 is warped by heating. For example, the linear expansion coefficients of the wiring boards 11b1 to 11b3 and the metal plate 11c are different from those of the insulating plate 11a. In addition, the volumes of the wiring boards 11b1 to 11b3 and the metal plate 11c formed on the front and back sides of the insulating plate 11a are different. Therefore, as an example of warping in the reference example, Figures 5 to 8 As shown, Figure 4 The following describes a case where the vertices 16a to 16d of the side surfaces 11a1 to 11a4 of the insulating circuit substrate 11 are vertices and warping occurs as an example.

[0137] For example, in Figure 3 The semiconductor unit 10 at the dot-dash line XX (corresponding to the side view viewed in the +X direction) produces Fig. 20 The insulating circuit substrate 11 is warped as shown. That is, the insulating circuit substrate 11 is warped with the vertex 16b as the vertex convex downward. In addition, the bonding components 14a and 14b are melted by heating. At this time, the semiconductor chip 12 arranged in the bonding area 11d of the wiring board 11b2 tilted by the warping will be tilted due to the melting of the bonding component 14a. It should be noted that since the main electrode bonding part 13a1 of the lead frame 13a has a boss 13a6 formed on the back, it is maintained approximately parallel to the semiconductor chip 12.

[0138] If the bonding member 14a is cured in such an inclined state and the semiconductor chip 12 is bonded to the wiring board 11b2, the thickness of the bonding member 14a cannot be uniform, resulting in thin parts and thick parts. That is, the side of the bonding member 14a close to the vertex 16b becomes thinner, and the side away from the vertex 16b becomes thicker.

[0139] In the thin part of the bonding component 14a, cracks are easily generated due to external stress. In addition, the heat dissipation of the thick part of the bonding component 14a is lower than that of the thin part. The inclusion of such a bonding component 14a with uneven thickness will lead to a reduction in the reliability of the semiconductor device.

[0140] In addition, for example, in a side view obtained by observing the semiconductor unit 10 in the -X direction, as shown in FIG. Fig.10 As shown, the vertex 16d is formed right below the center region of the semiconductor chip 12. In this case, the semiconductor chip 12 is substantially parallel to the wiring board 11b1, the thickness of the bonding member 14a becomes substantially uniform, and cracks are unlikely to occur.

[0141] Therefore, the semiconductor device described above includes a semiconductor chip 12 and an insulating circuit substrate 11, which includes a wiring board 11b2 on the front side and is warped to protrude downward with the back side set as the bottom side, and the semiconductor chip 12 is bonded to the bonding area 11d on the upper surface of the wiring board 11b2 inclined on the front side due to the warping via a bonding component 14a. At this time, the semiconductor chip 12 is bonded to the bonding area 11d in a manner that the end of the insulating circuit substrate 11 on the side of the warping vertex 16b on the back side of the semiconductor chip 12 is supported by the support portion 15 provided in the bonding area 11d. At this time, the semiconductor chip 12 is roughly parallel to the bonding area 11d of the wiring board 11b2 by the support portion 15, and the thickness of the bonding component 14a becomes roughly uniform. Therefore, the generation of cracks relative to the bonding component 14a is reduced. In addition, the deviation caused by the position of the thermal conductivity of the bonding component 14a is also reduced. As a result, the reliability of the semiconductor device 1 is prevented from being reduced. In addition, the support portion 15 is preferably formed to correspond to the two corners on the vertex 16b side of the semiconductor chip 12 with respect to the bonding area 11d on the upper surface of the wiring board 11b2. With such a structure, the semiconductor chip 12 is substantially parallel to the bonding area 11d of the wiring board 11b2 using the support portion 15, and the posture substantially parallel to the bonding area 11d can be made more stable.

[0142] It should be explained, such as Figure 4 As shown in FIG. 1 , the warping of the insulating circuit substrate 11 occurs not only at the vertex 16b, but also at the vertex 16a, 16c, and 16d. Fig.12 The vertices 16b and 16d shown in the figure are generated. It should be noted that, as mentioned above, Fig. 9 Since the vertices 16 b and 16 d are located directly below the center of the semiconductor chip 12 disposed on the bonding region 11 d in a side view, they do not have much influence on the inclination of the semiconductor chip 12 .

[0143] In this embodiment Figure 4 In the embodiment, the support portion 15 is arranged so that the semiconductor chip 12 arranged in the bonding area 11d on the upper surface of the wiring board 11b2 is approximately parallel to the wiring board 11b2, and the wiring board 11b2 is inclined due to the downward convex warping with the vertex 16b as the vertex when viewed from the side.

[0144] In addition, Figure 4In the embodiment, the support portion 15 can be arranged on the side 11a4 (vertices 16a and 16c) of the bonding region 11d of the wiring board 11b2 relative to the wiring board 11b2 which is tilted due to the downwardly convex warping with the vertices 16a and 16c as the vertices when viewed from the side. In addition, the support portion 15 can be appropriately arranged in the bonding region 11d according to the direction of the warping of the wiring board 11b2 so that the semiconductor chip 12 becomes substantially parallel to the wiring board 11b2.

[0145] In addition, in this embodiment Figure 4 In the embodiment, support portion 15 is arranged so that semiconductor chip 12 arranged in bonding region 11d on the upper surface of wiring board 11b1 is approximately parallel to wiring board 11b1 which is inclined by a downwardly convex warp with vertex 16d as the vertex when viewed from the side.

[0146] In addition, in this embodiment Fig.12 In the figure, the support portion 15 is arranged so that the semiconductor chip 12 arranged in the bonding area 11d on the upper surface of the wiring boards 11b1 and 11b2 is roughly parallel to the wiring boards 11b1 and 11b2, and the wiring boards 11b1 and 11b2 are inclined due to the downward convex warping with vertices 16b and 16d as vertices when viewed from the side.

[0147] Here, various forms of the support portion 15 will be described below as modified examples. Figure 4 The following describes the case where the warping with the vertex 16b as the vertex is given as an example. Fig. 9 The warping with vertex 16b as the vertex produces Fig.12 In the case of warping with vertices 16 b and 16 d as vertices, the following modified examples can also be applied to the support portion 15 in the same manner.

[0148] (Variant 1)

[0149] use Fig.21 The support portion 15 according to Modification 1 will be described. Fig.21 FIG. 1 is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (variant 1). Fig.21 (A) shows a top view of the insulating circuit substrate 11 including the support portion 15, Fig.21 (B) shows Fig.21 A cross-sectional view of the dotted line XX of (A). Fig.21 The insulating circuit substrate 11 is formed before warping occurs. Fig.21 The predetermined generation position of the vertex 16b is shown by a dotted circle. Here, only the vertex 16b is shown. Fig.21In (B), the semiconductor chip 12 arranged with respect to the bonding region 11d provided with the support portion 15 is indicated by a dotted line.

[0150] In modification 1, the support portion 15 is provided on the side where the vertex 16b is generated when viewed from the side in the +X direction of the bonding area 11d of the wiring board 11b2. The support portion 15 of modification 1 is rod-shaped when viewed from above. Such a support portion 15 is arranged along the side 11a3 on the side of the bonding area 11d of the wiring board 11b2. The cross-section of the YZ plane of the support portion 15 can be rectangular, triangular, or semicircular. Here, a rectangular case is shown. The height of the support portion 15 in the ±Z direction is preset according to the warping generated.

[0151] In such a wiring board 11b2, when the insulating circuit substrate 11 is warped with the vertex 16b as the vertex and protrudes downward, the semiconductor chip 12 is also substantially parallel to the wiring board 11b2. It should be noted that the example here shows a case where there is only one support portion 15. The support portion 15 is not limited to one, and a plurality of rows may be arranged parallel to the side surfaces 11a1 and 11a3. Fig.21 As shown, the support parts 15 are not limited to the case of being in a continuous rod shape. The support parts 15 may be arranged in one or more rows in a dotted line in parallel with the side surfaces 11a1 and 11a3.

[0152] In addition, depending on the occurrence of warpage, for example, for warpage that is convex downward with vertices 16a and 16c as vertices, such support portion 15 may be arranged along side surface 11a4 of bonding region 11d of wiring board 11b2.

[0153] (Variant 2)

[0154] use Fig. 22 The support portion 15 according to Modification 2 will be described. Fig. 22 FIG. 1 is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (variant 2). Fig. 22 (A) shows a top view of the insulating circuit substrate 11 including the support portion 15, Fig. 22 (B) shows Fig. 22 A cross-sectional view of (A) at the dotted line YY. Fig. 22 The insulating circuit substrate 11 is also formed before warping occurs. Fig. 22 The predetermined generation position of the middle apex 16b is shown by a dotted circle.

[0155] In the second modification, the support portion 15 is provided on the side where the vertex 16b is formed when viewed from the side in the +X direction of the bonding area 11d of the wiring board 11b2. The support portion 15 of the second modification is composed of a conductive wire. Here, the conductive wires are formed near the corners of the bonding area 11d of the wiring board 11b2 on the vertex 16b side when viewed from the side. The case where the conductive wires are arranged parallel to the side surfaces 11a1 and 11a3 is illustrated. In addition, the height of the support portion 15 in the ±Z direction is preset according to the warping that occurs.

[0156] In such a wiring board 11b2, when the insulating circuit substrate 11 is warped downward with the vertex 16b as the vertex, the semiconductor chip 12 is also substantially parallel to the wiring board 11b2. The support portion 15 is preferably formed along the side of the vertex 16b side of the semiconductor chip 12 with respect to the bonding area 11d of the wiring board 11b2. In addition, the support portion 15 is preferably formed corresponding to the two corners on the vertex 16b side of the semiconductor chip 12 with respect to the bonding area 11d on the upper surface of the wiring board 11b2. The semiconductor chip 12 is substantially parallel to the bonding area 11d of the wiring board 11b2 by the support portion 15, and the posture substantially parallel to the bonding area 11d can be made more stable. It should be noted that here, the case where there are two support portions 15 arranged in a row is illustrated. The support portion 15 is not limited to two, and one or more support portions 15 may be connected from the end of the side 11a2 side of the bonding area 11d to the end of the side 11a4 side. In addition, such support parts 15 may be formed in multiple rows near the side 11a3. In this case, the support parts 15 in multiple rows may be formed so that the height increases as they approach the side 11a3. In addition, depending on the occurrence of warping, for example, they may be formed along the side 11a2, 11a4, or on the diagonal line of the bonding area 11d. Since they are wires, they have a high degree of freedom in formation and can be appropriately formed at a desired location.

[0157] (Variant 3)

[0158] use Fig.23 The support portion 15 according to Modification 3 will be described. Fig.23 FIG. 1 is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (Variant 3). Fig.23 (A) shows a top view of the insulating circuit substrate 11 including the support portion 15, Fig.23 (B) shows Fig.23 A cross-sectional view of (A) at the dotted line YY. Fig.23 The insulating circuit substrate 11 is also formed before warping occurs. Fig.23 The predetermined generation position of the middle apex 16b is shown by a dotted circle.

[0159] In modification 3, the support portion 15 is provided on the side where the vertex 16b is generated when viewed from the side in the +X direction of the bonding area 11d of the wiring board 11b2. The support portion 15 of modification 3 is a roughened (roughened) area of ​​the front surface of the wiring board 11b2. It should be noted that the roughening treatment may be, for example, laser, sandblasting, or roughening plating. The case where the roughened support portion 15 is parallel to the side surfaces 11a1 and 11a3 and is arranged near the corner of the bonding area 11d is illustrated. In addition, the height of the support portion 15 in the ±Z direction is preset according to the warping generated.

[0160] In such a wiring board 11b2, when the insulating circuit substrate 11 is warped with the vertex 16b as the vertex and convex downward, the semiconductor chip 12 is also roughly parallel to the wiring board 11b2. In addition, it is preferred that the support portion 15 is formed corresponding to the two corners on the vertex 16b side of the semiconductor chip 12 with respect to the bonding area 11d on the upper surface of the wiring board 11b2. With such a structure, the semiconductor chip 12 is roughly parallel to the bonding area 11d of the wiring board 11b2 using the support portion 15, and the posture roughly parallel to the bonding area 11d can be made more stable. It should be noted that here, the case where the support portion 15 is two parts and arranged in one row is illustrated. Such a support portion 15 is not limited to two parts, and can also be a linear shape from the end of the side 11a2 side of the bonding area 11d to the end of the side 11a4 side with one part or more. In addition, such a support portion 15 can be formed in multiple rows on the side of the bonding area 11d included in the wiring board 11b2 close to the side 11a3. In addition, depending on the occurrence of warpage, for example, it can be formed along the side surfaces 11a2 and 11a4 or on the diagonal line of the bonding region 11d. Since the support portion 15 is formed by roughening, the degree of freedom in formation is high and it can be formed appropriately at a desired location.

[0161] (Variant 4)

[0162] use Fig.24 The support portion 15 according to Modification 4 will be described. Fig.24 FIG. 1 is a diagram showing an insulating circuit substrate included in a semiconductor device according to an embodiment (Variant 4). Fig.24 (A) shows a top view of the insulating circuit substrate 11 including the support portion 15, Fig.24 (B) shows Fig.24 A cross-sectional view of the dotted line XX of (A). Fig.24 The insulating circuit substrate 11 is also formed before warping occurs. Fig.24 The predetermined generation position of the middle vertex 16b is shown by a dotted circle. Fig.24In (B), the semiconductor chip 12 arranged with respect to the bonding region 11d provided with the support portion 15 is indicated by a dotted line.

[0163] In variant 4, the support portion 15 is rectangular in a plan view and is arranged at half of the +Y direction of the bonding area 11d of the wiring board 11b2. The front of the support portion 15 is inclined in such a manner that the height of the side where the vertex 16b is generated when the bonding area 11d of the wiring board 11b2 is viewed from the side in the +X direction becomes higher. That is, the front of the support portion 15 is inclined in such a manner that the height of the side close to the vertex 16b when the bonding area 11d of the wiring board 11b2 is viewed from the side in the +X direction is higher than the height of the side away from the vertex 16b. Here, the inclination angle of the support portion 15 is also preset according to the warping that occurs. In addition, the length of the support portion 15 in the ±Y direction and the length of the ±X direction are also preset according to the warping that occurs.

[0164] In such a wiring board 11b2, when the insulating circuit substrate 11 is warped with the vertex 16b as the vertex and bulges downward, the back surface of the semiconductor chip 12 is also supported by the support portion 15 to be approximately parallel to the wiring board 11b2. By such a support portion 15, the back surface of the inclined semiconductor chip 12 is stably supported. In addition, it is preferred that the support portion 15 is formed along the side of the semiconductor chip 12 on the side close to the vertex 16b with respect to the bonding area 11d of the wiring board 11b2. With such a structure, the semiconductor chip 12 is approximately parallel to the bonding area 11d of the wiring board 11b2 by the support portion 15, and the posture approximately parallel to the bonding area 11d can be made more stable.

[0165] It should be noted that the case where there is one support portion 15 along the side surfaces 11a1 and 11a3 is illustrated here. The support portion 15 including the inclination is not limited to one, and a plurality of support portions 15 may be arranged in a row along the side surfaces 11a1 and 11a3. When there are a plurality of support portions 15, the bonding member 14a enters between them, and the contact area between the support portion 15 and the bonding member 14a increases, so that the bonding region 11d and the semiconductor chip 12 can be bonded more reliably.

[0166] The above only illustrates the principle of the present invention. For those skilled in the art, a large number of modifications and changes can be further made. The present invention is not limited to the accurate configuration and application examples shown and described above, and all corresponding modifications and equivalents are regarded as the scope of the present invention based on the attached claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor chips; as well as A substrate including a wiring board on the front side, which is warped so as to protrude downward with the back side being the bottom side, wherein a semiconductor chip is bonded to a bonding area on the upper surface of the wiring board which is tilted on the front side due to the warping via a first bonding member, The semiconductor chip is bonded to the bonding region such that an end portion of the back surface of the semiconductor chip located on a vertex side of the warpage of the substrate is supported by a support portion provided in the bonding region.

2. The semiconductor device according to claim 1, wherein: The semiconductor chip is substantially parallel to the bonding region of the wiring board.

3. The semiconductor device according to claim 1, wherein: The support portion is formed on the vertex side of the bonding region of the wiring board and has a protruding shape.

4. The semiconductor device according to claim 3, wherein: The supporting portion is formed in plurality on the vertex side of the bonding region of the wiring board.

5. The semiconductor device according to claim 4, wherein: The semiconductor chip is rectangular in plan view. The support portion is formed to correspond to two corner portions on the vertex side of the semiconductor chip with respect to the bonding region of the wiring board, respectively.

6. The semiconductor device according to claim 1, wherein: The support portion is formed in the bonding region of the wiring board and includes an inclined surface that is inclined so that a side close to the apex is higher than a side far from the apex in a side view.

7. The semiconductor device according to claim 6, wherein: The semiconductor chip is rectangular in plan view. The support portion is formed along a side on the vertex side of the semiconductor chip with respect to the bonding region of the wiring board.

8. The semiconductor device according to claim 1, wherein: The support portion is a roughened region in which the vertex side of the bonding region of the wiring board is roughened.

9. The semiconductor device according to claim 8, wherein: The support portion includes a plurality of the roughened regions.

10. The semiconductor device according to claim 9, wherein: The semiconductor chip is rectangular in plan view. The support portion is formed to correspond to two corner portions on the vertex side of the semiconductor chip with respect to the bonding region of the wiring board, respectively.

11. The semiconductor device according to claim 1, wherein: The support portion is a conductive line formed on the vertex side of the bonding region of the wiring board.

12. The semiconductor device according to claim 11, wherein: The semiconductor chip is rectangular in plan view. The support portion is formed along a side on the vertex side of the semiconductor chip with respect to the bonding region of the wiring board.

13. The semiconductor device according to claim 12, wherein: The support portion is formed to correspond to two corner portions on the vertex side of the semiconductor chip with respect to the bonding region of the wiring board, respectively.

14. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a wiring member having a flat plate-shaped bonding portion that is bonded to the main electrode on the front surface of the semiconductor chip via a second bonding member.

15. The semiconductor device according to claim 14, wherein: The joining portion of the wiring member is substantially parallel to the front surface of the semiconductor chip.

16. The semiconductor device according to claim 14, wherein: A protrusion is formed on a bonding surface of the bonding portion that is bonded to the main electrode of the semiconductor chip.

Images